[deliverable/linux.git] / drivers / ide / pci / atiixp.c

/*
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

typedef struct {
	u8 command_width;
	u8 recover_width;
} atiixp_ide_timing;

static atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode.
 */

static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 pio_timing_data;
	u16 pio_mode_data;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a ATIIXP host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 tmp32;
	u16 tmp16;
	u16 udma_ctl = 0;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);

	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);

		udma_ctl |= (1 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0) {
		u8 i = speed & 0x03;

		pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
		tmp32 &= ~(0xff << timing_shift);
		tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
			 (mdma_timing[i].command_width << (timing_shift + 4));
		pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);

		udma_ctl &= ~(1 << drive->dn);
	}

	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

static u8 __devinit atiixp_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u8 udma_mode = 0, ch = hwif->channel;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);

	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops atiixp_port_ops = {
	.set_pio_mode		= atiixp_set_pio_mode,
	.set_dma_mode		= atiixp_set_dma_mode,
	.cable_detect		= atiixp_cable_detect,
};

static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
	{	/* 0 */
		.name		= "ATIIXP",
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.port_ops	= &atiixp_port_ops,
		.host_flags	= IDE_HFLAG_LEGACY_IRQS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 1 */
		.name		= "SB600_PATA",
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
		.port_ops	= &atiixp_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
}

static const struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(atiixp_ide_init);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
485efc6c	3	* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	4	*/
1da177e4 LT	5
1da177e4 LT	6	#include <linux/types.h>
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
1da177e4 LT	9	#include <linux/pci.h>
	10	#include <linux/hdreg.h>
	11	#include <linux/ide.h>
1da177e4 LT	12	#include <linux/init.h>
1da177e4 LT	13
1da177e4 LT	14	#define ATIIXP_IDE_PIO_TIMING 0x40
	15	#define ATIIXP_IDE_MDMA_TIMING 0x44
	16	#define ATIIXP_IDE_PIO_CONTROL 0x48
	17	#define ATIIXP_IDE_PIO_MODE 0x4a
	18	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	19	#define ATIIXP_IDE_UDMA_MODE 0x56
	20
	21	typedef struct {
	22	u8 command_width;
	23	u8 recover_width;
	24	} atiixp_ide_timing;
	25
	26	static atiixp_ide_timing pio_timing[] = {
	27	{ 0x05, 0x0d },
	28	{ 0x04, 0x07 },
	29	{ 0x03, 0x04 },
	30	{ 0x02, 0x02 },
	31	{ 0x02, 0x00 },
	32	};
	33
	34	static atiixp_ide_timing mdma_timing[] = {
	35	{ 0x07, 0x07 },
	36	{ 0x02, 0x01 },
	37	{ 0x02, 0x00 },
	38	};
	39
6c5f8cc3 A	40	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 A	41
1da177e4	42	/**
88b2b32b BZ	43	* atiixp_set_pio_mode - set host controller for PIO mode
	44	* @drive: drive
	45	* @pio: PIO mode number
1da177e4 LT	46	*
	47	* Set the interface PIO mode.
	48	*/
	49
88b2b32b	50	static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	51	{
36501650	52	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4 LT	53	unsigned long flags;
	54	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	55	u32 pio_timing_data;
	56	u16 pio_mode_data;
	57
6c5f8cc3	58	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	59
	60	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	61	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	62	pio_mode_data \|= (pio << (drive->dn * 4));
	63	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	64
	65	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	66	pio_timing_data &= ~(0xff << timing_shift);
	67	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	68	(pio_timing[pio].command_width << (timing_shift + 4));
	69	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	70
6c5f8cc3	71	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	72	}
	73
	74	/**
88b2b32b BZ	75	* atiixp_set_dma_mode - set host controller for DMA mode
	76	* @drive: drive
	77	* @speed: DMA mode
1da177e4	78	*
88b2b32b BZ	79	* Set a ATIIXP host controller to the desired DMA mode. This involves
88b2b32b BZ	80	* programming the right timing data into the PCI configuration space.
1da177e4 LT	81	*/
1da177e4 LT	82
88b2b32b	83	static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	84	{
36501650	85	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4 LT	86	unsigned long flags;
	87	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	88	u32 tmp32;
	89	u16 tmp16;
8ae60e34	90	u16 udma_ctl = 0;
94c7fa0f	91
6c5f8cc3	92	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4	93
8ae60e34 BZ	94	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
8ae60e34 BZ	95
1da177e4 LT	96	if (speed >= XFER_UDMA_0) {
	97	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	98	tmp16 &= ~(0x07 << (drive->dn * 4));
	99	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	100	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
8ae60e34 BZ	101
	102	udma_ctl \|= (1 << drive->dn);
	103	} else if (speed >= XFER_MW_DMA_0) {
	104	u8 i = speed & 0x03;
	105
	106	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	107	tmp32 &= ~(0xff << timing_shift);
	108	tmp32 \|= (mdma_timing[i].recover_width << timing_shift) \|
	109	(mdma_timing[i].command_width << (timing_shift + 4));
	110	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	111
	112	udma_ctl &= ~(1 << drive->dn);
1da177e4 LT	113	}
1da177e4 LT	114
8ae60e34 BZ	115	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
8ae60e34 BZ	116
6c5f8cc3	117	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	118	}
1da177e4 LT	119
b4d1c73d BZ	120	static u8 __devinit atiixp_cable_detect(ide_hwif_t *hwif)
	121	{
	122	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	123	u8 udma_mode = 0, ch = hwif->channel;
	124
	125	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
	126
	127	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
	128	return ATA_CBL_PATA80;
	129	else
	130	return ATA_CBL_PATA40;
	131	}
	132
ac95beed BZ	133	static const struct ide_port_ops atiixp_port_ops = {
	134	.set_pio_mode = atiixp_set_pio_mode,
	135	.set_dma_mode = atiixp_set_dma_mode,
	136	.cable_detect = atiixp_cable_detect,
	137	};
1da177e4	138
85620436	139	static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
1da177e4 LT	140	{ /* 0 */
1da177e4 LT	141	.name = "ATIIXP",
1da177e4	142	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
ac95beed	143	.port_ops = &atiixp_port_ops,
5e71d9c5	144	.host_flags = IDE_HFLAG_LEGACY_IRQS,
4099d143	145	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	146	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	147	.udma_mask = ATA_UDMA5,
b25168df CH	148	},{ /* 1 */
b25168df CH	149	.name = "SB600_PATA",
b25168df	150	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
ac95beed	151	.port_ops = &atiixp_port_ops,
5e71d9c5	152	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_LEGACY_IRQS,
4099d143	153	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	154	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	155	.udma_mask = ATA_UDMA5,
b25168df	156	},
1da177e4 LT	157	};
	158
	159	/**
	160	* atiixp_init_one - called when a ATIIXP is found
	161	* @dev: the atiixp device
	162	* @id: the matching pci id
	163	*
	164	* Called when the PCI registration layer (or the IDE initialization)
	165	* finds a device matching our IDE device tables.
	166	*/
	167
	168	static int __devinit atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
	169	{
6cdf6eb3	170	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
1da177e4 LT	171	}
1da177e4 LT	172
9cbcc5e3 BZ	173	static const struct pci_device_id atiixp_pci_tbl[] = {
	174	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	175	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	176	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	177	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	178	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
1da177e4 LT	179	{ 0, },
	180	};
	181	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	182
	183	static struct pci_driver driver = {
	184	.name = "ATIIXP_IDE",
	185	.id_table = atiixp_pci_tbl,
	186	.probe = atiixp_init_one,
	187	};
	188
82ab1eec	189	static int __init atiixp_ide_init(void)
1da177e4 LT	190	{
	191	return ide_pci_register_driver(&driver);
	192	}
	193
	194	module_init(atiixp_ide_init);
	195
	196	MODULE_AUTHOR("HUI YU");
	197	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	198	MODULE_LICENSE("GPL");