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[PATCH] clockevents: Fix suspend/resume to disk hangs
[deliverable/linux.git] / drivers / ide / pci / cmd64x.c
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1da177e4
LT		 1/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2 *
f92d50e6 3 * linux/drivers/ide/pci/cmd64x.c Version 1.41 Feb 3, 2007
1da177e4
LT		 4 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
10 *
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
13 *
14 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
f92d50e6 15 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 16 */
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/pci.h>
21#include <linux/delay.h>
22#include <linux/hdreg.h>
23#include <linux/ide.h>
24#include <linux/init.h>
25
26#include <asm/io.h>
27
28#define DISPLAY_CMD64X_TIMINGS
29
30#define CMD_DEBUG 0
31
32#if CMD_DEBUG
33#define cmdprintk(x...) printk(x)
34#else
35#define cmdprintk(x...)
36#endif
37
38/*
39 * CMD64x specific registers definition.
40 */
41#define CFR 0x50
42#define CFR_INTR_CH0 0x02
43#define CNTRL 0x51
44#define CNTRL_DIS_RA0 0x40
45#define CNTRL_DIS_RA1 0x80
46#define CNTRL_ENA_2ND 0x08
47
48#define CMDTIM 0x52
49#define ARTTIM0 0x53
50#define DRWTIM0 0x54
51#define ARTTIM1 0x55
52#define DRWTIM1 0x56
53#define ARTTIM23 0x57
54#define ARTTIM23_DIS_RA2 0x04
55#define ARTTIM23_DIS_RA3 0x08
56#define ARTTIM23_INTR_CH1 0x10
57#define ARTTIM2 0x57
58#define ARTTIM3 0x57
59#define DRWTIM23 0x58
60#define DRWTIM2 0x58
61#define BRST 0x59
62#define DRWTIM3 0x5b
63
64#define BMIDECR0 0x70
65#define MRDMODE 0x71
66#define MRDMODE_INTR_CH0 0x04
67#define MRDMODE_INTR_CH1 0x08
68#define MRDMODE_BLK_CH0 0x10
69#define MRDMODE_BLK_CH1 0x20
70#define BMIDESR0 0x72
71#define UDIDETCR0 0x73
72#define DTPR0 0x74
73#define BMIDECR1 0x78
74#define BMIDECSR 0x79
75#define BMIDESR1 0x7A
76#define UDIDETCR1 0x7B
77#define DTPR1 0x7C
78
79#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
80#include <linux/stat.h>
81#include <linux/proc_fs.h>
82
83static u8 cmd64x_proc = 0;
84
85#define CMD_MAX_DEVS 5
86
87static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
88static int n_cmd_devs;
89
90static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91{
92 char *p = buf;
93
94 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
95 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
96 u8 reg72 = 0, reg73 = 0; /* primary */
97 u8 reg7a = 0, reg7b = 0; /* secondary */
98 u8 reg50 = 0, reg71 = 0; /* extra */
99
100 p += sprintf(p, "\nController: %d\n", index);
101 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
102 (void) pci_read_config_byte(dev, CFR, &reg50);
103 (void) pci_read_config_byte(dev, ARTTIM0, &reg53);
104 (void) pci_read_config_byte(dev, DRWTIM0, &reg54);
105 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
106 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
107 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
108 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
109 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
110 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
111 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
112 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
114 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115
116 p += sprintf(p, "--------------- Primary Channel "
117 "---------------- Secondary Channel "
118 "-------------\n");
119 p += sprintf(p, " %sabled "
120 " %sabled\n",
121 (reg72&0x80)?"dis":" en",
122 (reg7a&0x80)?"dis":" en");
123 p += sprintf(p, "--------------- drive0 "
124 "--------- drive1 -------- drive0 "
125 "---------- drive1 ------\n");
126 p += sprintf(p, "DMA enabled: %s %s"
127 " %s %s\n",
128 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
129 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
130
131 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
132 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
133 (reg72&0x20)?(
134 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
135 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
136 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
137 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
138 "X"):"?",
139 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
140 (reg72&0x40)?(
141 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
142 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
143 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
144 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
145 "X"):"?");
146 p += sprintf(p, " %s(%s) %s(%s)\n",
147 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
148 (reg7a&0x20)?(
149 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
150 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
151 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
152 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
153 "X"):"?",
154 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
155 (reg7a&0x40)?(
156 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
157 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
158 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
159 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
160 "X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s"
162 " %s %s\n",
163 "?", "?", "?", "?");
164 p += sprintf(p, " %s %s\n",
165 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
166 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
169 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170 p += sprintf(p, " %s %s\n",
171 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173
174 return (char *)p;
175}
176
177static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
178{
179 char *p = buffer;
180 int i;
181
182 p += sprintf(p, "\n");
183 for (i = 0; i < n_cmd_devs; i++) {
184 struct pci_dev *dev = cmd_devs[i];
185 p = print_cmd64x_get_info(p, dev, i);
186 }
187 return p-buffer; /* => must be less than 4k! */
188}
189
190#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
191
1da177e4
LT		 192/*
193 * This routine writes the prepared setup/active/recovery counts
194 * for a drive into the cmd646 chipset registers to active them.
195 */
196static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
197{
198 unsigned long flags;
199 struct pci_dev *dev = HWIF(drive)->pci_dev;
200 ide_drive_t *drives = HWIF(drive)->drives;
201 u8 temp_b;
202 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
203 static const u8 recovery_counts[] =
204 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
205 static const u8 arttim_regs[2][2] = {
206 { ARTTIM0, ARTTIM1 },
207 { ARTTIM23, ARTTIM23 }
208 };
209 static const u8 drwtim_regs[2][2] = {
210 { DRWTIM0, DRWTIM1 },
211 { DRWTIM2, DRWTIM3 }
212 };
213 int channel = (int) HWIF(drive)->channel;
214 int slave = (drives != drive); /* Is this really the best way to determine this?? */
215
216 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
217 setup_count, active_count, recovery_count, drive->present);
218 /*
219 * Set up address setup count registers.
220 * Primary interface has individual count/timing registers for
221 * each drive. Secondary interface has one common set of registers,
222 * for address setup so we merge these timings, using the slowest
223 * value.
224 */
225 if (channel) {
226 drive->drive_data = setup_count;
227 setup_count = max(drives[0].drive_data,
228 drives[1].drive_data);
229 cmdprintk("Secondary interface, setup_count = %d\n",
230 setup_count);
231 }
232
233 /*
234 * Convert values to internal chipset representation
235 */
236 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
237 active_count &= 0xf; /* Remember, max value is 16 */
238 recovery_count = (int) recovery_counts[recovery_count];
239
240 cmdprintk("Final values = %d,%d,%d\n",
241 setup_count, active_count, recovery_count);
242
243 /*
244 * Now that everything is ready, program the new timings
245 */
246 local_irq_save(flags);
247 /*
248 * Program the address_setup clocks into ARTTIM reg,
249 * and then the active/recovery counts into the DRWTIM reg
250 */
251 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
252 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
253 ((u8) setup_count) | (temp_b & 0x3f));
254 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
255 (u8) ((active_count << 4) | recovery_count));
256 cmdprintk ("Write %x to %x\n",
257 ((u8) setup_count) | (temp_b & 0x3f),
258 arttim_regs[channel][slave]);
259 cmdprintk ("Write %x to %x\n",
260 (u8) ((active_count << 4) | recovery_count),
261 drwtim_regs[channel][slave]);
262 local_irq_restore(flags);
263}
264
265/*
f92d50e6
SS		 266 * This routine selects drive's best PIO mode, calculates setup/active/recovery
267 * counts, and then writes them into the chipset registers.
1da177e4 268 */
f92d50e6 269static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
1da177e4
LT		 270{
271 int setup_time, active_time, recovery_time;
272 int clock_time, pio_mode, cycle_time;
273 u8 recovery_count2, cycle_count;
274 int setup_count, active_count, recovery_count;
275 int bus_speed = system_bus_clock();
1da177e4
LT		 276 ide_pio_data_t d;
277
f92d50e6 278 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &d);
1da177e4
LT		 279 cycle_time = d.cycle_time;
280
281 /*
282 * I copied all this complicated stuff from cmd640.c and made a few
283 * minor changes. For now I am just going to pray that it is correct.
284 */
1da177e4
LT		 285 setup_time = ide_pio_timings[pio_mode].setup_time;
286 active_time = ide_pio_timings[pio_mode].active_time;
287 recovery_time = cycle_time - (setup_time + active_time);
288 clock_time = 1000 / bus_speed;
289 cycle_count = (cycle_time + clock_time - 1) / clock_time;
290
291 setup_count = (setup_time + clock_time - 1) / clock_time;
292
293 active_count = (active_time + clock_time - 1) / clock_time;
294
295 recovery_count = (recovery_time + clock_time - 1) / clock_time;
296 recovery_count2 = cycle_count - (setup_count + active_count);
297 if (recovery_count2 > recovery_count)
298 recovery_count = recovery_count2;
299 if (recovery_count > 16) {
300 active_count += recovery_count - 16;
301 recovery_count = 16;
302 }
303 if (active_count > 16)
304 active_count = 16; /* maximum allowed by cmd646 */
305
1da177e4
LT		 306 program_drive_counts (drive, setup_count, active_count, recovery_count);
307
f92d50e6 308 cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, "
1da177e4 309 "clocks=%d/%d/%d\n",
f92d50e6 310 drive->name, mode_wanted, pio_mode, cycle_time,
1da177e4
LT		 311 d.overridden ? " (overriding vendor mode)" : "",
312 setup_count, active_count, recovery_count);
f92d50e6
SS		 313
314 return pio_mode;
315}
316
317/*
318 * Attempts to set drive's PIO mode.
319 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
320 * and 255: auto-select best mode (used at boot time).
321 */
322static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
323{
324 /*
325 * Filter out the prefetch control values
326 * to prevent PIO5 from being programmed
327 */
328 if (pio == 8 || pio == 9)
329 return;
330
331 pio = cmd64x_tune_pio(drive, pio);
332 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 333}
334
335static u8 cmd64x_ratemask (ide_drive_t *drive)
336{
337 struct pci_dev *dev = HWIF(drive)->pci_dev;
338 u8 mode = 0;
339
340 switch(dev->device) {
341 case PCI_DEVICE_ID_CMD_649:
342 mode = 3;
343 break;
344 case PCI_DEVICE_ID_CMD_648:
345 mode = 2;
346 break;
347 case PCI_DEVICE_ID_CMD_643:
348 return 0;
349
350 case PCI_DEVICE_ID_CMD_646:
351 {
352 unsigned int class_rev = 0;
353 pci_read_config_dword(dev,
354 PCI_CLASS_REVISION, &class_rev);
355 class_rev &= 0xff;
356 /*
357 * UltraDMA only supported on PCI646U and PCI646U2, which
358 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
359 * Actually, although the CMD tech support people won't
360 * tell me the details, the 0x03 revision cannot support
361 * UDMA correctly without hardware modifications, and even
362 * then it only works with Quantum disks due to some
363 * hold time assumptions in the 646U part which are fixed
364 * in the 646U2.
365 *
366 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
367 */
368 switch(class_rev) {
369 case 0x07:
370 case 0x05:
371 return 1;
372 case 0x03:
373 case 0x01:
374 default:
375 return 0;
376 }
377 }
378 }
379 if (!eighty_ninty_three(drive))
380 mode = min(mode, (u8)1);
381 return mode;
382}
383
1da177e4
LT		 384static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
385{
386 ide_hwif_t *hwif = HWIF(drive);
387 struct pci_dev *dev = hwif->pci_dev;
388
389 u8 unit = (drive->select.b.unit & 0x01);
390 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
391 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
392
393 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
394
f92d50e6 395 if (speed >= XFER_SW_DMA_0) {
1da177e4
LT		 396 (void) pci_read_config_byte(dev, pciD, &regD);
397 (void) pci_read_config_byte(dev, pciU, &regU);
398 regD &= ~(unit ? 0x40 : 0x20);
399 regU &= ~(unit ? 0xCA : 0x35);
400 (void) pci_write_config_byte(dev, pciD, regD);
401 (void) pci_write_config_byte(dev, pciU, regU);
402 (void) pci_read_config_byte(dev, pciD, &regD);
403 (void) pci_read_config_byte(dev, pciU, &regU);
404 }
405
406 switch(speed) {
407 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
408 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
409 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
410 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
411 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
412 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
413 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
414 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
415 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
416 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
417 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
418 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
f92d50e6
SS		 419 case XFER_PIO_5:
420 case XFER_PIO_4:
421 case XFER_PIO_3:
422 case XFER_PIO_2:
423 case XFER_PIO_1:
424 case XFER_PIO_0:
425 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
426 break;
1da177e4
LT		 427
428 default:
429 return 1;
430 }
431
f92d50e6 432 if (speed >= XFER_SW_DMA_0) {
1da177e4
LT		 433 (void) pci_write_config_byte(dev, pciU, regU);
434 regD |= (unit ? 0x40 : 0x20);
435 (void) pci_write_config_byte(dev, pciD, regD);
436 }
437
438 return (ide_config_drive_speed(drive, speed));
439}
440
441static int config_chipset_for_dma (ide_drive_t *drive)
442{
443 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
444
1da177e4
LT		 445 if (!speed)
446 return 0;
447
056a697b
BZ		 448 if (cmd64x_tune_chipset(drive, speed))
449 return 0;
1da177e4
LT		 450
451 return ide_dma_enable(drive);
452}
453
454static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
455{
7569e8dc 456 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
3608b5d7 457 return 0;
1da177e4 458
d8f4469d 459 if (ide_use_fast_pio(drive))
f92d50e6 460 cmd64x_tune_drive(drive, 255);
d8f4469d 461
3608b5d7 462 return -1;
1da177e4
LT		 463}
464
465static int cmd64x_alt_dma_status (struct pci_dev *dev)
466{
467 switch(dev->device) {
468 case PCI_DEVICE_ID_CMD_648:
469 case PCI_DEVICE_ID_CMD_649:
470 return 1;
471 default:
472 break;
473 }
474 return 0;
475}
476
477static int cmd64x_ide_dma_end (ide_drive_t *drive)
478{
479 u8 dma_stat = 0, dma_cmd = 0;
480 ide_hwif_t *hwif = HWIF(drive);
481 struct pci_dev *dev = hwif->pci_dev;
482
483 drive->waiting_for_dma = 0;
484 /* read DMA command state */
0ecdca26 485 dma_cmd = inb(hwif->dma_command);
1da177e4 486 /* stop DMA */
0ecdca26 487 outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 488 /* get DMA status */
0ecdca26 489 dma_stat = inb(hwif->dma_status);
1da177e4 490 /* clear the INTR & ERROR bits */
0ecdca26 491 outb(dma_stat | 6, hwif->dma_status);
1da177e4
LT		 492 if (cmd64x_alt_dma_status(dev)) {
493 u8 dma_intr = 0;
494 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
495 CFR_INTR_CH0;
496 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
497 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
498 /* clear the INTR bit */
499 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
500 }
501 /* purge DMA mappings */
502 ide_destroy_dmatable(drive);
503 /* verify good DMA status */
504 return (dma_stat & 7) != 4;
505}
506
507static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
508{
509 ide_hwif_t *hwif = HWIF(drive);
510 struct pci_dev *dev = hwif->pci_dev;
511 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
512 MRDMODE_INTR_CH0;
0ecdca26 513 u8 dma_stat = inb(hwif->dma_status);
1da177e4
LT		 514
515 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
516#ifdef DEBUG
517 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
518 "0x%02x mask: 0x%02x\n", drive->name,
519 dma_stat, dma_alt_stat, mask);
520#endif
521 if (!(dma_alt_stat & mask))
522 return 0;
523
524 /* return 1 if INTR asserted */
525 if ((dma_stat & 4) == 4)
526 return 1;
527
528 return 0;
529}
530
531/*
532 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
533 * event order for DMA transfers.
534 */
535
536static int cmd646_1_ide_dma_end (ide_drive_t *drive)
537{
538 ide_hwif_t *hwif = HWIF(drive);
539 u8 dma_stat = 0, dma_cmd = 0;
540
541 drive->waiting_for_dma = 0;
542 /* get DMA status */
0ecdca26 543 dma_stat = inb(hwif->dma_status);
1da177e4 544 /* read DMA command state */
0ecdca26 545 dma_cmd = inb(hwif->dma_command);
1da177e4 546 /* stop DMA */
0ecdca26 547 outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 548 /* clear the INTR & ERROR bits */
0ecdca26 549 outb(dma_stat | 6, hwif->dma_status);
1da177e4
LT		 550 /* and free any DMA resources */
551 ide_destroy_dmatable(drive);
552 /* verify good DMA status */
553 return (dma_stat & 7) != 4;
554}
555
556static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
557{
558 u32 class_rev = 0;
559 u8 mrdmode = 0;
560
561 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
562 class_rev &= 0xff;
563
1da177e4
LT		 564 switch(dev->device) {
565 case PCI_DEVICE_ID_CMD_643:
566 break;
567 case PCI_DEVICE_ID_CMD_646:
568 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
569 switch(class_rev) {
570 case 0x07:
571 case 0x05:
572 printk("UltraDMA Capable");
573 break;
574 case 0x03:
575 printk("MultiWord DMA Force Limited");
576 break;
577 case 0x01:
578 default:
579 printk("MultiWord DMA Limited, IRQ workaround enabled");
580 break;
581 }
582 printk("\n");
583 break;
584 case PCI_DEVICE_ID_CMD_648:
585 case PCI_DEVICE_ID_CMD_649:
586 break;
587 default:
588 break;
589 }
590
591 /* Set a good latency timer and cache line size value. */
592 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
593 /* FIXME: pci_set_master() to ensure a good latency timer value */
594
595 /* Setup interrupts. */
596 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
597 mrdmode &= ~(0x30);
598 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
599
600 /* Use MEMORY READ LINE for reads.
601 * NOTE: Although not mentioned in the PCI0646U specs,
602 * these bits are write only and won't be read
603 * back as set or not. The PCI0646U2 specs clarify
604 * this point.
605 */
606 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
607
608 /* Set reasonable active/recovery/address-setup values. */
609 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
610 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
611 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
612 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
613#ifdef __i386__
614 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
615#else
616 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
617#endif
618 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
619 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
620#ifdef CONFIG_PPC
621 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
622#endif /* CONFIG_PPC */
623
624#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
625
626 cmd_devs[n_cmd_devs++] = dev;
627
628 if (!cmd64x_proc) {
629 cmd64x_proc = 1;
630 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
631 }
632#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
633
634 return 0;
635}
636
637static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
638{
639 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
640
641 switch(hwif->pci_dev->device) {
642 case PCI_DEVICE_ID_CMD_643:
643 case PCI_DEVICE_ID_CMD_646:
644 return ata66;
645 default:
646 break;
647 }
648 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
649 return (ata66 & mask) ? 1 : 0;
650}
651
652static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
653{
654 struct pci_dev *dev = hwif->pci_dev;
655 unsigned int class_rev;
656
657 hwif->autodma = 0;
658 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
659 class_rev &= 0xff;
660
f92d50e6 661 hwif->tuneproc = &cmd64x_tune_drive;
1da177e4
LT		 662 hwif->speedproc = &cmd64x_tune_chipset;
663
f92d50e6
SS		 664 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
665
666 if (!hwif->dma_base)
1da177e4 667 return;
1da177e4
LT		 668
669 hwif->atapi_dma = 1;
670
671 hwif->ultra_mask = 0x3f;
672 hwif->mwdma_mask = 0x07;
673 hwif->swdma_mask = 0x07;
674
675 if (dev->device == PCI_DEVICE_ID_CMD_643)
676 hwif->ultra_mask = 0x80;
677 if (dev->device == PCI_DEVICE_ID_CMD_646)
678 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
679 if (dev->device == PCI_DEVICE_ID_CMD_648)
680 hwif->ultra_mask = 0x1f;
681
682 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
683 if (!(hwif->udma_four))
684 hwif->udma_four = ata66_cmd64x(hwif);
685
686 if (dev->device == PCI_DEVICE_ID_CMD_646) {
687 hwif->chipset = ide_cmd646;
688 if (class_rev == 0x01) {
689 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
690 } else {
691 hwif->ide_dma_end = &cmd64x_ide_dma_end;
692 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
693 }
694 } else {
695 hwif->ide_dma_end = &cmd64x_ide_dma_end;
696 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
697 }
698
699
700 if (!noautodma)
701 hwif->autodma = 1;
702 hwif->drives[0].autodma = hwif->autodma;
703 hwif->drives[1].autodma = hwif->autodma;
704}
705
706static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
707 { /* 0 */
708 .name = "CMD643",
709 .init_chipset = init_chipset_cmd64x,
710 .init_hwif = init_hwif_cmd64x,
711 .channels = 2,
712 .autodma = AUTODMA,
713 .bootable = ON_BOARD,
714 },{ /* 1 */
715 .name = "CMD646",
716 .init_chipset = init_chipset_cmd64x,
717 .init_hwif = init_hwif_cmd64x,
718 .channels = 2,
719 .autodma = AUTODMA,
720 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
721 .bootable = ON_BOARD,
722 },{ /* 2 */
723 .name = "CMD648",
724 .init_chipset = init_chipset_cmd64x,
725 .init_hwif = init_hwif_cmd64x,
726 .channels = 2,
727 .autodma = AUTODMA,
728 .bootable = ON_BOARD,
729 },{ /* 3 */
730 .name = "CMD649",
731 .init_chipset = init_chipset_cmd64x,
732 .init_hwif = init_hwif_cmd64x,
733 .channels = 2,
734 .autodma = AUTODMA,
735 .bootable = ON_BOARD,
736 }
737};
738
739static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
740{
741 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
742}
743
744static struct pci_device_id cmd64x_pci_tbl[] = {
745 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
746 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
747 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
748 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
749 { 0, },
750};
751MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
752
753static struct pci_driver driver = {
754 .name = "CMD64x_IDE",
755 .id_table = cmd64x_pci_tbl,
756 .probe = cmd64x_init_one,
757};
758
82ab1eec 759static int __init cmd64x_ide_init(void)
1da177e4
LT		 760{
761 return ide_pci_register_driver(&driver);
762}
763
764module_init(cmd64x_ide_init);
765
766MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
767MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
768MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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