Commit | Line | Data |
---|---|---|
60e7a82f | 1 | /* |
1da177e4 | 2 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
1da177e4 LT |
3 | * Due to massive hardware bugs, UltraDMA is only supported |
4 | * on the 646U2 and not on the 646U. | |
5 | * | |
6 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
7 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
8 | * | |
9 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
f92d50e6 | 10 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
11 | */ |
12 | ||
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/pci.h> | |
1da177e4 LT |
16 | #include <linux/hdreg.h> |
17 | #include <linux/ide.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | ||
1da177e4 LT |
22 | #define CMD_DEBUG 0 |
23 | ||
24 | #if CMD_DEBUG | |
25 | #define cmdprintk(x...) printk(x) | |
26 | #else | |
27 | #define cmdprintk(x...) | |
28 | #endif | |
29 | ||
30 | /* | |
31 | * CMD64x specific registers definition. | |
32 | */ | |
33 | #define CFR 0x50 | |
e51e2528 | 34 | #define CFR_INTR_CH0 0x04 |
1da177e4 LT |
35 | |
36 | #define CMDTIM 0x52 | |
37 | #define ARTTIM0 0x53 | |
38 | #define DRWTIM0 0x54 | |
39 | #define ARTTIM1 0x55 | |
40 | #define DRWTIM1 0x56 | |
41 | #define ARTTIM23 0x57 | |
42 | #define ARTTIM23_DIS_RA2 0x04 | |
43 | #define ARTTIM23_DIS_RA3 0x08 | |
44 | #define ARTTIM23_INTR_CH1 0x10 | |
1da177e4 LT |
45 | #define DRWTIM2 0x58 |
46 | #define BRST 0x59 | |
47 | #define DRWTIM3 0x5b | |
48 | ||
49 | #define BMIDECR0 0x70 | |
50 | #define MRDMODE 0x71 | |
51 | #define MRDMODE_INTR_CH0 0x04 | |
52 | #define MRDMODE_INTR_CH1 0x08 | |
1da177e4 LT |
53 | #define UDIDETCR0 0x73 |
54 | #define DTPR0 0x74 | |
55 | #define BMIDECR1 0x78 | |
56 | #define BMIDECSR 0x79 | |
1da177e4 LT |
57 | #define UDIDETCR1 0x7B |
58 | #define DTPR1 0x7C | |
59 | ||
e277a1aa SS |
60 | static u8 quantize_timing(int timing, int quant) |
61 | { | |
62 | return (timing + quant - 1) / quant; | |
63 | } | |
64 | ||
1da177e4 | 65 | /* |
60e7a82f SS |
66 | * This routine calculates active/recovery counts and then writes them into |
67 | * the chipset registers. | |
1da177e4 | 68 | */ |
60e7a82f | 69 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
1da177e4 | 70 | { |
36501650 | 71 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
60e7a82f SS |
72 | int clock_time = 1000 / system_bus_clock(); |
73 | u8 cycle_count, active_count, recovery_count, drwtim; | |
74 | static const u8 recovery_values[] = | |
1da177e4 | 75 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
60e7a82f SS |
76 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
77 | ||
78 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", | |
79 | cycle_time, active_time); | |
80 | ||
81 | cycle_count = quantize_timing( cycle_time, clock_time); | |
82 | active_count = quantize_timing(active_time, clock_time); | |
83 | recovery_count = cycle_count - active_count; | |
84 | ||
1da177e4 | 85 | /* |
60e7a82f SS |
86 | * In case we've got too long recovery phase, try to lengthen |
87 | * the active phase | |
1da177e4 | 88 | */ |
60e7a82f SS |
89 | if (recovery_count > 16) { |
90 | active_count += recovery_count - 16; | |
91 | recovery_count = 16; | |
1da177e4 | 92 | } |
60e7a82f SS |
93 | if (active_count > 16) /* shouldn't actually happen... */ |
94 | active_count = 16; | |
95 | ||
96 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", | |
97 | cycle_count, active_count, recovery_count); | |
1da177e4 LT |
98 | |
99 | /* | |
100 | * Convert values to internal chipset representation | |
101 | */ | |
60e7a82f SS |
102 | recovery_count = recovery_values[recovery_count]; |
103 | active_count &= 0x0f; | |
1da177e4 | 104 | |
60e7a82f SS |
105 | /* Program the active/recovery counts into the DRWTIM register */ |
106 | drwtim = (active_count << 4) | recovery_count; | |
107 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); | |
108 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); | |
1da177e4 LT |
109 | } |
110 | ||
111 | /* | |
26bcb879 BZ |
112 | * This routine writes into the chipset registers |
113 | * PIO setup/active/recovery timings. | |
1da177e4 | 114 | */ |
26bcb879 | 115 | static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) |
1da177e4 | 116 | { |
60e7a82f | 117 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 118 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
7dd00083 | 119 | unsigned int cycle_time; |
26bcb879 BZ |
120 | u8 setup_count, arttim = 0; |
121 | ||
60e7a82f SS |
122 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; |
123 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; | |
7dd00083 | 124 | |
26bcb879 | 125 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 | 126 | |
7dd00083 | 127 | program_cycle_times(drive, cycle_time, |
26bcb879 | 128 | ide_pio_timings[pio].active_time); |
1da177e4 | 129 | |
26bcb879 | 130 | setup_count = quantize_timing(ide_pio_timings[pio].setup_time, |
60e7a82f SS |
131 | 1000 / system_bus_clock()); |
132 | ||
133 | /* | |
134 | * The primary channel has individual address setup timing registers | |
135 | * for each drive and the hardware selects the slowest timing itself. | |
136 | * The secondary channel has one common register and we have to select | |
137 | * the slowest address setup timing ourselves. | |
138 | */ | |
139 | if (hwif->channel) { | |
140 | ide_drive_t *drives = hwif->drives; | |
141 | ||
142 | drive->drive_data = setup_count; | |
143 | setup_count = max(drives[0].drive_data, drives[1].drive_data); | |
1da177e4 | 144 | } |
1da177e4 | 145 | |
60e7a82f SS |
146 | if (setup_count > 5) /* shouldn't actually happen... */ |
147 | setup_count = 5; | |
148 | cmdprintk("Final address setup count: %d\n", setup_count); | |
1da177e4 | 149 | |
60e7a82f SS |
150 | /* |
151 | * Program the address setup clocks into the ARTTIM registers. | |
152 | * Avoid clearing the secondary channel's interrupt bit. | |
153 | */ | |
154 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); | |
155 | if (hwif->channel) | |
156 | arttim &= ~ARTTIM23_INTR_CH1; | |
157 | arttim &= ~0xc0; | |
158 | arttim |= setup_values[setup_count]; | |
159 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); | |
160 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); | |
f92d50e6 SS |
161 | } |
162 | ||
163 | /* | |
164 | * Attempts to set drive's PIO mode. | |
26bcb879 | 165 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked) |
f92d50e6 | 166 | */ |
26bcb879 BZ |
167 | |
168 | static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
f92d50e6 SS |
169 | { |
170 | /* | |
171 | * Filter out the prefetch control values | |
172 | * to prevent PIO5 from being programmed | |
173 | */ | |
174 | if (pio == 8 || pio == 9) | |
175 | return; | |
176 | ||
26bcb879 | 177 | cmd64x_tune_pio(drive, pio); |
1da177e4 LT |
178 | } |
179 | ||
88b2b32b | 180 | static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
181 | { |
182 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 183 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
60e7a82f SS |
184 | u8 unit = drive->dn & 0x01; |
185 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; | |
1da177e4 | 186 | |
f92d50e6 | 187 | if (speed >= XFER_SW_DMA_0) { |
1da177e4 | 188 | (void) pci_read_config_byte(dev, pciU, ®U); |
1da177e4 | 189 | regU &= ~(unit ? 0xCA : 0x35); |
1da177e4 LT |
190 | } |
191 | ||
192 | switch(speed) { | |
60e7a82f SS |
193 | case XFER_UDMA_5: |
194 | regU |= unit ? 0x0A : 0x05; | |
195 | break; | |
196 | case XFER_UDMA_4: | |
197 | regU |= unit ? 0x4A : 0x15; | |
198 | break; | |
199 | case XFER_UDMA_3: | |
200 | regU |= unit ? 0x8A : 0x25; | |
201 | break; | |
202 | case XFER_UDMA_2: | |
203 | regU |= unit ? 0x42 : 0x11; | |
204 | break; | |
205 | case XFER_UDMA_1: | |
206 | regU |= unit ? 0x82 : 0x21; | |
207 | break; | |
208 | case XFER_UDMA_0: | |
209 | regU |= unit ? 0xC2 : 0x31; | |
210 | break; | |
211 | case XFER_MW_DMA_2: | |
212 | program_cycle_times(drive, 120, 70); | |
213 | break; | |
214 | case XFER_MW_DMA_1: | |
215 | program_cycle_times(drive, 150, 80); | |
216 | break; | |
217 | case XFER_MW_DMA_0: | |
218 | program_cycle_times(drive, 480, 215); | |
219 | break; | |
1da177e4 LT |
220 | } |
221 | ||
60e7a82f | 222 | if (speed >= XFER_SW_DMA_0) |
1da177e4 | 223 | (void) pci_write_config_byte(dev, pciU, regU); |
1da177e4 LT |
224 | } |
225 | ||
5e37bdc0 | 226 | static int cmd648_dma_end(ide_drive_t *drive) |
1da177e4 | 227 | { |
66602c83 | 228 | ide_hwif_t *hwif = HWIF(drive); |
1c029fd6 | 229 | unsigned long base = hwif->dma_base - (hwif->channel * 8); |
66602c83 SS |
230 | int err = __ide_dma_end(drive); |
231 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | |
232 | MRDMODE_INTR_CH0; | |
1c029fd6 | 233 | u8 mrdmode = inb(base + 1); |
66602c83 SS |
234 | |
235 | /* clear the interrupt bit */ | |
6183289c | 236 | outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask, |
1c029fd6 | 237 | base + 1); |
66602c83 SS |
238 | |
239 | return err; | |
1da177e4 LT |
240 | } |
241 | ||
5e37bdc0 | 242 | static int cmd64x_dma_end(ide_drive_t *drive) |
1da177e4 | 243 | { |
1da177e4 | 244 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 245 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
66602c83 SS |
246 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
247 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
248 | CFR_INTR_CH0; | |
249 | u8 irq_stat = 0; | |
250 | int err = __ide_dma_end(drive); | |
1da177e4 | 251 | |
66602c83 SS |
252 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
253 | /* clear the interrupt bit */ | |
254 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); | |
255 | ||
256 | return err; | |
257 | } | |
258 | ||
5e37bdc0 | 259 | static int cmd648_dma_test_irq(ide_drive_t *drive) |
66602c83 SS |
260 | { |
261 | ide_hwif_t *hwif = HWIF(drive); | |
1c029fd6 | 262 | unsigned long base = hwif->dma_base - (hwif->channel * 8); |
66602c83 SS |
263 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
264 | MRDMODE_INTR_CH0; | |
265 | u8 dma_stat = inb(hwif->dma_status); | |
1c029fd6 | 266 | u8 mrdmode = inb(base + 1); |
66602c83 SS |
267 | |
268 | #ifdef DEBUG | |
269 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", | |
270 | drive->name, dma_stat, mrdmode, irq_mask); | |
271 | #endif | |
272 | if (!(mrdmode & irq_mask)) | |
273 | return 0; | |
274 | ||
275 | /* return 1 if INTR asserted */ | |
276 | if (dma_stat & 4) | |
277 | return 1; | |
278 | ||
279 | return 0; | |
1da177e4 LT |
280 | } |
281 | ||
5e37bdc0 | 282 | static int cmd64x_dma_test_irq(ide_drive_t *drive) |
1da177e4 | 283 | { |
e51e2528 | 284 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 285 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
66602c83 SS |
286 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
287 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
288 | CFR_INTR_CH0; | |
289 | u8 dma_stat = inb(hwif->dma_status); | |
290 | u8 irq_stat = 0; | |
e51e2528 SS |
291 | |
292 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | |
1da177e4 | 293 | |
1da177e4 | 294 | #ifdef DEBUG |
66602c83 SS |
295 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", |
296 | drive->name, dma_stat, irq_stat, irq_mask); | |
1da177e4 | 297 | #endif |
66602c83 | 298 | if (!(irq_stat & irq_mask)) |
1da177e4 LT |
299 | return 0; |
300 | ||
301 | /* return 1 if INTR asserted */ | |
66602c83 | 302 | if (dma_stat & 4) |
1da177e4 LT |
303 | return 1; |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | /* | |
309 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old | |
310 | * event order for DMA transfers. | |
311 | */ | |
312 | ||
5e37bdc0 | 313 | static int cmd646_1_dma_end(ide_drive_t *drive) |
1da177e4 LT |
314 | { |
315 | ide_hwif_t *hwif = HWIF(drive); | |
316 | u8 dma_stat = 0, dma_cmd = 0; | |
317 | ||
318 | drive->waiting_for_dma = 0; | |
319 | /* get DMA status */ | |
0ecdca26 | 320 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 321 | /* read DMA command state */ |
0ecdca26 | 322 | dma_cmd = inb(hwif->dma_command); |
1da177e4 | 323 | /* stop DMA */ |
0ecdca26 | 324 | outb(dma_cmd & ~1, hwif->dma_command); |
1da177e4 | 325 | /* clear the INTR & ERROR bits */ |
0ecdca26 | 326 | outb(dma_stat | 6, hwif->dma_status); |
1da177e4 LT |
327 | /* and free any DMA resources */ |
328 | ide_destroy_dmatable(drive); | |
329 | /* verify good DMA status */ | |
330 | return (dma_stat & 7) != 4; | |
331 | } | |
332 | ||
333 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) | |
334 | { | |
1da177e4 LT |
335 | u8 mrdmode = 0; |
336 | ||
83a6d4ab | 337 | if (dev->device == PCI_DEVICE_ID_CMD_646) { |
1da177e4 | 338 | |
1afa6554 | 339 | switch (dev->revision) { |
83a6d4ab SS |
340 | case 0x07: |
341 | case 0x05: | |
b37c6b84 | 342 | printk("%s: UltraDMA capable\n", name); |
1da177e4 | 343 | break; |
83a6d4ab | 344 | case 0x03: |
1da177e4 | 345 | default: |
b37c6b84 | 346 | printk("%s: MultiWord DMA force limited\n", name); |
83a6d4ab SS |
347 | break; |
348 | case 0x01: | |
349 | printk("%s: MultiWord DMA limited, " | |
350 | "IRQ workaround enabled\n", name); | |
1da177e4 | 351 | break; |
83a6d4ab | 352 | } |
1da177e4 LT |
353 | } |
354 | ||
355 | /* Set a good latency timer and cache line size value. */ | |
356 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
357 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | |
358 | ||
83a6d4ab SS |
359 | /* |
360 | * Enable interrupts, select MEMORY READ LINE for reads. | |
361 | * | |
362 | * NOTE: although not mentioned in the PCI0646U specs, | |
363 | * bits 0-1 are write only and won't be read back as | |
364 | * set or not -- PCI0646U2 specs clarify this point. | |
1da177e4 | 365 | */ |
83a6d4ab SS |
366 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
367 | mrdmode &= ~0x30; | |
368 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); | |
1da177e4 | 369 | |
1da177e4 LT |
370 | return 0; |
371 | } | |
372 | ||
ac95beed | 373 | static u8 __devinit cmd64x_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 374 | { |
36501650 | 375 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
83a6d4ab | 376 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; |
1da177e4 | 377 | |
83a6d4ab SS |
378 | switch (dev->device) { |
379 | case PCI_DEVICE_ID_CMD_648: | |
380 | case PCI_DEVICE_ID_CMD_649: | |
381 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); | |
49521f97 | 382 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
83a6d4ab | 383 | default: |
49521f97 | 384 | return ATA_CBL_PATA40; |
1da177e4 | 385 | } |
1da177e4 LT |
386 | } |
387 | ||
ac95beed BZ |
388 | static const struct ide_port_ops cmd64x_port_ops = { |
389 | .set_pio_mode = cmd64x_set_pio_mode, | |
390 | .set_dma_mode = cmd64x_set_dma_mode, | |
391 | .cable_detect = cmd64x_cable_detect, | |
392 | }; | |
393 | ||
f37afdac BZ |
394 | static const struct ide_dma_ops cmd64x_dma_ops = { |
395 | .dma_host_set = ide_dma_host_set, | |
396 | .dma_setup = ide_dma_setup, | |
397 | .dma_exec_cmd = ide_dma_exec_cmd, | |
398 | .dma_start = ide_dma_start, | |
5e37bdc0 BZ |
399 | .dma_end = cmd64x_dma_end, |
400 | .dma_test_irq = cmd64x_dma_test_irq, | |
f37afdac BZ |
401 | .dma_lost_irq = ide_dma_lost_irq, |
402 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
403 | }; |
404 | ||
f37afdac BZ |
405 | static const struct ide_dma_ops cmd646_rev1_dma_ops = { |
406 | .dma_host_set = ide_dma_host_set, | |
407 | .dma_setup = ide_dma_setup, | |
408 | .dma_exec_cmd = ide_dma_exec_cmd, | |
409 | .dma_start = ide_dma_start, | |
5e37bdc0 | 410 | .dma_end = cmd646_1_dma_end, |
f37afdac BZ |
411 | .dma_test_irq = ide_dma_test_irq, |
412 | .dma_lost_irq = ide_dma_lost_irq, | |
413 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
414 | }; |
415 | ||
f37afdac BZ |
416 | static const struct ide_dma_ops cmd648_dma_ops = { |
417 | .dma_host_set = ide_dma_host_set, | |
418 | .dma_setup = ide_dma_setup, | |
419 | .dma_exec_cmd = ide_dma_exec_cmd, | |
420 | .dma_start = ide_dma_start, | |
5e37bdc0 BZ |
421 | .dma_end = cmd648_dma_end, |
422 | .dma_test_irq = cmd648_dma_test_irq, | |
f37afdac BZ |
423 | .dma_lost_irq = ide_dma_lost_irq, |
424 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
425 | }; |
426 | ||
85620436 | 427 | static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { |
1da177e4 LT |
428 | { /* 0 */ |
429 | .name = "CMD643", | |
430 | .init_chipset = init_chipset_cmd64x, | |
7accbffd | 431 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
ac95beed | 432 | .port_ops = &cmd64x_port_ops, |
5e37bdc0 | 433 | .dma_ops = &cmd64x_dma_ops, |
8ac2b42a | 434 | .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | |
5e71d9c5 | 435 | IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 436 | .pio_mask = ATA_PIO5, |
5f8b6c34 | 437 | .mwdma_mask = ATA_MWDMA2, |
18137207 | 438 | .udma_mask = 0x00, /* no udma */ |
1da177e4 LT |
439 | },{ /* 1 */ |
440 | .name = "CMD646", | |
441 | .init_chipset = init_chipset_cmd64x, | |
7accbffd | 442 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
deffca11 | 443 | .chipset = ide_cmd646, |
ac95beed | 444 | .port_ops = &cmd64x_port_ops, |
5e37bdc0 | 445 | .dma_ops = &cmd648_dma_ops, |
5e71d9c5 | 446 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 447 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
448 | .mwdma_mask = ATA_MWDMA2, |
449 | .udma_mask = ATA_UDMA2, | |
1da177e4 LT |
450 | },{ /* 2 */ |
451 | .name = "CMD648", | |
452 | .init_chipset = init_chipset_cmd64x, | |
7accbffd | 453 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
ac95beed | 454 | .port_ops = &cmd64x_port_ops, |
5e37bdc0 | 455 | .dma_ops = &cmd648_dma_ops, |
5e71d9c5 | 456 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 457 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
458 | .mwdma_mask = ATA_MWDMA2, |
459 | .udma_mask = ATA_UDMA4, | |
1da177e4 LT |
460 | },{ /* 3 */ |
461 | .name = "CMD649", | |
462 | .init_chipset = init_chipset_cmd64x, | |
7accbffd | 463 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
ac95beed | 464 | .port_ops = &cmd64x_port_ops, |
5e37bdc0 | 465 | .dma_ops = &cmd648_dma_ops, |
5e71d9c5 | 466 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 467 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
468 | .mwdma_mask = ATA_MWDMA2, |
469 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
470 | } |
471 | }; | |
472 | ||
473 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
474 | { | |
039788e1 | 475 | struct ide_port_info d; |
bfd314a3 BZ |
476 | u8 idx = id->driver_data; |
477 | ||
478 | d = cmd64x_chipsets[idx]; | |
479 | ||
5e37bdc0 BZ |
480 | if (idx == 1) { |
481 | /* | |
482 | * UltraDMA only supported on PCI646U and PCI646U2, which | |
483 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. | |
484 | * Actually, although the CMD tech support people won't | |
485 | * tell me the details, the 0x03 revision cannot support | |
486 | * UDMA correctly without hardware modifications, and even | |
487 | * then it only works with Quantum disks due to some | |
488 | * hold time assumptions in the 646U part which are fixed | |
489 | * in the 646U2. | |
490 | * | |
491 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | |
492 | */ | |
493 | if (dev->revision < 5) { | |
494 | d.udma_mask = 0x00; | |
495 | /* | |
496 | * The original PCI0646 didn't have the primary | |
497 | * channel enable bit, it appeared starting with | |
498 | * PCI0646U (i.e. revision ID 3). | |
499 | */ | |
500 | if (dev->revision < 3) { | |
501 | d.enablebits[0].reg = 0; | |
502 | if (dev->revision == 1) | |
503 | d.dma_ops = &cmd646_rev1_dma_ops; | |
504 | else | |
505 | d.dma_ops = &cmd64x_dma_ops; | |
506 | } | |
507 | } | |
508 | } | |
7accbffd | 509 | |
bfd314a3 | 510 | return ide_setup_pci_device(dev, &d); |
1da177e4 LT |
511 | } |
512 | ||
9cbcc5e3 BZ |
513 | static const struct pci_device_id cmd64x_pci_tbl[] = { |
514 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, | |
515 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, | |
516 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 }, | |
517 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 }, | |
1da177e4 LT |
518 | { 0, }, |
519 | }; | |
520 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); | |
521 | ||
522 | static struct pci_driver driver = { | |
523 | .name = "CMD64x_IDE", | |
524 | .id_table = cmd64x_pci_tbl, | |
525 | .probe = cmd64x_init_one, | |
526 | }; | |
527 | ||
82ab1eec | 528 | static int __init cmd64x_ide_init(void) |
1da177e4 LT |
529 | { |
530 | return ide_pci_register_driver(&driver); | |
531 | } | |
532 | ||
533 | module_init(cmd64x_ide_init); | |
534 | ||
535 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); | |
536 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); | |
537 | MODULE_LICENSE("GPL"); |