[deliverable/linux.git] / drivers / ide / pci / cs5520.c

/*
 *	IDE tuning and bus mastering support for the CS5510/CS5520
 *	chipsets
 *
 *	The CS5510/CS5520 are slightly unusual devices. Unlike the 
 *	typical IDE controllers they do bus mastering with the drive in
 *	PIO mode and smarter silicon.
 *
 *	The practical upshot of this is that we must always tune the
 *	drive for the right PIO mode. We must also ignore all the blacklists
 *	and the drive bus mastering DMA information.
 *
 *	*** This driver is strictly experimental ***
 *
 *	(c) Copyright Red Hat Inc 2002
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * For the avoidance of doubt the "preferred form" of this code is one which
 * is in an open non patent encumbered format. Where cryptographic key signing
 * forms part of the process of creating an executable the information
 * including keys needed to generate an equivalently functional executable
 * are deemed to be part of the source code.
 *
 */
 
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>

#include <asm/io.h>
#include <asm/irq.h>

struct pio_clocks
{
	int address;
	int assert;
	int recovery;
};

static struct pio_clocks cs5520_pio_clocks[]={
	{3, 6, 11},
	{2, 5, 6},
	{1, 4, 3},
	{1, 3, 2},
	{1, 2, 1}
};

static int cs5520_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *pdev = hwif->pci_dev;
	int pio = speed;
	u8 reg;
	int controller = drive->dn > 1 ? 1 : 0;

	switch(speed)
	{
		case XFER_PIO_4:
		case XFER_PIO_3:
		case XFER_PIO_2:
		case XFER_PIO_1:
		case XFER_PIO_0:
			pio -= XFER_PIO_0;
			break;
		default:
			pio = 0;
			printk(KERN_ERR "cs55x0: bad ide timing.\n");
	}
	
	printk("PIO clocking = %d\n", pio);
	
	/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */

	/* 8bit CAT/CRT - 8bit command timing for channel */
	pci_write_config_byte(pdev, 0x62 + controller, 
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));

	/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */

	/* FIXME: should these use address ? */
	/* Data read timing */
	pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));
	/* Write command timing */
	pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));
		
	/* Set the DMA enable/disable flag */
	reg = inb(hwif->dma_base + 0x02 + 8*controller);
	reg |= 1<<((drive->dn&1)+5);
	outb(reg, hwif->dma_base + 0x02 + 8*controller);

	return ide_config_drive_speed(drive, speed);
}

static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	cs5520_tune_chipset(drive, XFER_PIO_0 + pio);
}

static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
{
	/* Tune the drive for PIO modes up to PIO 4 */	
	ide_set_max_pio(drive);

	/* Then tell the core to use DMA operations */
	return 0;
}

/*
 *	We provide a callback for our nonstandard DMA location
 */

static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
{
	unsigned long bmide = pci_resource_start(dev, 2);	/* Not the usual 4 */
	if(hwif->mate && hwif->mate->dma_base)	/* Second channel at primary + 8 */
		bmide += 8;
	ide_setup_dma(hwif, bmide, 8);
}

/*
 *	We wrap the DMA activate to set the vdma flag. This is needed
 *	so that the IDE DMA layer issues PIO not DMA commands over the
 *	DMA channel
 */
 
static int cs5520_dma_on(ide_drive_t *drive)
{
	drive->vdma = 1;
	return 0;
}

static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &cs5520_set_pio_mode;
	hwif->speedproc = &cs5520_tune_chipset;
	hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
	hwif->ide_dma_on = &cs5520_dma_on;

	if(!noautodma)
		hwif->autodma = 1;
	
	if(!hwif->dma_base)
	{
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}

	/* ATAPI is harder so leave it for now */
	hwif->atapi_dma = 0;
	hwif->ultra_mask = 0;
	hwif->swdma_mask = 0;
	hwif->mwdma_mask = 0;
	
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

#define DECLARE_CS_DEV(name_str)				\
	{							\
		.name		= name_str,			\
		.init_setup_dma = cs5520_init_setup_dma,	\
		.init_hwif	= init_hwif_cs5520,		\
		.autodma	= AUTODMA,			\
		.bootable	= ON_BOARD,			\
		.host_flags	= IDE_HFLAG_ISA_PORTS,		\
		.pio_mask	= ATA_PIO4,			\
	}

static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
	/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
};

/*
 *	The 5510/5520 are a bit weird. They don't quite set up the way
 *	the PCI helper layer expects so we must do much of the set up 
 *	work longhand.
 */
 
static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_hwif_t *hwif = NULL, *mate = NULL;
	ata_index_t index;
	ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];

	ide_setup_pci_noise(dev, d);

	/* We must not grab the entire device, it has 'ISA' space in its
	   BARS too and we will freak out other bits of the kernel */
	if (pci_enable_device_bars(dev, 1<<2)) {
		printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
		return -ENODEV;
	}
	pci_set_master(dev);
	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
		printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
		return -ENODEV;
	}

	index.all = 0xf0f0;

	/*
	 *	Now the chipset is configured we can let the core
	 *	do all the device setup for us
	 */

	ide_pci_setup_ports(dev, d, 14, &index);

	if ((index.b.low & 0xf0) != 0xf0)
		hwif = &ide_hwifs[index.b.low];
	if ((index.b.high & 0xf0) != 0xf0)
		mate = &ide_hwifs[index.b.high];

	if (hwif)
		probe_hwif_init(hwif);
	if (mate)
		probe_hwif_init(mate);

	if (hwif)
		ide_proc_register_port(hwif);
	if (mate)
		ide_proc_register_port(mate);

	return 0;
}

static struct pci_device_id cs5520_pci_tbl[] = {
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);

static struct pci_driver driver = {
	.name		= "Cyrix_IDE",
	.id_table	= cs5520_pci_tbl,
	.probe		= cs5520_init_one,
};

static int __init cs5520_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5520_ide_init);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* IDE tuning and bus mastering support for the CS5510/CS5520
	3	* chipsets
	4	*
	5	* The CS5510/CS5520 are slightly unusual devices. Unlike the
	6	* typical IDE controllers they do bus mastering with the drive in
	7	* PIO mode and smarter silicon.
	8	*
	9	* The practical upshot of this is that we must always tune the
	10	* drive for the right PIO mode. We must also ignore all the blacklists
	11	* and the drive bus mastering DMA information.
	12	*
	13	* * This driver is strictly experimental *
	14	*
	15	* (c) Copyright Red Hat Inc 2002
	16	*
	17	* This program is free software; you can redistribute it and/or modify it
	18	* under the terms of the GNU General Public License as published by the
	19	* Free Software Foundation; either version 2, or (at your option) any
	20	* later version.
	21	*
	22	* This program is distributed in the hope that it will be useful, but
	23	* WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	25	* General Public License for more details.
	26	*
	27	* For the avoidance of doubt the "preferred form" of this code is one which
	28	* is in an open non patent encumbered format. Where cryptographic key signing
	29	* forms part of the process of creating an executable the information
	30	* including keys needed to generate an equivalently functional executable
	31	* are deemed to be part of the source code.
	32	*
	33	*/
	34
1da177e4 LT	35	#include <linux/module.h>
	36	#include <linux/types.h>
	37	#include <linux/kernel.h>
	38	#include <linux/delay.h>
	39	#include <linux/timer.h>
	40	#include <linux/mm.h>
	41	#include <linux/ioport.h>
	42	#include <linux/blkdev.h>
	43	#include <linux/hdreg.h>
	44
	45	#include <linux/interrupt.h>
	46	#include <linux/init.h>
	47	#include <linux/pci.h>
	48	#include <linux/ide.h>
	49	#include <linux/dma-mapping.h>
	50
	51	#include <asm/io.h>
	52	#include <asm/irq.h>
	53
	54	struct pio_clocks
	55	{
	56	int address;
	57	int assert;
	58	int recovery;
	59	};
	60
	61	static struct pio_clocks cs5520_pio_clocks[]={
	62	{3, 6, 11},
	63	{2, 5, 6},
	64	{1, 4, 3},
	65	{1, 3, 2},
	66	{1, 2, 1}
	67	};
	68
f212ff28	69	static int cs5520_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4 LT	70	{
	71	ide_hwif_t *hwif = HWIF(drive);
	72	struct pci_dev *pdev = hwif->pci_dev;
1da177e4 LT	73	int pio = speed;
	74	u8 reg;
	75	int controller = drive->dn > 1 ? 1 : 0;
f212ff28	76
1da177e4 LT	77	switch(speed)
	78	{
	79	case XFER_PIO_4:
	80	case XFER_PIO_3:
	81	case XFER_PIO_2:
	82	case XFER_PIO_1:
	83	case XFER_PIO_0:
	84	pio -= XFER_PIO_0;
	85	break;
	86	default:
	87	pio = 0;
	88	printk(KERN_ERR "cs55x0: bad ide timing.\n");
	89	}
	90
	91	printk("PIO clocking = %d\n", pio);
	92
	93	/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
	94
	95	/* 8bit CAT/CRT - 8bit command timing for channel */
	96	pci_write_config_byte(pdev, 0x62 + controller,
	97	(cs5520_pio_clocks[pio].recovery << 4) \|
	98	(cs5520_pio_clocks[pio].assert));
	99
	100	/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
	101
	102	/* FIXME: should these use address ? */
	103	/* Data read timing */
	104	pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
	105	(cs5520_pio_clocks[pio].recovery << 4) \|
	106	(cs5520_pio_clocks[pio].assert));
	107	/* Write command timing */
	108	pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
	109	(cs5520_pio_clocks[pio].recovery << 4) \|
	110	(cs5520_pio_clocks[pio].assert));
	111
	112	/* Set the DMA enable/disable flag */
	113	reg = inb(hwif->dma_base + 0x02 + 8*controller);
	114	reg \|= 1<<((drive->dn&1)+5);
	115	outb(reg, hwif->dma_base + 0x02 + 8*controller);
1da177e4	116
326d72f4 BZ	117	return ide_config_drive_speed(drive, speed);
326d72f4 BZ	118	}
26bcb879 BZ	119
26bcb879 BZ	120	static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	121	{
26bcb879	122	cs5520_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4 LT	123	}
	124
	125	static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
	126	{
1da177e4	127	/* Tune the drive for PIO modes up to PIO 4 */
26bcb879	128	ide_set_max_pio(drive);
3608b5d7	129
1da177e4	130	/* Then tell the core to use DMA operations */
3608b5d7	131	return 0;
1da177e4 LT	132	}
	133
	134	/*
	135	* We provide a callback for our nonstandard DMA location
	136	*/
	137
	138	static void __devinit cs5520_init_setup_dma(struct pci_dev dev, ide_pci_device_t d, ide_hwif_t *hwif)
	139	{
	140	unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
	141	if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
	142	bmide += 8;
	143	ide_setup_dma(hwif, bmide, 8);
	144	}
	145
	146	/*
	147	* We wrap the DMA activate to set the vdma flag. This is needed
	148	* so that the IDE DMA layer issues PIO not DMA commands over the
	149	* DMA channel
	150	*/
	151
	152	static int cs5520_dma_on(ide_drive_t *drive)
	153	{
	154	drive->vdma = 1;
	155	return 0;
	156	}
	157
	158	static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
	159	{
26bcb879	160	hwif->set_pio_mode = &cs5520_set_pio_mode;
1da177e4 LT	161	hwif->speedproc = &cs5520_tune_chipset;
	162	hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
	163	hwif->ide_dma_on = &cs5520_dma_on;
	164
	165	if(!noautodma)
	166	hwif->autodma = 1;
	167
	168	if(!hwif->dma_base)
	169	{
	170	hwif->drives[0].autotune = 1;
	171	hwif->drives[1].autotune = 1;
	172	return;
	173	}
326d72f4 BZ	174
326d72f4 BZ	175	/* ATAPI is harder so leave it for now */
1da177e4 LT	176	hwif->atapi_dma = 0;
	177	hwif->ultra_mask = 0;
	178	hwif->swdma_mask = 0;
	179	hwif->mwdma_mask = 0;
	180
	181	hwif->drives[0].autodma = hwif->autodma;
	182	hwif->drives[1].autodma = hwif->autodma;
	183	}
	184
	185	#define DECLARE_CS_DEV(name_str) \
	186	{ \
	187	.name = name_str, \
	188	.init_setup_dma = cs5520_init_setup_dma, \
	189	.init_hwif = init_hwif_cs5520, \
1da177e4 LT	190	.autodma = AUTODMA, \
1da177e4 LT	191	.bootable = ON_BOARD, \
a5d8c5c8	192	.host_flags = IDE_HFLAG_ISA_PORTS, \
4099d143	193	.pio_mask = ATA_PIO4, \
1da177e4 LT	194	}
	195
	196	static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
	197	/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
	198	/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
	199	};
	200
	201	/*
	202	* The 5510/5520 are a bit weird. They don't quite set up the way
	203	* the PCI helper layer expects so we must do much of the set up
	204	* work longhand.
	205	*/
	206
	207	static int __devinit cs5520_init_one(struct pci_dev dev, const struct pci_device_id id)
	208	{
5cbf79cd	209	ide_hwif_t hwif = NULL, mate = NULL;
1da177e4 LT	210	ata_index_t index;
	211	ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
	212
	213	ide_setup_pci_noise(dev, d);
	214
	215	/* We must not grab the entire device, it has 'ISA' space in its
	216	BARS too and we will freak out other bits of the kernel */
1e39dead	217	if (pci_enable_device_bars(dev, 1<<2)) {
1da177e4	218	printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
1e39dead	219	return -ENODEV;
1da177e4 LT	220	}
	221	pci_set_master(dev);
	222	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
	223	printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
	224	return -ENODEV;
	225	}
	226
	227	index.all = 0xf0f0;
	228
	229	/*
	230	* Now the chipset is configured we can let the core
	231	* do all the device setup for us
	232	*/
	233
	234	ide_pci_setup_ports(dev, d, 14, &index);
	235
5cbf79cd BZ	236	if ((index.b.low & 0xf0) != 0xf0)
	237	hwif = &ide_hwifs[index.b.low];
	238	if ((index.b.high & 0xf0) != 0xf0)
	239	mate = &ide_hwifs[index.b.high];
	240
	241	if (hwif)
	242	probe_hwif_init(hwif);
	243	if (mate)
	244	probe_hwif_init(mate);
	245
	246	if (hwif)
	247	ide_proc_register_port(hwif);
	248	if (mate)
	249	ide_proc_register_port(mate);
	250
1da177e4 LT	251	return 0;
	252	}
	253
	254	static struct pci_device_id cs5520_pci_tbl[] = {
	255	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	256	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	257	{ 0, },
	258	};
	259	MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
	260
	261	static struct pci_driver driver = {
	262	.name = "Cyrix_IDE",
	263	.id_table = cs5520_pci_tbl,
	264	.probe = cs5520_init_one,
	265	};
	266
82ab1eec	267	static int __init cs5520_ide_init(void)
1da177e4 LT	268	{
	269	return ide_pci_register_driver(&driver);
	270	}
	271
	272	module_init(cs5520_ide_init);
	273
	274	MODULE_AUTHOR("Alan Cox");
	275	MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
	276	MODULE_LICENSE("GPL");