[deliverable/linux.git] / drivers / ide / pci / cs5520.c

/*
 *	IDE tuning and bus mastering support for the CS5510/CS5520
 *	chipsets
 *
 *	The CS5510/CS5520 are slightly unusual devices. Unlike the 
 *	typical IDE controllers they do bus mastering with the drive in
 *	PIO mode and smarter silicon.
 *
 *	The practical upshot of this is that we must always tune the
 *	drive for the right PIO mode. We must also ignore all the blacklists
 *	and the drive bus mastering DMA information.
 *
 *	*** This driver is strictly experimental ***
 *
 *	(c) Copyright Red Hat Inc 2002
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * For the avoidance of doubt the "preferred form" of this code is one which
 * is in an open non patent encumbered format. Where cryptographic key signing
 * forms part of the process of creating an executable the information
 * including keys needed to generate an equivalently functional executable
 * are deemed to be part of the source code.
 *
 */
 
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>

#include <asm/io.h>
#include <asm/irq.h>

struct pio_clocks
{
	int address;
	int assert;
	int recovery;
};

static struct pio_clocks cs5520_pio_clocks[]={
	{3, 6, 11},
	{2, 5, 6},
	{1, 4, 3},
	{1, 3, 2},
	{1, 2, 1}
};

static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *pdev = hwif->pci_dev;
	u8 speed = min((u8)XFER_PIO_4, xferspeed);
	int pio = speed;
	u8 reg;
	int controller = drive->dn > 1 ? 1 : 0;
	int error;
	
	switch(speed)
	{
		case XFER_PIO_4:
		case XFER_PIO_3:
		case XFER_PIO_2:
		case XFER_PIO_1:
		case XFER_PIO_0:
			pio -= XFER_PIO_0;
			break;
		default:
			pio = 0;
			printk(KERN_ERR "cs55x0: bad ide timing.\n");
	}
	
	printk("PIO clocking = %d\n", pio);
	
	/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */

	/* 8bit CAT/CRT - 8bit command timing for channel */
	pci_write_config_byte(pdev, 0x62 + controller, 
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));

	/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */

	/* FIXME: should these use address ? */
	/* Data read timing */
	pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));
	/* Write command timing */
	pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
		(cs5520_pio_clocks[pio].recovery << 4) |
		(cs5520_pio_clocks[pio].assert));
		
	/* Set the DMA enable/disable flag */
	reg = inb(hwif->dma_base + 0x02 + 8*controller);
	reg |= 1<<((drive->dn&1)+5);
	outb(reg, hwif->dma_base + 0x02 + 8*controller);
		
	error = ide_config_drive_speed(drive, speed);
	/* ATAPI is harder so leave it for now */
	if(!error && drive->media == ide_disk)
		error = hwif->ide_dma_on(drive);

	return error;
}	
	
static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
}

static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
{
	/* Tune the drive for PIO modes up to PIO 4 */	
	cs5520_tune_drive(drive, 4);

	/* Then tell the core to use DMA operations */
	return 0;
}

/*
 *	We provide a callback for our nonstandard DMA location
 */

static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
{
	unsigned long bmide = pci_resource_start(dev, 2);	/* Not the usual 4 */
	if(hwif->mate && hwif->mate->dma_base)	/* Second channel at primary + 8 */
		bmide += 8;
	ide_setup_dma(hwif, bmide, 8);
}

/*
 *	We wrap the DMA activate to set the vdma flag. This is needed
 *	so that the IDE DMA layer issues PIO not DMA commands over the
 *	DMA channel
 */
 
static int cs5520_dma_on(ide_drive_t *drive)
{
	drive->vdma = 1;
	return 0;
}

static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
{
	hwif->tuneproc = &cs5520_tune_drive;
	hwif->speedproc = &cs5520_tune_chipset;
	hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
	hwif->ide_dma_on = &cs5520_dma_on;

	if(!noautodma)
		hwif->autodma = 1;
	
	if(!hwif->dma_base)
	{
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}
	
	hwif->atapi_dma = 0;
	hwif->ultra_mask = 0;
	hwif->swdma_mask = 0;
	hwif->mwdma_mask = 0;
	
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

#define DECLARE_CS_DEV(name_str)				\
	{							\
		.name		= name_str,			\
		.init_setup_dma = cs5520_init_setup_dma,	\
		.init_hwif	= init_hwif_cs5520,		\
		.channels	= 2,				\
		.autodma	= AUTODMA,			\
		.bootable	= ON_BOARD,			\
		.flags		= IDEPCI_FLAG_ISA_PORTS,	\
	}

static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
	/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
};

/*
 *	The 5510/5520 are a bit weird. They don't quite set up the way
 *	the PCI helper layer expects so we must do much of the set up 
 *	work longhand.
 */
 
static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ata_index_t index;
	ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];

	ide_setup_pci_noise(dev, d);

	/* We must not grab the entire device, it has 'ISA' space in its
	   BARS too and we will freak out other bits of the kernel */
	if (pci_enable_device_bars(dev, 1<<2)) {
		printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
		return -ENODEV;
	}
	pci_set_master(dev);
	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
		printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
		return -ENODEV;
	}

	index.all = 0xf0f0;

	/*
	 *	Now the chipset is configured we can let the core
	 *	do all the device setup for us
	 */

	ide_pci_setup_ports(dev, d, 14, &index);

	if((index.b.low & 0xf0) != 0xf0)
		probe_hwif_init(&ide_hwifs[index.b.low]);
	if((index.b.high & 0xf0) != 0xf0)
		probe_hwif_init(&ide_hwifs[index.b.high]);
	return 0;
}

static struct pci_device_id cs5520_pci_tbl[] = {
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);

static struct pci_driver driver = {
	.name		= "Cyrix_IDE",
	.id_table	= cs5520_pci_tbl,
	.probe		= cs5520_init_one,
};

static int __init cs5520_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5520_ide_init);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* IDE tuning and bus mastering support for the CS5510/CS5520
	3	* chipsets
	4	*
	5	* The CS5510/CS5520 are slightly unusual devices. Unlike the
	6	* typical IDE controllers they do bus mastering with the drive in
	7	* PIO mode and smarter silicon.
	8	*
	9	* The practical upshot of this is that we must always tune the
	10	* drive for the right PIO mode. We must also ignore all the blacklists
	11	* and the drive bus mastering DMA information.
	12	*
	13	* * This driver is strictly experimental *
	14	*
	15	* (c) Copyright Red Hat Inc 2002
	16	*
	17	* This program is free software; you can redistribute it and/or modify it
	18	* under the terms of the GNU General Public License as published by the
	19	* Free Software Foundation; either version 2, or (at your option) any
	20	* later version.
	21	*
	22	* This program is distributed in the hope that it will be useful, but
	23	* WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	25	* General Public License for more details.
	26	*
	27	* For the avoidance of doubt the "preferred form" of this code is one which
	28	* is in an open non patent encumbered format. Where cryptographic key signing
	29	* forms part of the process of creating an executable the information
	30	* including keys needed to generate an equivalently functional executable
	31	* are deemed to be part of the source code.
	32	*
	33	*/
	34
1da177e4 LT	35	#include <linux/module.h>
	36	#include <linux/types.h>
	37	#include <linux/kernel.h>
	38	#include <linux/delay.h>
	39	#include <linux/timer.h>
	40	#include <linux/mm.h>
	41	#include <linux/ioport.h>
	42	#include <linux/blkdev.h>
	43	#include <linux/hdreg.h>
	44
	45	#include <linux/interrupt.h>
	46	#include <linux/init.h>
	47	#include <linux/pci.h>
	48	#include <linux/ide.h>
	49	#include <linux/dma-mapping.h>
	50
	51	#include <asm/io.h>
	52	#include <asm/irq.h>
	53
	54	struct pio_clocks
	55	{
	56	int address;
	57	int assert;
	58	int recovery;
	59	};
	60
	61	static struct pio_clocks cs5520_pio_clocks[]={
	62	{3, 6, 11},
	63	{2, 5, 6},
	64	{1, 4, 3},
	65	{1, 3, 2},
	66	{1, 2, 1}
	67	};
	68
	69	static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
	70	{
	71	ide_hwif_t *hwif = HWIF(drive);
	72	struct pci_dev *pdev = hwif->pci_dev;
	73	u8 speed = min((u8)XFER_PIO_4, xferspeed);
	74	int pio = speed;
	75	u8 reg;
	76	int controller = drive->dn > 1 ? 1 : 0;
	77	int error;
	78
	79	switch(speed)
	80	{
	81	case XFER_PIO_4:
	82	case XFER_PIO_3:
	83	case XFER_PIO_2:
	84	case XFER_PIO_1:
	85	case XFER_PIO_0:
	86	pio -= XFER_PIO_0;
	87	break;
	88	default:
	89	pio = 0;
	90	printk(KERN_ERR "cs55x0: bad ide timing.\n");
	91	}
	92
	93	printk("PIO clocking = %d\n", pio);
	94
	95	/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
	96
	97	/* 8bit CAT/CRT - 8bit command timing for channel */
	98	pci_write_config_byte(pdev, 0x62 + controller,
99	(cs5520_pio_clocks[pio].recovery << 4) \|
100	(cs5520_pio_clocks[pio].assert));
101
102	/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
103
104	/* FIXME: should these use address ? */
105	/* Data read timing */
106	pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
107	(cs5520_pio_clocks[pio].recovery << 4) \|
108	(cs5520_pio_clocks[pio].assert));
109	/* Write command timing */
110	pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
111	(cs5520_pio_clocks[pio].recovery << 4) \|
112	(cs5520_pio_clocks[pio].assert));
113
114	/* Set the DMA enable/disable flag */
115	reg = inb(hwif->dma_base + 0x02 + 8*controller);
116	reg \|= 1<<((drive->dn&1)+5);
117	outb(reg, hwif->dma_base + 0x02 + 8*controller);
118
119	error = ide_config_drive_speed(drive, speed);
120	/* ATAPI is harder so leave it for now */
121	if(!error && drive->media == ide_disk)
122	error = hwif->ide_dma_on(drive);
123
124	return error;
125	}
126
127	static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
128	{
129	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
130	cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
131	}
132
133	static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
134	{
1da177e4 LT	135	/* Tune the drive for PIO modes up to PIO 4 */
1da177e4 LT	136	cs5520_tune_drive(drive, 4);
3608b5d7	137
1da177e4	138	/* Then tell the core to use DMA operations */
3608b5d7	139	return 0;
1da177e4 LT	140	}
	141
	142	/*
	143	* We provide a callback for our nonstandard DMA location
	144	*/
	145
	146	static void __devinit cs5520_init_setup_dma(struct pci_dev dev, ide_pci_device_t d, ide_hwif_t *hwif)
	147	{
	148	unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
	149	if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
	150	bmide += 8;
	151	ide_setup_dma(hwif, bmide, 8);
	152	}
	153
	154	/*
	155	* We wrap the DMA activate to set the vdma flag. This is needed
	156	* so that the IDE DMA layer issues PIO not DMA commands over the
	157	* DMA channel
	158	*/
	159
	160	static int cs5520_dma_on(ide_drive_t *drive)
	161	{
	162	drive->vdma = 1;
	163	return 0;
	164	}
	165
	166	static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
	167	{
	168	hwif->tuneproc = &cs5520_tune_drive;
	169	hwif->speedproc = &cs5520_tune_chipset;
	170	hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
	171	hwif->ide_dma_on = &cs5520_dma_on;
	172
	173	if(!noautodma)
	174	hwif->autodma = 1;
	175
	176	if(!hwif->dma_base)
	177	{
	178	hwif->drives[0].autotune = 1;
	179	hwif->drives[1].autotune = 1;
	180	return;
	181	}
	182
	183	hwif->atapi_dma = 0;
	184	hwif->ultra_mask = 0;
	185	hwif->swdma_mask = 0;
	186	hwif->mwdma_mask = 0;
	187
	188	hwif->drives[0].autodma = hwif->autodma;
	189	hwif->drives[1].autodma = hwif->autodma;
	190	}
	191
	192	#define DECLARE_CS_DEV(name_str) \
	193	{ \
	194	.name = name_str, \
	195	.init_setup_dma = cs5520_init_setup_dma, \
	196	.init_hwif = init_hwif_cs5520, \
	197	.channels = 2, \
	198	.autodma = AUTODMA, \
	199	.bootable = ON_BOARD, \
	200	.flags = IDEPCI_FLAG_ISA_PORTS, \
	201	}
	202
	203	static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
204	/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
205	/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
206	};
207
208	/*
209	* The 5510/5520 are a bit weird. They don't quite set up the way
210	* the PCI helper layer expects so we must do much of the set up
211	* work longhand.
212	*/
213
214	static int __devinit cs5520_init_one(struct pci_dev dev, const struct pci_device_id id)
215	{
216	ata_index_t index;
217	ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
218
219	ide_setup_pci_noise(dev, d);
220
221	/* We must not grab the entire device, it has 'ISA' space in its
222	BARS too and we will freak out other bits of the kernel */
1e39dead	223	if (pci_enable_device_bars(dev, 1<<2)) {
1da177e4	224	printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
1e39dead	225	return -ENODEV;
1da177e4 LT	226	}
	227	pci_set_master(dev);
	228	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
	229	printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
	230	return -ENODEV;
	231	}
	232
	233	index.all = 0xf0f0;
	234
	235	/*
	236	* Now the chipset is configured we can let the core
	237	* do all the device setup for us
	238	*/
	239
	240	ide_pci_setup_ports(dev, d, 14, &index);
	241
	242	if((index.b.low & 0xf0) != 0xf0)
	243	probe_hwif_init(&ide_hwifs[index.b.low]);
	244	if((index.b.high & 0xf0) != 0xf0)
	245	probe_hwif_init(&ide_hwifs[index.b.high]);
	246	return 0;
	247	}
	248
	249	static struct pci_device_id cs5520_pci_tbl[] = {
	250	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	251	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	252	{ 0, },
	253	};
	254	MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
	255
	256	static struct pci_driver driver = {
	257	.name = "Cyrix_IDE",
	258	.id_table = cs5520_pci_tbl,
	259	.probe = cs5520_init_one,
	260	};
	261
82ab1eec	262	static int __init cs5520_ide_init(void)
1da177e4 LT	263	{
	264	return ide_pci_register_driver(&driver);
	265	}
	266
	267	module_init(cs5520_ide_init);
	268
	269	MODULE_AUTHOR("Alan Cox");
	270	MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
	271	MODULE_LICENSE("GPL");