[deliverable/linux.git] / drivers / ide / pci / cy82c693.c

/*
 *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
 *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
 *
 * CYPRESS CY82C693 chipset IDE controller
 *
 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
 * Writing the driver was quite simple, since most of the job is
 * done by the generic pci-ide support. 
 * The hard part was finding the CY82C693's datasheet on Cypress's
 * web page :-(. But Altavista solved this problem :-).
 *
 *
 * Notes:
 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
 *   a large and fast disk - the results look great, so I'd say the
 *   driver is working fine :-)
 *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA 
 * - this is my first linux driver, so there's probably a lot  of room 
 *   for optimizations and bug fixing, so feel free to do it.
 * - use idebus=xx parameter to set PCI bus speed - needed to calc
 *   timings for PIO modes (default will be 40)
 * - if using PIO mode it's a good idea to set the PIO mode and 
 *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
 * - I had some problems with my IBM DHEA with PIO modes < 2
 *   (lost interrupts) ?????
 * - first tests with DMA look okay, they seem to work, but there is a
 *   problem with sound - the BusMaster IDE TimeOut should fixed this
 *
 * Ancient History:
 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
 * ASK@1999-01-23: v0.33 made a few minor code clean ups
 *                       removed DMA clock speed setting by default
 *                       added boot message
 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
 *                       added support to set DMA Controller Clock Speed
 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
 *                       on some drives.
 * ASK@1998-10-29: v0.3 added support to set DMA modes
 * ASK@1998-10-28: v0.2 added support to set PIO modes
 * ASK@1998-10-27: v0.1 first version - chipset detection
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

/* the current version */
#define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"

/*
 *	The following are used to debug the driver.
 */
#define CY82C693_DEBUG_LOGS	0
#define CY82C693_DEBUG_INFO	0

/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
#undef CY82C693_SETDMA_CLOCK

/*
 *	NOTE: the value for busmaster timeout is tricky and I got it by
 *	trial and error!  By using a to low value will cause DMA timeouts
 *	and drop IDE performance, and by using a to high value will cause
 *	audio playback to scatter.
 *	If you know a better value or how to calc it, please let me know.
 */

/* twice the value written in cy82c693ub datasheet */
#define BUSMASTER_TIMEOUT	0x50
/*
 * the value above was tested on my machine and it seems to work okay
 */

/* here are the offset definitions for the registers */
#define CY82_IDE_CMDREG		0x04
#define CY82_IDE_ADDRSETUP	0x48
#define CY82_IDE_MASTER_IOR	0x4C
#define CY82_IDE_MASTER_IOW	0x4D
#define CY82_IDE_SLAVE_IOR	0x4E
#define CY82_IDE_SLAVE_IOW	0x4F
#define CY82_IDE_MASTER_8BIT	0x50
#define CY82_IDE_SLAVE_8BIT	0x51

#define CY82_INDEX_PORT		0x22
#define CY82_DATA_PORT		0x23

#define CY82_INDEX_CTRLREG1	0x01
#define CY82_INDEX_CHANNEL0	0x30
#define CY82_INDEX_CHANNEL1	0x31
#define CY82_INDEX_TIMEOUT	0x32

/* the min and max PCI bus speed in MHz - from datasheet */
#define CY82C963_MIN_BUS_SPEED	25
#define CY82C963_MAX_BUS_SPEED	33

/* the struct for the PIO mode timings */
typedef struct pio_clocks_s {
	u8	address_time;	/* Address setup (clocks) */
	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
} pio_clocks_t;

/*
 * calc clocks using bus_speed
 * returns (rounded up) time in bus clocks for time in ns
 */
static int calc_clk (int time, int bus_speed)
{
	int clocks;

	clocks = (time*bus_speed+999)/1000 -1;

	if (clocks < 0)
		clocks = 0;

	if (clocks > 0x0F)
		clocks = 0x0F;

	return clocks;
}

/*
 * compute the values for the clock registers for PIO
 * mode and pci_clk [MHz] speed
 *
 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 *
 */ 
static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
{
	int clk1, clk2;
	int bus_speed = system_bus_clock();	/* get speed of PCI bus */

	/* we don't check against CY82C693's min and max speed,
	 * so you can play with the idebus=xx parameter
	 */

	/* let's calc the address setup time clocks */
	p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);

	/* let's calc the active and recovery time clocks */
	clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);

	/* calc recovery timing */
	clk2 =	ide_pio_timings[pio].cycle_time -
		ide_pio_timings[pio].active_time -
		ide_pio_timings[pio].setup_time;

	clk2 = calc_clk(clk2, bus_speed);

	clk1 = (clk1<<4)|clk2;	/* combine active and recovery clocks */

	/* note: we use the same values for 16bit IOR and IOW
         *	those are all the same, since I don't have other
	 *	timings than those from ide-lib.c
	 */

	p_pclk->time_16r = (u8)clk1;
	p_pclk->time_16w = (u8)clk1;

	/* what are good values for 8bit ?? */
	p_pclk->time_8 = (u8)clk1;
}

/*
 * set DMA mode a specific channel for CY82C693
 */

static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;

	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the previous values */

	outb(index, CY82_INDEX_PORT);
	data = inb(CY82_DATA_PORT);

	printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		(data&0x3), ((data>>2)&1));
#endif /* CY82C693_DEBUG_LOGS */

	data = (mode & 3) | (single << 2);

	outb(index, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
		drive->name, HWIF(drive)->channel, drive->select.b.unit,
		mode & 3, single);
#endif /* CY82C693_DEBUG_INFO */

	/* 
	 * note: below we set the value for Bus Master IDE TimeOut Register
	 * I'm not absolutly sure what this does, but it solved my problem
	 * with IDE DMA and sound, so I now can play sound and work with
	 * my IDE driver at the same time :-)
	 *
	 * If you know the correct (best) value for this register please
	 * let me know - ASK
	 */

	data = BUSMASTER_TIMEOUT;
	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO	
	printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
		drive->name, data);
#endif /* CY82C693_DEBUG_INFO */
}

static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	pio_clocks_t pclk;
	unsigned int addrCtrl;

	/* select primary or secondary channel */
	if (hwif->index > 0) {  /* drive is on the secondary channel */
		dev = pci_get_slot(dev->bus, dev->devfn+1);
		if (!dev) {
			printk(KERN_ERR "%s: tune_drive: "
				"Cannot find secondary interface!\n",
				drive->name);
			return;
		}
	}

#if CY82C693_DEBUG_LOGS
	/* for debug let's show the register values */
	
       	if (drive->select.b.unit == 0) {
		/*
		 * get master drive registers               	
		 * address setup control register
		 * is 32 bit !!!
		 */ 
	  	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);                
		addrCtrl &= 0x0F;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	} else {
		/*
		 * set slave drive registers
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= 0xF0;
		addrCtrl >>= 4;

		/* now let's get the remaining registers */
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
		pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	}

	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_LOGS */

	/* let's calc the values for this PIO mode */
	compute_clocks(pio, &pclk);

	/* now let's write  the clocks registers */
	if (drive->select.b.unit == 0) {
		/*
		 * set master drive
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
		
		addrCtrl &= (~0xF);
		addrCtrl |= (unsigned int)pclk.address_time;
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
		
		addrCtrl &= 0xF;
	} else {
		/*
		 * set slave drive
		 * address setup control register
		 * is 32 bit !!!
		 */ 
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF0);
		addrCtrl |= ((unsigned int)pclk.address_time<<4);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);

		addrCtrl >>= 4;
		addrCtrl &= 0xF;
	}	

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->select.b.unit,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_INFO */
}

/*
 * this function is called during init and is used to setup the cy82c693 chip
 */
static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
{
	if (PCI_FUNC(dev->devfn) != 1)
		return 0;

#ifdef CY82C693_SETDMA_CLOCK
	u8 data = 0;
#endif /* CY82C693_SETDMA_CLOCK */ 

	/* write info about this verion of the driver */
	printk(KERN_INFO CY82_VERSION "\n");

#ifdef CY82C693_SETDMA_CLOCK
       /* okay let's set the DMA clock speed */
        
        outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
        data = inb(CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

        /*
	 * for some reason sometimes the DMA controller
	 * speed is set to ATCLK/2 ???? - we fix this here
	 * 
	 * note: i don't know what causes this strange behaviour,
	 *       but even changing the dma speed doesn't solve it :-(
	 *       the ide performance is still only half the normal speed 
	 * 
	 *       if anybody knows what goes wrong with my machine, please
	 *       let me know - ASK
         */

	data |= 0x03;

        outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
        outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
		name, data);
#endif /* CY82C693_DEBUG_INFO */

#endif /* CY82C693_SETDMA_CLOCK */
	return 0;
}

/*
 * the init function - called for each ide channel once
 */
static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &cy82c693_set_pio_mode;
	hwif->set_dma_mode = &cy82c693_set_dma_mode;
}

static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
{
	static ide_hwif_t *primary;
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_FUNC(dev->devfn) == 1)
		primary = hwif;
	else {
		hwif->mate = primary;
		hwif->channel = 1;
	}
}

static const struct ide_port_info cy82c693_chipset __devinitdata = {
	.name		= "CY82C693",
	.init_chipset	= init_chipset_cy82c693,
	.init_iops	= init_iops_cy82c693,
	.init_hwif	= init_hwif_cy82c693,
	.chipset	= ide_cy82c693,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_CY82C693 |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO4,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *dev2;
	int ret = -ENODEV;

	/* CY82C693 is more than only a IDE controller.
	   Function 1 is primary IDE channel, function 2 - secondary. */
        if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	    PCI_FUNC(dev->devfn) == 1) {
		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
		ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
		/* We leak pci refs here but thats ok - we can't be unloaded */
	}
	return ret;
}

static const struct pci_device_id cy82c693_pci_tbl[] = {
	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);

static struct pci_driver driver = {
	.name		= "Cypress_IDE",
	.id_table	= cy82c693_pci_tbl,
	.probe		= cy82c693_init_one,
};

static int __init cy82c693_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cy82c693_ide_init);

MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
	3	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
	4	*
	5	* CYPRESS CY82C693 chipset IDE controller
	6	*
	7	* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
	8	* Writing the driver was quite simple, since most of the job is
	9	* done by the generic pci-ide support.
	10	* The hard part was finding the CY82C693's datasheet on Cypress's
	11	* web page :-(. But Altavista solved this problem :-).
	12	*
	13	*
	14	* Notes:
	15	* - I recently got a 16.8G IBM DTTA, so I was able to test it with
	16	* a large and fast disk - the results look great, so I'd say the
	17	* driver is working fine :-)
	18	* hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
	19	* - this is my first linux driver, so there's probably a lot of room
	20	* for optimizations and bug fixing, so feel free to do it.
	21	* - use idebus=xx parameter to set PCI bus speed - needed to calc
	22	* timings for PIO modes (default will be 40)
	23	* - if using PIO mode it's a good idea to set the PIO mode and
	24	* 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
	25	* - I had some problems with my IBM DHEA with PIO modes < 2
	26	* (lost interrupts) ?????
	27	* - first tests with DMA look okay, they seem to work, but there is a
	28	* problem with sound - the BusMaster IDE TimeOut should fixed this
	29	*
	30	* Ancient History:
	31	* AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
	32	* ASK@1999-01-23: v0.33 made a few minor code clean ups
	33	* removed DMA clock speed setting by default
	34	* added boot message
	35	* ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
	36	* added support to set DMA Controller Clock Speed
	37	* ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
	38	* on some drives.
	39	* ASK@1998-10-29: v0.3 added support to set DMA modes
	40	* ASK@1998-10-28: v0.2 added support to set PIO modes
	41	* ASK@1998-10-27: v0.1 first version - chipset detection
	42	*
	43	*/
	44
1da177e4 LT	45	#include <linux/module.h>
	46	#include <linux/types.h>
	47	#include <linux/pci.h>
	48	#include <linux/delay.h>
	49	#include <linux/ide.h>
	50	#include <linux/init.h>
	51
	52	#include <asm/io.h>
	53
	54	/* the current version */
	55	#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
	56
	57	/*
	58	* The following are used to debug the driver.
	59	*/
	60	#define CY82C693_DEBUG_LOGS 0
	61	#define CY82C693_DEBUG_INFO 0
	62
	63	/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
	64	#undef CY82C693_SETDMA_CLOCK
	65
	66	/*
	67	* NOTE: the value for busmaster timeout is tricky and I got it by
	68	* trial and error! By using a to low value will cause DMA timeouts
	69	* and drop IDE performance, and by using a to high value will cause
	70	* audio playback to scatter.
	71	* If you know a better value or how to calc it, please let me know.
	72	*/
	73
	74	/* twice the value written in cy82c693ub datasheet */
	75	#define BUSMASTER_TIMEOUT 0x50
	76	/*
	77	* the value above was tested on my machine and it seems to work okay
	78	*/
	79
	80	/* here are the offset definitions for the registers */
	81	#define CY82_IDE_CMDREG 0x04
	82	#define CY82_IDE_ADDRSETUP 0x48
	83	#define CY82_IDE_MASTER_IOR 0x4C
	84	#define CY82_IDE_MASTER_IOW 0x4D
	85	#define CY82_IDE_SLAVE_IOR 0x4E
	86	#define CY82_IDE_SLAVE_IOW 0x4F
	87	#define CY82_IDE_MASTER_8BIT 0x50
	88	#define CY82_IDE_SLAVE_8BIT 0x51
	89
	90	#define CY82_INDEX_PORT 0x22
	91	#define CY82_DATA_PORT 0x23
	92
	93	#define CY82_INDEX_CTRLREG1 0x01
	94	#define CY82_INDEX_CHANNEL0 0x30
	95	#define CY82_INDEX_CHANNEL1 0x31
	96	#define CY82_INDEX_TIMEOUT 0x32
	97
1da177e4 LT	98	/* the min and max PCI bus speed in MHz - from datasheet */
	99	#define CY82C963_MIN_BUS_SPEED 25
	100	#define CY82C963_MAX_BUS_SPEED 33
	101
	102	/* the struct for the PIO mode timings */
	103	typedef struct pio_clocks_s {
	104	u8 address_time; /* Address setup (clocks) */
	105	u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	106	u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	107	u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
	108	} pio_clocks_t;
	109
	110	/*
	111	* calc clocks using bus_speed
	112	* returns (rounded up) time in bus clocks for time in ns
	113	*/
	114	static int calc_clk (int time, int bus_speed)
	115	{
	116	int clocks;
	117
	118	clocks = (time*bus_speed+999)/1000 -1;
	119
	120	if (clocks < 0)
	121	clocks = 0;
	122
	123	if (clocks > 0x0F)
	124	clocks = 0x0F;
	125
	126	return clocks;
	127	}
	128
	129	/*
	130	* compute the values for the clock registers for PIO
	131	* mode and pci_clk [MHz] speed
	132	*
	133	* NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
	134	* for mode 3 and 4 drives 8 and 16-bit timings are the same
	135	*
	136	*/
	137	static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
	138	{
	139	int clk1, clk2;
	140	int bus_speed = system_bus_clock(); /* get speed of PCI bus */
	141
	142	/* we don't check against CY82C693's min and max speed,
	143	* so you can play with the idebus=xx parameter
	144	*/
	145
1da177e4 LT	146	/* let's calc the address setup time clocks */
	147	p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
	148
	149	/* let's calc the active and recovery time clocks */
	150	clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
	151
	152	/* calc recovery timing */
	153	clk2 = ide_pio_timings[pio].cycle_time -
	154	ide_pio_timings[pio].active_time -
	155	ide_pio_timings[pio].setup_time;
	156
	157	clk2 = calc_clk(clk2, bus_speed);
	158
	159	clk1 = (clk1<<4)\|clk2; /* combine active and recovery clocks */
	160
	161	/* note: we use the same values for 16bit IOR and IOW
	162	* those are all the same, since I don't have other
	163	* timings than those from ide-lib.c
	164	*/
	165
	166	p_pclk->time_16r = (u8)clk1;
	167	p_pclk->time_16w = (u8)clk1;
	168
	169	/* what are good values for 8bit ?? */
	170	p_pclk->time_8 = (u8)clk1;
	171	}
	172
	173	/*
	174	* set DMA mode a specific channel for CY82C693
	175	*/
	176
8704de8f	177	static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4	178	{
8704de8f BZ	179	ide_hwif_t *hwif = drive->hwif;
8704de8f BZ	180	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
1da177e4	181
8704de8f	182	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
1da177e4 LT	183
	184	#if CY82C693_DEBUG_LOGS
	185	/* for debug let's show the previous values */
	186
0ecdca26 BZ	187	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	188	data = inb(CY82_DATA_PORT);
1da177e4 LT	189
	190	printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
	191	drive->name, HWIF(drive)->channel, drive->select.b.unit,
	192	(data&0x3), ((data>>2)&1));
	193	#endif /* CY82C693_DEBUG_LOGS */
	194
8704de8f	195	data = (mode & 3) \| (single << 2);
1da177e4	196
0ecdca26 BZ	197	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	198	outb(data, CY82_DATA_PORT);
1da177e4 LT	199
	200	#if CY82C693_DEBUG_INFO
	201	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
	202	drive->name, HWIF(drive)->channel, drive->select.b.unit,
8704de8f	203	mode & 3, single);
1da177e4 LT	204	#endif /* CY82C693_DEBUG_INFO */
	205
	206	/*
	207	* note: below we set the value for Bus Master IDE TimeOut Register
	208	* I'm not absolutly sure what this does, but it solved my problem
	209	* with IDE DMA and sound, so I now can play sound and work with
	210	* my IDE driver at the same time :-)
	211	*
	212	* If you know the correct (best) value for this register please
	213	* let me know - ASK
	214	*/
	215
	216	data = BUSMASTER_TIMEOUT;
0ecdca26 BZ	217	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
0ecdca26 BZ	218	outb(data, CY82_DATA_PORT);
1da177e4 LT	219
	220	#if CY82C693_DEBUG_INFO
	221	printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
	222	drive->name, data);
	223	#endif /* CY82C693_DEBUG_INFO */
	224	}
	225
26bcb879	226	static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	227	{
1da177e4 LT	228	ide_hwif_t *hwif = HWIF(drive);
36501650	229	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	230	pio_clocks_t pclk;
	231	unsigned int addrCtrl;
	232
	233	/* select primary or secondary channel */
	234	if (hwif->index > 0) { /* drive is on the secondary channel */
652aa162	235	dev = pci_get_slot(dev->bus, dev->devfn+1);
1da177e4 LT	236	if (!dev) {
	237	printk(KERN_ERR "%s: tune_drive: "
	238	"Cannot find secondary interface!\n",
	239	drive->name);
	240	return;
	241	}
	242	}
	243
	244	#if CY82C693_DEBUG_LOGS
	245	/* for debug let's show the register values */
	246
	247	if (drive->select.b.unit == 0) {
	248	/*
	249	* get master drive registers
	250	* address setup control register
	251	* is 32 bit !!!
	252	*/
	253	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	254	addrCtrl &= 0x0F;
	255
	256	/* now let's get the remaining registers */
	257	pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
	258	pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
	259	pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
	260	} else {
	261	/*
	262	* set slave drive registers
	263	* address setup control register
	264	* is 32 bit !!!
	265	*/
	266	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	267
	268	addrCtrl &= 0xF0;
	269	addrCtrl >>= 4;
	270
	271	/* now let's get the remaining registers */
	272	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
	273	pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
	274	pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
	275	}
	276
	277	printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
	278	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	279	drive->name, hwif->channel, drive->select.b.unit,
	280	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	281	#endif /* CY82C693_DEBUG_LOGS */
	282
1da177e4 LT	283	/* let's calc the values for this PIO mode */
	284	compute_clocks(pio, &pclk);
	285
	286	/* now let's write the clocks registers */
	287	if (drive->select.b.unit == 0) {
	288	/*
	289	* set master drive
	290	* address setup control register
	291	* is 32 bit !!!
	292	*/
	293	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	294
	295	addrCtrl &= (~0xF);
	296	addrCtrl \|= (unsigned int)pclk.address_time;
	297	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	298
	299	/* now let's set the remaining registers */
	300	pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
	301	pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
	302	pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
	303
	304	addrCtrl &= 0xF;
	305	} else {
	306	/*
	307	* set slave drive
	308	* address setup control register
	309	* is 32 bit !!!
	310	*/
	311	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	312
	313	addrCtrl &= (~0xF0);
	314	addrCtrl \|= ((unsigned int)pclk.address_time<<4);
	315	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	316
	317	/* now let's set the remaining registers */
	318	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
	319	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
	320	pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
	321
	322	addrCtrl >>= 4;
	323	addrCtrl &= 0xF;
	324	}
	325
	326	#if CY82C693_DEBUG_INFO
	327	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
	328	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
	329	drive->name, hwif->channel, drive->select.b.unit,
	330	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	331	#endif /* CY82C693_DEBUG_INFO */
	332	}
	333
	334	/*
	335	* this function is called during init and is used to setup the cy82c693 chip
	336	*/
ddbc9fb4	337	static unsigned int __devinit init_chipset_cy82c693(struct pci_dev dev, const char name)
1da177e4 LT	338	{
	339	if (PCI_FUNC(dev->devfn) != 1)
	340	return 0;
	341
	342	#ifdef CY82C693_SETDMA_CLOCK
	343	u8 data = 0;
	344	#endif /* CY82C693_SETDMA_CLOCK */
	345
	346	/* write info about this verion of the driver */
	347	printk(KERN_INFO CY82_VERSION "\n");
	348
	349	#ifdef CY82C693_SETDMA_CLOCK
	350	/* okay let's set the DMA clock speed */
	351
	352	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	353	data = inb(CY82_DATA_PORT);
	354
	355	#if CY82C693_DEBUG_INFO
	356	printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
	357	name, data);
	358	#endif /* CY82C693_DEBUG_INFO */
	359
	360	/*
	361	* for some reason sometimes the DMA controller
	362	* speed is set to ATCLK/2 ???? - we fix this here
	363	*
	364	* note: i don't know what causes this strange behaviour,
	365	* but even changing the dma speed doesn't solve it :-(
	366	* the ide performance is still only half the normal speed
	367	*
	368	* if anybody knows what goes wrong with my machine, please
	369	* let me know - ASK
	370	*/
	371
	372	data \|= 0x03;
	373
	374	outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
	375	outb(data, CY82_DATA_PORT);
	376
	377	#if CY82C693_DEBUG_INFO
	378	printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
	379	name, data);
	380	#endif /* CY82C693_DEBUG_INFO */
	381
	382	#endif /* CY82C693_SETDMA_CLOCK */
	383	return 0;
	384	}
	385
	386	/*
	387	* the init function - called for each ide channel once
	388	*/
ddbc9fb4	389	static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
1da177e4	390	{
26bcb879	391	hwif->set_pio_mode = &cy82c693_set_pio_mode;
8704de8f	392	hwif->set_dma_mode = &cy82c693_set_dma_mode;
1da177e4 LT	393	}
1da177e4 LT	394
e851b620	395	static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
1da177e4	396	{
f32d26ae	397	static ide_hwif_t *primary;
36501650	398	struct pci_dev *dev = to_pci_dev(hwif->dev);
f32d26ae	399
36501650	400	if (PCI_FUNC(dev->devfn) == 1)
1da177e4 LT	401	primary = hwif;
	402	else {
	403	hwif->mate = primary;
	404	hwif->channel = 1;
	405	}
	406	}
	407
85620436	408	static const struct ide_port_info cy82c693_chipset __devinitdata = {
7b77d864 BZ	409	.name = "CY82C693",
	410	.init_chipset = init_chipset_cy82c693,
	411	.init_iops = init_iops_cy82c693,
	412	.init_hwif = init_hwif_cy82c693,
528a572d	413	.chipset = ide_cy82c693,
8704de8f	414	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_CY82C693 \|
7cab14a7	415	IDE_HFLAG_BOOTABLE,
4099d143	416	.pio_mask = ATA_PIO4,
8704de8f BZ	417	.swdma_mask = ATA_SWDMA2,
8704de8f BZ	418	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	419	};
	420
	421	static int __devinit cy82c693_init_one(struct pci_dev dev, const struct pci_device_id id)
	422	{
1da177e4 LT	423	struct pci_dev *dev2;
	424	int ret = -ENODEV;
	425
	426	/* CY82C693 is more than only a IDE controller.
	427	Function 1 is primary IDE channel, function 2 - secondary. */
	428	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	429	PCI_FUNC(dev->devfn) == 1) {
652aa162	430	dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
7b77d864	431	ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
652aa162	432	/* We leak pci refs here but thats ok - we can't be unloaded */
1da177e4 LT	433	}
	434	return ret;
	435	}
	436
9cbcc5e3 BZ	437	static const struct pci_device_id cy82c693_pci_tbl[] = {
9cbcc5e3 BZ	438	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
1da177e4 LT	439	{ 0, },
	440	};
	441	MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
	442
	443	static struct pci_driver driver = {
	444	.name = "Cypress_IDE",
	445	.id_table = cy82c693_pci_tbl,
	446	.probe = cy82c693_init_one,
	447	};
	448
82ab1eec	449	static int __init cy82c693_ide_init(void)
1da177e4 LT	450	{
	451	return ide_pci_register_driver(&driver);
	452	}
	453
	454	module_init(cy82c693_ide_init);
	455
	456	MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
	457	MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
	458	MODULE_LICENSE("GPL");