[deliverable/linux.git] / drivers / ide / pci / hpt34x.c

/*
 * Copyright (C) 1998-2000	Andre Hedrick <andre@linux-ide.org>
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 *
 * 00:12.0 Unknown mass storage controller:
 * Triones Technologies, Inc.
 * Unknown device 0003 (rev 01)
 *
 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
 * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
 * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
 * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
 * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
 *
 * ide-pci.c reference
 *
 * Since there are two cards that report almost identically,
 * the only discernable difference is the values reported in pcicmd.
 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
 * Non-bootable card or HPT343 :: pcicmd == 0x05
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define HPT343_DEBUG_DRIVE_INFO		0

static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
	u8			hi_speed, lo_speed;

	hi_speed = speed >> 4;
	lo_speed = speed & 0x0f;

	if (hi_speed & 7) {
		hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
	} else {
		lo_speed <<= 5;
		lo_speed >>= 5;
	}

	pci_read_config_dword(dev, 0x44, &reg1);
	pci_read_config_dword(dev, 0x48, &reg2);
	tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
	tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
	pci_write_config_dword(dev, 0x44, tmp1);
	pci_write_config_dword(dev, 0x48, tmp2);

#if HPT343_DEBUG_DRIVE_INFO
	printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
		" (0x%02x 0x%02x)\n",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, reg1, tmp1, reg2, tmp2,
		hi_speed, lo_speed);
#endif /* HPT343_DEBUG_DRIVE_INFO */
}

static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	hpt34x_set_mode(drive, XFER_PIO_0 + pio);
}

/*
 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
 */
#define	HPT34X_PCI_INIT_REG		0x80

static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
{
	int i = 0;
	unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
	unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
	unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
	u16 cmd;
	unsigned long flags;

	local_irq_save(flags);

	pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
	pci_read_config_word(dev, PCI_COMMAND, &cmd);

	if (cmd & PCI_COMMAND_MEMORY)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	else
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);

	/*
	 * Since 20-23 can be assigned and are R/W, we correct them.
	 */
	pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
	for(i=0; i<4; i++) {
		dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
		dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
		dev->resource[i].flags = IORESOURCE_IO;
		pci_write_config_dword(dev,
				(PCI_BASE_ADDRESS_0 + (i * 4)),
				dev->resource[i].start);
	}
	pci_write_config_word(dev, PCI_COMMAND, cmd);

	local_irq_restore(flags);

	return dev->irq;
}

static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &hpt34x_set_pio_mode;
	hwif->set_dma_mode = &hpt34x_set_mode;
}

#define IDE_HFLAGS_HPT34X \
	(IDE_HFLAG_NO_ATAPI_DMA | \
	 IDE_HFLAG_NO_DSC | \
	 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
	 IDE_HFLAG_NO_AUTODMA)

static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
	{ /* 0 */
		.name		= "HPT343",
		.init_chipset	= init_chipset_hpt34x,
		.init_hwif	= init_hwif_hpt34x,
		.extra		= 16,
		.host_flags	= IDE_HFLAGS_HPT34X,
		.pio_mask	= ATA_PIO5,
	},
	{ /* 1 */
		.name		= "HPT345",
		.init_chipset	= init_chipset_hpt34x,
		.init_hwif	= init_hwif_hpt34x,
		.extra		= 16,
		.host_flags	= IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO5,
#ifdef CONFIG_HPT34X_AUTODMA
		.swdma_mask	= ATA_SWDMA2,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
#endif
	}
};

static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u16 pcicmd = 0;

	pci_read_config_word(dev, PCI_COMMAND, &pcicmd);

	d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];

	return ide_setup_pci_device(dev, d);
}

static const struct pci_device_id hpt34x_pci_tbl[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);

static struct pci_driver driver = {
	.name		= "HPT34x_IDE",
	.id_table	= hpt34x_pci_tbl,
	.probe		= hpt34x_init_one,
};

static int __init hpt34x_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(hpt34x_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
58f189fc	3	*
1da177e4 LT	4	* May be copied or modified under the terms of the GNU General Public License
	5	*
	6	*
	7	* 00:12.0 Unknown mass storage controller:
	8	* Triones Technologies, Inc.
	9	* Unknown device 0003 (rev 01)
	10	*
	11	* hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
	12	* hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
	13	* hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
	14	* hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
	15	* hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
	16	* hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
	17	*
	18	* ide-pci.c reference
	19	*
	20	* Since there are two cards that report almost identically,
	21	* the only discernable difference is the values reported in pcicmd.
	22	* Booting-BIOS card or HPT363 :: pcicmd == 0x07
	23	* Non-bootable card or HPT343 :: pcicmd == 0x05
	24	*/
	25
1da177e4 LT	26	#include <linux/module.h>
	27	#include <linux/types.h>
	28	#include <linux/kernel.h>
	29	#include <linux/delay.h>
	30	#include <linux/timer.h>
	31	#include <linux/mm.h>
	32	#include <linux/ioport.h>
	33	#include <linux/blkdev.h>
	34	#include <linux/hdreg.h>
	35	#include <linux/interrupt.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/ide.h>
	39
	40	#include <asm/io.h>
	41	#include <asm/irq.h>
	42
	43	#define HPT343_DEBUG_DRIVE_INFO 0
	44
88b2b32b	45	static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4	46	{
36501650	47	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4 LT	48	u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
	49	u8 hi_speed, lo_speed;
	50
	51	hi_speed = speed >> 4;
	52	lo_speed = speed & 0x0f;
	53
	54	if (hi_speed & 7) {
	55	hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
	56	} else {
	57	lo_speed <<= 5;
	58	lo_speed >>= 5;
	59	}
	60
	61	pci_read_config_dword(dev, 0x44, &reg1);
	62	pci_read_config_dword(dev, 0x48, &reg2);
	63	tmp1 = ((lo_speed << (3drive->dn)) \| (reg1 & ~(7 << (3drive->dn))));
296d9bcc	64	tmp2 = ((hi_speed << drive->dn) \| (reg2 & ~(0x11 << drive->dn)));
1da177e4 LT	65	pci_write_config_dword(dev, 0x44, tmp1);
	66	pci_write_config_dword(dev, 0x48, tmp2);
	67
	68	#if HPT343_DEBUG_DRIVE_INFO
	69	printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
	70	" (0x%02x 0x%02x)\n",
	71	drive->name, ide_xfer_verbose(speed),
	72	drive->dn, reg1, tmp1, reg2, tmp2,
	73	hi_speed, lo_speed);
	74	#endif /* HPT343_DEBUG_DRIVE_INFO */
1da177e4 LT	75	}
1da177e4 LT	76
26bcb879	77	static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	78	{
88b2b32b	79	hpt34x_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	80	}
1da177e4 LT	81
1da177e4 LT	82	/*
	83	* If the BIOS does not set the IO base addaress to XX00, 343 will fail.
	84	*/
	85	#define HPT34X_PCI_INIT_REG 0x80
	86
	87	static unsigned int __devinit init_chipset_hpt34x(struct pci_dev dev, const char name)
	88	{
	89	int i = 0;
	90	unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
	91	unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
	92	unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
	93	u16 cmd;
	94	unsigned long flags;
	95
	96	local_irq_save(flags);
	97
	98	pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
	99	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	100
9702b5d5	101	if (cmd & PCI_COMMAND_MEMORY)
1da177e4	102	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
9702b5d5	103	else
1da177e4	104	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
1da177e4 LT	105
	106	/*
	107	* Since 20-23 can be assigned and are R/W, we correct them.
	108	*/
	109	pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
	110	for(i=0; i<4; i++) {
	111	dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
	112	dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
	113	dev->resource[i].flags = IORESOURCE_IO;
	114	pci_write_config_dword(dev,
	115	(PCI_BASE_ADDRESS_0 + (i * 4)),
	116	dev->resource[i].start);
	117	}
	118	pci_write_config_word(dev, PCI_COMMAND, cmd);
	119
	120	local_irq_restore(flags);
	121
	122	return dev->irq;
	123	}
	124
	125	static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
	126	{
26bcb879	127	hwif->set_pio_mode = &hpt34x_set_pio_mode;
88b2b32b	128	hwif->set_dma_mode = &hpt34x_set_mode;
5f8b6c34	129	}
1da177e4	130
4db90a14 BZ	131	#define IDE_HFLAGS_HPT34X \
4db90a14 BZ	132	(IDE_HFLAG_NO_ATAPI_DMA \| \
4166c199	133	IDE_HFLAG_NO_DSC \| \
4db90a14 BZ	134	IDE_HFLAG_ABUSE_SET_DMA_MODE \| \
	135	IDE_HFLAG_NO_AUTODMA)
	136
85620436	137	static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
5f8b6c34 BZ	138	{ /* 0 */
	139	.name = "HPT343",
	140	.init_chipset = init_chipset_hpt34x,
	141	.init_hwif = init_hwif_hpt34x,
	142	.extra = 16,
4db90a14	143	.host_flags = IDE_HFLAGS_HPT34X,
5f8b6c34 BZ	144	.pio_mask = ATA_PIO5,
	145	},
	146	{ /* 1 */
	147	.name = "HPT345",
	148	.init_chipset = init_chipset_hpt34x,
	149	.init_hwif = init_hwif_hpt34x,
	150	.extra = 16,
4db90a14	151	.host_flags = IDE_HFLAGS_HPT34X \| IDE_HFLAG_OFF_BOARD,
5f8b6c34	152	.pio_mask = ATA_PIO5,
76e1faa7	153	#ifdef CONFIG_HPT34X_AUTODMA
5f8b6c34 BZ	154	.swdma_mask = ATA_SWDMA2,
	155	.mwdma_mask = ATA_MWDMA2,
	156	.udma_mask = ATA_UDMA2,
76e1faa7	157	#endif
5f8b6c34	158	}
1da177e4 LT	159	};
	160
	161	static int __devinit hpt34x_init_one(struct pci_dev dev, const struct pci_device_id id)
	162	{
85620436	163	const struct ide_port_info *d;
1da177e4 LT	164	u16 pcicmd = 0;
	165
	166	pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
	167
5f8b6c34	168	d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
1da177e4 LT	169
	170	return ide_setup_pci_device(dev, d);
	171	}
	172
9cbcc5e3 BZ	173	static const struct pci_device_id hpt34x_pci_tbl[] = {
9cbcc5e3 BZ	174	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), 0 },
1da177e4 LT	175	{ 0, },
	176	};
	177	MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
	178
	179	static struct pci_driver driver = {
	180	.name = "HPT34x_IDE",
	181	.id_table = hpt34x_pci_tbl,
	182	.probe = hpt34x_init_one,
	183	};
	184
82ab1eec	185	static int __init hpt34x_ide_init(void)
1da177e4 LT	186	{
	187	return ide_pci_register_driver(&driver);
	188	}
	189
	190	module_init(hpt34x_ide_init);
	191
	192	MODULE_AUTHOR("Andre Hedrick");
	193	MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
	194	MODULE_LICENSE("GPL");