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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002 | |
3 | * | |
4 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | * | |
7 | * | |
8 | * 00:12.0 Unknown mass storage controller: | |
9 | * Triones Technologies, Inc. | |
10 | * Unknown device 0003 (rev 01) | |
11 | * | |
12 | * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010) | |
13 | * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030) | |
14 | * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010) | |
15 | * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030) | |
16 | * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070) | |
17 | * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0) | |
18 | * | |
19 | * ide-pci.c reference | |
20 | * | |
21 | * Since there are two cards that report almost identically, | |
22 | * the only discernable difference is the values reported in pcicmd. | |
23 | * Booting-BIOS card or HPT363 :: pcicmd == 0x07 | |
24 | * Non-bootable card or HPT343 :: pcicmd == 0x05 | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/hdreg.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/ide.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | ||
44 | #define HPT343_DEBUG_DRIVE_INFO 0 | |
45 | ||
46 | static u8 hpt34x_ratemask (ide_drive_t *drive) | |
47 | { | |
48 | return 1; | |
49 | } | |
50 | ||
51 | static void hpt34x_clear_chipset (ide_drive_t *drive) | |
52 | { | |
53 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
54 | u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0; | |
55 | ||
56 | pci_read_config_dword(dev, 0x44, ®1); | |
57 | pci_read_config_dword(dev, 0x48, ®2); | |
58 | tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn)))); | |
59 | tmp2 = (reg2 & ~(0x11 << drive->dn)); | |
60 | pci_write_config_dword(dev, 0x44, tmp1); | |
61 | pci_write_config_dword(dev, 0x48, tmp2); | |
62 | } | |
63 | ||
64 | static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
65 | { | |
66 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
67 | u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed); | |
68 | u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0; | |
69 | u8 hi_speed, lo_speed; | |
70 | ||
71 | hi_speed = speed >> 4; | |
72 | lo_speed = speed & 0x0f; | |
73 | ||
74 | if (hi_speed & 7) { | |
75 | hi_speed = (hi_speed & 4) ? 0x01 : 0x10; | |
76 | } else { | |
77 | lo_speed <<= 5; | |
78 | lo_speed >>= 5; | |
79 | } | |
80 | ||
81 | pci_read_config_dword(dev, 0x44, ®1); | |
82 | pci_read_config_dword(dev, 0x48, ®2); | |
83 | tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn)))); | |
84 | tmp2 = ((hi_speed << drive->dn) | reg2); | |
85 | pci_write_config_dword(dev, 0x44, tmp1); | |
86 | pci_write_config_dword(dev, 0x48, tmp2); | |
87 | ||
88 | #if HPT343_DEBUG_DRIVE_INFO | |
89 | printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \ | |
90 | " (0x%02x 0x%02x)\n", | |
91 | drive->name, ide_xfer_verbose(speed), | |
92 | drive->dn, reg1, tmp1, reg2, tmp2, | |
93 | hi_speed, lo_speed); | |
94 | #endif /* HPT343_DEBUG_DRIVE_INFO */ | |
95 | ||
96 | return(ide_config_drive_speed(drive, speed)); | |
97 | } | |
98 | ||
99 | static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio) | |
100 | { | |
101 | pio = ide_get_best_pio_mode(drive, pio, 5, NULL); | |
102 | hpt34x_clear_chipset(drive); | |
103 | (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio)); | |
104 | } | |
105 | ||
106 | /* | |
107 | * This allows the configuration of ide_pci chipset registers | |
108 | * for cards that learn about the drive's UDMA, DMA, PIO capabilities | |
109 | * after the drive is reported by the OS. Initially for designed for | |
110 | * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc. | |
111 | */ | |
112 | ||
113 | static int config_chipset_for_dma (ide_drive_t *drive) | |
114 | { | |
115 | u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive)); | |
116 | ||
117 | if (!(speed)) | |
118 | return 0; | |
119 | ||
120 | hpt34x_clear_chipset(drive); | |
121 | (void) hpt34x_tune_chipset(drive, speed); | |
122 | return ide_dma_enable(drive); | |
123 | } | |
124 | ||
125 | static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive) | |
126 | { | |
127 | ide_hwif_t *hwif = HWIF(drive); | |
128 | struct hd_driveid *id = drive->id; | |
129 | ||
130 | drive->init_speed = 0; | |
131 | ||
132 | if (id && (id->capability & 1) && drive->autodma) { | |
133 | ||
134 | if (ide_use_dma(drive)) { | |
135 | if (config_chipset_for_dma(drive)) | |
136 | #ifndef CONFIG_HPT34X_AUTODMA | |
137 | return hwif->ide_dma_off_quietly(drive); | |
138 | #else | |
139 | return hwif->ide_dma_on(drive); | |
140 | #endif | |
141 | } | |
142 | ||
143 | goto fast_ata_pio; | |
144 | ||
145 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
146 | fast_ata_pio: | |
147 | hpt34x_tune_drive(drive, 255); | |
148 | return hwif->ide_dma_off_quietly(drive); | |
149 | } | |
150 | /* IORDY not supported */ | |
151 | return 0; | |
152 | } | |
153 | ||
154 | /* | |
155 | * If the BIOS does not set the IO base addaress to XX00, 343 will fail. | |
156 | */ | |
157 | #define HPT34X_PCI_INIT_REG 0x80 | |
158 | ||
159 | static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name) | |
160 | { | |
161 | int i = 0; | |
162 | unsigned long hpt34xIoBase = pci_resource_start(dev, 4); | |
163 | unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c }; | |
164 | unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 }; | |
165 | u16 cmd; | |
166 | unsigned long flags; | |
167 | ||
168 | local_irq_save(flags); | |
169 | ||
170 | pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00); | |
171 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
172 | ||
173 | if (cmd & PCI_COMMAND_MEMORY) { | |
174 | if (pci_resource_start(dev, PCI_ROM_RESOURCE)) { | |
299cc3c1 | 175 | pci_write_config_dword(dev, PCI_ROM_ADDRESS, |
1da177e4 LT |
176 | dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); |
177 | printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n", | |
08f46de9 | 178 | (unsigned long)dev->resource[PCI_ROM_RESOURCE].start); |
1da177e4 LT |
179 | } |
180 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0); | |
181 | } else { | |
182 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); | |
183 | } | |
184 | ||
185 | /* | |
186 | * Since 20-23 can be assigned and are R/W, we correct them. | |
187 | */ | |
188 | pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO); | |
189 | for(i=0; i<4; i++) { | |
190 | dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]); | |
191 | dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i]; | |
192 | dev->resource[i].flags = IORESOURCE_IO; | |
193 | pci_write_config_dword(dev, | |
194 | (PCI_BASE_ADDRESS_0 + (i * 4)), | |
195 | dev->resource[i].start); | |
196 | } | |
197 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
198 | ||
199 | local_irq_restore(flags); | |
200 | ||
201 | return dev->irq; | |
202 | } | |
203 | ||
204 | static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif) | |
205 | { | |
206 | u16 pcicmd = 0; | |
207 | ||
208 | hwif->autodma = 0; | |
209 | ||
210 | hwif->tuneproc = &hpt34x_tune_drive; | |
211 | hwif->speedproc = &hpt34x_tune_chipset; | |
212 | hwif->no_dsc = 1; | |
213 | hwif->drives[0].autotune = 1; | |
214 | hwif->drives[1].autotune = 1; | |
215 | ||
216 | pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd); | |
217 | ||
218 | if (!hwif->dma_base) | |
219 | return; | |
220 | ||
221 | hwif->ultra_mask = 0x07; | |
222 | hwif->mwdma_mask = 0x07; | |
223 | hwif->swdma_mask = 0x07; | |
224 | ||
225 | hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate; | |
226 | if (!noautodma) | |
227 | hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0; | |
228 | hwif->drives[0].autodma = hwif->autodma; | |
229 | hwif->drives[1].autodma = hwif->autodma; | |
230 | } | |
231 | ||
232 | static ide_pci_device_t hpt34x_chipset __devinitdata = { | |
233 | .name = "HPT34X", | |
234 | .init_chipset = init_chipset_hpt34x, | |
235 | .init_hwif = init_hwif_hpt34x, | |
236 | .channels = 2, | |
237 | .autodma = NOAUTODMA, | |
238 | .bootable = NEVER_BOARD, | |
239 | .extra = 16 | |
240 | }; | |
241 | ||
242 | static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
243 | { | |
244 | ide_pci_device_t *d = &hpt34x_chipset; | |
245 | static char *chipset_names[] = {"HPT343", "HPT345"}; | |
246 | u16 pcicmd = 0; | |
247 | ||
248 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
249 | ||
250 | d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]; | |
251 | d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD; | |
252 | ||
253 | return ide_setup_pci_device(dev, d); | |
254 | } | |
255 | ||
256 | static struct pci_device_id hpt34x_pci_tbl[] = { | |
257 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
258 | { 0, }, | |
259 | }; | |
260 | MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl); | |
261 | ||
262 | static struct pci_driver driver = { | |
263 | .name = "HPT34x_IDE", | |
264 | .id_table = hpt34x_pci_tbl, | |
265 | .probe = hpt34x_init_one, | |
266 | }; | |
267 | ||
82ab1eec | 268 | static int __init hpt34x_ide_init(void) |
1da177e4 LT |
269 | { |
270 | return ide_pci_register_driver(&driver); | |
271 | } | |
272 | ||
273 | module_init(hpt34x_ide_init); | |
274 | ||
275 | MODULE_AUTHOR("Andre Hedrick"); | |
276 | MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE"); | |
277 | MODULE_LICENSE("GPL"); |