Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
31e8a465 | 2 | * linux/drivers/ide/pci/hpt366.c Version 1.15 Oct 1, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
6 | * Portions Copyright (C) 2003 Red Hat Inc | |
38b66f84 | 7 | * Portions Copyright (C) 2005-2007 MontaVista Software, Inc. |
1da177e4 LT |
8 | * |
9 | * Thanks to HighPoint Technologies for their assistance, and hardware. | |
10 | * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his | |
11 | * donation of an ABit BP6 mainboard, processor, and memory acellerated | |
12 | * development and support. | |
13 | * | |
b39b01ff | 14 | * |
836c0063 SS |
15 | * HighPoint has its own drivers (open source except for the RAID part) |
16 | * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. | |
17 | * This may be useful to anyone wanting to work on this driver, however do not | |
18 | * trust them too much since the code tends to become less and less meaningful | |
19 | * as the time passes... :-/ | |
b39b01ff | 20 | * |
1da177e4 LT |
21 | * Note that final HPT370 support was done by force extraction of GPL. |
22 | * | |
23 | * - add function for getting/setting power status of drive | |
24 | * - the HPT370's state machine can get confused. reset it before each dma | |
25 | * xfer to prevent that from happening. | |
26 | * - reset state engine whenever we get an error. | |
27 | * - check for busmaster state at end of dma. | |
28 | * - use new highpoint timings. | |
29 | * - detect bus speed using highpoint register. | |
30 | * - use pll if we don't have a clock table. added a 66MHz table that's | |
31 | * just 2x the 33MHz table. | |
32 | * - removed turnaround. NOTE: we never want to switch between pll and | |
33 | * pci clocks as the chip can glitch in those cases. the highpoint | |
34 | * approved workaround slows everything down too much to be useful. in | |
35 | * addition, we would have to serialize access to each chip. | |
36 | * Adrian Sun <a.sun@sun.com> | |
37 | * | |
38 | * add drive timings for 66MHz PCI bus, | |
39 | * fix ATA Cable signal detection, fix incorrect /proc info | |
40 | * add /proc display for per-drive PIO/DMA/UDMA mode and | |
41 | * per-channel ATA-33/66 Cable detect. | |
42 | * Duncan Laurie <void@sun.com> | |
43 | * | |
44 | * fixup /proc output for multiple controllers | |
45 | * Tim Hockin <thockin@sun.com> | |
46 | * | |
47 | * On hpt366: | |
48 | * Reset the hpt366 on error, reset on dma | |
49 | * Fix disabling Fast Interrupt hpt366. | |
50 | * Mike Waychison <crlf@sun.com> | |
51 | * | |
52 | * Added support for 372N clocking and clock switching. The 372N needs | |
53 | * different clocks on read/write. This requires overloading rw_disk and | |
54 | * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for | |
55 | * keeping me sane. | |
56 | * Alan Cox <alan@redhat.com> | |
57 | * | |
836c0063 SS |
58 | * - fix the clock turnaround code: it was writing to the wrong ports when |
59 | * called for the secondary channel, caching the current clock mode per- | |
60 | * channel caused the cached register value to get out of sync with the | |
61 | * actual one, the channels weren't serialized, the turnaround shouldn't | |
62 | * be done on 66 MHz PCI bus | |
7b73ee05 SS |
63 | * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used |
64 | * does not allow for this speed anyway | |
65 | * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, | |
66 | * their primary channel is kind of virtual, it isn't tied to any pins) | |
471a0bda SS |
67 | * - fix/remove bad/unused timing tables and use one set of tables for the whole |
68 | * HPT37x chip family; save space by introducing the separate transfer mode | |
69 | * table in which the mode lookup is done | |
26c068da | 70 | * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives |
72931368 SS |
71 | * the wrong PCI frequency since DPLL has already been calibrated by BIOS; |
72 | * read it only from the function 0 of HPT374 chips | |
33b18a60 SS |
73 | * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, |
74 | * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead | |
73d1dd93 SS |
75 | * - pass to init_chipset() handlers a copy of the IDE PCI device structure as |
76 | * they tamper with its fields | |
7b73ee05 SS |
77 | * - pass to the init_setup handlers a copy of the ide_pci_device_t structure |
78 | * since they may tamper with its fields | |
90778574 SS |
79 | * - prefix the driver startup messages with the real chip name |
80 | * - claim the extra 240 bytes of I/O space for all chips | |
2648e5d9 | 81 | * - optimize the UltraDMA filtering and the drive list lookup code |
b4586715 | 82 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
7b73ee05 SS |
83 | * - cache offset of the channel's misc. control registers (MCRs) being used |
84 | * throughout the driver | |
85 | * - only touch the relevant MCR when detecting the cable type on HPT374's | |
86 | * function 1 | |
abc4ad4c | 87 | * - rename all the register related variables consistently |
7b73ee05 SS |
88 | * - move all the interrupt twiddling code from the speedproc handlers into |
89 | * init_hwif_hpt366(), also grouping all the DMA related code together there | |
90 | * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and | |
91 | * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings | |
92 | * when setting an UltraDMA mode | |
93 | * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select | |
94 | * the best possible one | |
4bf63de2 | 95 | * - clean up DMA timeout handling for HPT370 |
7b73ee05 SS |
96 | * - switch to using the enumeration type to differ between the numerous chip |
97 | * variants, matching PCI device/revision ID with the chip type early, at the | |
98 | * init_setup stage | |
99 | * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, | |
100 | * stop duplicating it for each channel by storing the pointer in the pci_dev | |
101 | * structure: first, at the init_setup stage, point it to a static "template" | |
102 | * with only the chip type and its specific base DPLL frequency, the highest | |
2648e5d9 SS |
103 | * UltraDMA mode, and the chip settings table pointer filled, then, at the |
104 | * init_chipset stage, allocate per-chip instance and fill it with the rest | |
105 | * of the necessary information | |
7b73ee05 SS |
106 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, |
107 | * switch to calculating PCI clock frequency based on the chip's base DPLL | |
108 | * frequency | |
109 | * - switch to using the DPLL clock and enable UltraATA/133 mode by default on | |
278978e9 SS |
110 | * anything newer than HPT370/A (except HPT374 that is not capable of this |
111 | * mode according to the manual) | |
6273d26a SS |
112 | * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), |
113 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; | |
7b73ee05 SS |
114 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining |
115 | * the register setting lists into the table indexed by the clock selected | |
2648e5d9 | 116 | * - set the correct hwif->ultra_mask for each individual chip |
b4e44369 | 117 | * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards |
7b73ee05 | 118 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> |
1da177e4 LT |
119 | */ |
120 | ||
1da177e4 LT |
121 | #include <linux/types.h> |
122 | #include <linux/module.h> | |
123 | #include <linux/kernel.h> | |
124 | #include <linux/delay.h> | |
125 | #include <linux/timer.h> | |
126 | #include <linux/mm.h> | |
127 | #include <linux/ioport.h> | |
128 | #include <linux/blkdev.h> | |
129 | #include <linux/hdreg.h> | |
130 | ||
131 | #include <linux/interrupt.h> | |
132 | #include <linux/pci.h> | |
133 | #include <linux/init.h> | |
134 | #include <linux/ide.h> | |
135 | ||
136 | #include <asm/uaccess.h> | |
137 | #include <asm/io.h> | |
138 | #include <asm/irq.h> | |
139 | ||
140 | /* various tuning parameters */ | |
141 | #define HPT_RESET_STATE_ENGINE | |
836c0063 SS |
142 | #undef HPT_DELAY_INTERRUPT |
143 | #define HPT_SERIALIZE_IO 0 | |
1da177e4 LT |
144 | |
145 | static const char *quirk_drives[] = { | |
146 | "QUANTUM FIREBALLlct08 08", | |
147 | "QUANTUM FIREBALLP KA6.4", | |
148 | "QUANTUM FIREBALLP LM20.4", | |
149 | "QUANTUM FIREBALLP LM20.5", | |
150 | NULL | |
151 | }; | |
152 | ||
153 | static const char *bad_ata100_5[] = { | |
154 | "IBM-DTLA-307075", | |
155 | "IBM-DTLA-307060", | |
156 | "IBM-DTLA-307045", | |
157 | "IBM-DTLA-307030", | |
158 | "IBM-DTLA-307020", | |
159 | "IBM-DTLA-307015", | |
160 | "IBM-DTLA-305040", | |
161 | "IBM-DTLA-305030", | |
162 | "IBM-DTLA-305020", | |
163 | "IC35L010AVER07-0", | |
164 | "IC35L020AVER07-0", | |
165 | "IC35L030AVER07-0", | |
166 | "IC35L040AVER07-0", | |
167 | "IC35L060AVER07-0", | |
168 | "WDC AC310200R", | |
169 | NULL | |
170 | }; | |
171 | ||
172 | static const char *bad_ata66_4[] = { | |
173 | "IBM-DTLA-307075", | |
174 | "IBM-DTLA-307060", | |
175 | "IBM-DTLA-307045", | |
176 | "IBM-DTLA-307030", | |
177 | "IBM-DTLA-307020", | |
178 | "IBM-DTLA-307015", | |
179 | "IBM-DTLA-305040", | |
180 | "IBM-DTLA-305030", | |
181 | "IBM-DTLA-305020", | |
182 | "IC35L010AVER07-0", | |
183 | "IC35L020AVER07-0", | |
184 | "IC35L030AVER07-0", | |
185 | "IC35L040AVER07-0", | |
186 | "IC35L060AVER07-0", | |
187 | "WDC AC310200R", | |
783353b1 | 188 | "MAXTOR STM3320620A", |
1da177e4 LT |
189 | NULL |
190 | }; | |
191 | ||
192 | static const char *bad_ata66_3[] = { | |
193 | "WDC AC310200R", | |
194 | NULL | |
195 | }; | |
196 | ||
197 | static const char *bad_ata33[] = { | |
198 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
199 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
200 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
201 | "Maxtor 90510D4", | |
202 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
203 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
204 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
205 | NULL | |
206 | }; | |
207 | ||
471a0bda SS |
208 | static u8 xfer_speeds[] = { |
209 | XFER_UDMA_6, | |
210 | XFER_UDMA_5, | |
211 | XFER_UDMA_4, | |
212 | XFER_UDMA_3, | |
213 | XFER_UDMA_2, | |
214 | XFER_UDMA_1, | |
215 | XFER_UDMA_0, | |
216 | ||
217 | XFER_MW_DMA_2, | |
218 | XFER_MW_DMA_1, | |
219 | XFER_MW_DMA_0, | |
220 | ||
221 | XFER_PIO_4, | |
222 | XFER_PIO_3, | |
223 | XFER_PIO_2, | |
224 | XFER_PIO_1, | |
225 | XFER_PIO_0 | |
1da177e4 LT |
226 | }; |
227 | ||
471a0bda SS |
228 | /* Key for bus clock timings |
229 | * 36x 37x | |
230 | * bits bits | |
231 | * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. | |
232 | * cycles = value + 1 | |
233 | * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
234 | * cycles = value + 1 | |
235 | * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
236 | * register access. | |
237 | * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file | |
238 | * register access. | |
239 | * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. | |
240 | * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. | |
241 | * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and | |
242 | * MW DMA xfer. | |
243 | * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for | |
244 | * task file register access. | |
245 | * 28 28 UDMA enable. | |
246 | * 29 29 DMA enable. | |
247 | * 30 30 PIO MST enable. If set, the chip is in bus master mode during | |
248 | * PIO xfer. | |
249 | * 31 31 FIFO enable. | |
1da177e4 | 250 | */ |
1da177e4 | 251 | |
471a0bda SS |
252 | static u32 forty_base_hpt36x[] = { |
253 | /* XFER_UDMA_6 */ 0x900fd943, | |
254 | /* XFER_UDMA_5 */ 0x900fd943, | |
255 | /* XFER_UDMA_4 */ 0x900fd943, | |
256 | /* XFER_UDMA_3 */ 0x900ad943, | |
257 | /* XFER_UDMA_2 */ 0x900bd943, | |
258 | /* XFER_UDMA_1 */ 0x9008d943, | |
259 | /* XFER_UDMA_0 */ 0x9008d943, | |
260 | ||
261 | /* XFER_MW_DMA_2 */ 0xa008d943, | |
262 | /* XFER_MW_DMA_1 */ 0xa010d955, | |
263 | /* XFER_MW_DMA_0 */ 0xa010d9fc, | |
264 | ||
265 | /* XFER_PIO_4 */ 0xc008d963, | |
266 | /* XFER_PIO_3 */ 0xc010d974, | |
267 | /* XFER_PIO_2 */ 0xc010d997, | |
268 | /* XFER_PIO_1 */ 0xc010d9c7, | |
269 | /* XFER_PIO_0 */ 0xc018d9d9 | |
1da177e4 LT |
270 | }; |
271 | ||
471a0bda SS |
272 | static u32 thirty_three_base_hpt36x[] = { |
273 | /* XFER_UDMA_6 */ 0x90c9a731, | |
274 | /* XFER_UDMA_5 */ 0x90c9a731, | |
275 | /* XFER_UDMA_4 */ 0x90c9a731, | |
276 | /* XFER_UDMA_3 */ 0x90cfa731, | |
277 | /* XFER_UDMA_2 */ 0x90caa731, | |
278 | /* XFER_UDMA_1 */ 0x90cba731, | |
279 | /* XFER_UDMA_0 */ 0x90c8a731, | |
280 | ||
281 | /* XFER_MW_DMA_2 */ 0xa0c8a731, | |
282 | /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ | |
283 | /* XFER_MW_DMA_0 */ 0xa0c8a797, | |
284 | ||
285 | /* XFER_PIO_4 */ 0xc0c8a731, | |
286 | /* XFER_PIO_3 */ 0xc0c8a742, | |
287 | /* XFER_PIO_2 */ 0xc0d0a753, | |
288 | /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ | |
289 | /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ | |
1da177e4 LT |
290 | }; |
291 | ||
471a0bda SS |
292 | static u32 twenty_five_base_hpt36x[] = { |
293 | /* XFER_UDMA_6 */ 0x90c98521, | |
294 | /* XFER_UDMA_5 */ 0x90c98521, | |
295 | /* XFER_UDMA_4 */ 0x90c98521, | |
296 | /* XFER_UDMA_3 */ 0x90cf8521, | |
297 | /* XFER_UDMA_2 */ 0x90cf8521, | |
298 | /* XFER_UDMA_1 */ 0x90cb8521, | |
299 | /* XFER_UDMA_0 */ 0x90cb8521, | |
300 | ||
301 | /* XFER_MW_DMA_2 */ 0xa0ca8521, | |
302 | /* XFER_MW_DMA_1 */ 0xa0ca8532, | |
303 | /* XFER_MW_DMA_0 */ 0xa0ca8575, | |
304 | ||
305 | /* XFER_PIO_4 */ 0xc0ca8521, | |
306 | /* XFER_PIO_3 */ 0xc0ca8532, | |
307 | /* XFER_PIO_2 */ 0xc0ca8542, | |
308 | /* XFER_PIO_1 */ 0xc0d08572, | |
309 | /* XFER_PIO_0 */ 0xc0d08585 | |
1da177e4 LT |
310 | }; |
311 | ||
471a0bda SS |
312 | static u32 thirty_three_base_hpt37x[] = { |
313 | /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ | |
314 | /* XFER_UDMA_5 */ 0x12446231, | |
315 | /* XFER_UDMA_4 */ 0x12446231, | |
316 | /* XFER_UDMA_3 */ 0x126c6231, | |
317 | /* XFER_UDMA_2 */ 0x12486231, | |
318 | /* XFER_UDMA_1 */ 0x124c6233, | |
319 | /* XFER_UDMA_0 */ 0x12506297, | |
320 | ||
321 | /* XFER_MW_DMA_2 */ 0x22406c31, | |
322 | /* XFER_MW_DMA_1 */ 0x22406c33, | |
323 | /* XFER_MW_DMA_0 */ 0x22406c97, | |
324 | ||
325 | /* XFER_PIO_4 */ 0x06414e31, | |
326 | /* XFER_PIO_3 */ 0x06414e42, | |
327 | /* XFER_PIO_2 */ 0x06414e53, | |
328 | /* XFER_PIO_1 */ 0x06814e93, | |
329 | /* XFER_PIO_0 */ 0x06814ea7 | |
1da177e4 LT |
330 | }; |
331 | ||
471a0bda SS |
332 | static u32 fifty_base_hpt37x[] = { |
333 | /* XFER_UDMA_6 */ 0x12848242, | |
334 | /* XFER_UDMA_5 */ 0x12848242, | |
335 | /* XFER_UDMA_4 */ 0x12ac8242, | |
336 | /* XFER_UDMA_3 */ 0x128c8242, | |
337 | /* XFER_UDMA_2 */ 0x120c8242, | |
338 | /* XFER_UDMA_1 */ 0x12148254, | |
339 | /* XFER_UDMA_0 */ 0x121882ea, | |
340 | ||
341 | /* XFER_MW_DMA_2 */ 0x22808242, | |
342 | /* XFER_MW_DMA_1 */ 0x22808254, | |
343 | /* XFER_MW_DMA_0 */ 0x228082ea, | |
344 | ||
345 | /* XFER_PIO_4 */ 0x0a81f442, | |
346 | /* XFER_PIO_3 */ 0x0a81f443, | |
347 | /* XFER_PIO_2 */ 0x0a81f454, | |
348 | /* XFER_PIO_1 */ 0x0ac1f465, | |
349 | /* XFER_PIO_0 */ 0x0ac1f48a | |
1da177e4 LT |
350 | }; |
351 | ||
471a0bda SS |
352 | static u32 sixty_six_base_hpt37x[] = { |
353 | /* XFER_UDMA_6 */ 0x1c869c62, | |
354 | /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ | |
355 | /* XFER_UDMA_4 */ 0x1c8a9c62, | |
356 | /* XFER_UDMA_3 */ 0x1c8e9c62, | |
357 | /* XFER_UDMA_2 */ 0x1c929c62, | |
358 | /* XFER_UDMA_1 */ 0x1c9a9c62, | |
359 | /* XFER_UDMA_0 */ 0x1c829c62, | |
360 | ||
361 | /* XFER_MW_DMA_2 */ 0x2c829c62, | |
362 | /* XFER_MW_DMA_1 */ 0x2c829c66, | |
363 | /* XFER_MW_DMA_0 */ 0x2c829d2e, | |
364 | ||
365 | /* XFER_PIO_4 */ 0x0c829c62, | |
366 | /* XFER_PIO_3 */ 0x0c829c84, | |
367 | /* XFER_PIO_2 */ 0x0c829ca6, | |
368 | /* XFER_PIO_1 */ 0x0d029d26, | |
369 | /* XFER_PIO_0 */ 0x0d029d5e | |
1da177e4 LT |
370 | }; |
371 | ||
1da177e4 | 372 | #define HPT366_DEBUG_DRIVE_INFO 0 |
7b73ee05 SS |
373 | #define HPT371_ALLOW_ATA133_6 1 |
374 | #define HPT302_ALLOW_ATA133_6 1 | |
375 | #define HPT372_ALLOW_ATA133_6 1 | |
e139b0b0 | 376 | #define HPT370_ALLOW_ATA100_5 0 |
1da177e4 LT |
377 | #define HPT366_ALLOW_ATA66_4 1 |
378 | #define HPT366_ALLOW_ATA66_3 1 | |
379 | #define HPT366_MAX_DEVS 8 | |
380 | ||
7b73ee05 SS |
381 | /* Supported ATA clock frequencies */ |
382 | enum ata_clock { | |
383 | ATA_CLOCK_25MHZ, | |
384 | ATA_CLOCK_33MHZ, | |
385 | ATA_CLOCK_40MHZ, | |
386 | ATA_CLOCK_50MHZ, | |
387 | ATA_CLOCK_66MHZ, | |
388 | NUM_ATA_CLOCKS | |
389 | }; | |
1da177e4 | 390 | |
b39b01ff | 391 | /* |
7b73ee05 | 392 | * Hold all the HighPoint chip information in one place. |
b39b01ff | 393 | */ |
1da177e4 | 394 | |
7b73ee05 SS |
395 | struct hpt_info { |
396 | u8 chip_type; /* Chip type */ | |
2648e5d9 | 397 | u8 max_ultra; /* Max. UltraDMA mode allowed */ |
7b73ee05 SS |
398 | u8 dpll_clk; /* DPLL clock in MHz */ |
399 | u8 pci_clk; /* PCI clock in MHz */ | |
400 | u32 **settings; /* Chipset settings table */ | |
b39b01ff AC |
401 | }; |
402 | ||
7b73ee05 SS |
403 | /* Supported HighPoint chips */ |
404 | enum { | |
405 | HPT36x, | |
406 | HPT370, | |
407 | HPT370A, | |
408 | HPT374, | |
409 | HPT372, | |
410 | HPT372A, | |
411 | HPT302, | |
412 | HPT371, | |
413 | HPT372N, | |
414 | HPT302N, | |
415 | HPT371N | |
416 | }; | |
b39b01ff | 417 | |
7b73ee05 SS |
418 | static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = { |
419 | twenty_five_base_hpt36x, | |
420 | thirty_three_base_hpt36x, | |
421 | forty_base_hpt36x, | |
422 | NULL, | |
423 | NULL | |
424 | }; | |
e139b0b0 | 425 | |
7b73ee05 SS |
426 | static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = { |
427 | NULL, | |
428 | thirty_three_base_hpt37x, | |
429 | NULL, | |
430 | fifty_base_hpt37x, | |
431 | sixty_six_base_hpt37x | |
432 | }; | |
1da177e4 | 433 | |
7b73ee05 SS |
434 | static struct hpt_info hpt36x __devinitdata = { |
435 | .chip_type = HPT36x, | |
2648e5d9 | 436 | .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2, |
7b73ee05 SS |
437 | .dpll_clk = 0, /* no DPLL */ |
438 | .settings = hpt36x_settings | |
439 | }; | |
440 | ||
441 | static struct hpt_info hpt370 __devinitdata = { | |
442 | .chip_type = HPT370, | |
2648e5d9 | 443 | .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, |
7b73ee05 SS |
444 | .dpll_clk = 48, |
445 | .settings = hpt37x_settings | |
446 | }; | |
447 | ||
448 | static struct hpt_info hpt370a __devinitdata = { | |
449 | .chip_type = HPT370A, | |
2648e5d9 | 450 | .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4, |
7b73ee05 SS |
451 | .dpll_clk = 48, |
452 | .settings = hpt37x_settings | |
453 | }; | |
454 | ||
455 | static struct hpt_info hpt374 __devinitdata = { | |
456 | .chip_type = HPT374, | |
2648e5d9 | 457 | .max_ultra = 5, |
7b73ee05 SS |
458 | .dpll_clk = 48, |
459 | .settings = hpt37x_settings | |
460 | }; | |
461 | ||
462 | static struct hpt_info hpt372 __devinitdata = { | |
463 | .chip_type = HPT372, | |
2648e5d9 | 464 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
465 | .dpll_clk = 55, |
466 | .settings = hpt37x_settings | |
467 | }; | |
468 | ||
469 | static struct hpt_info hpt372a __devinitdata = { | |
470 | .chip_type = HPT372A, | |
2648e5d9 | 471 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
472 | .dpll_clk = 66, |
473 | .settings = hpt37x_settings | |
474 | }; | |
475 | ||
476 | static struct hpt_info hpt302 __devinitdata = { | |
477 | .chip_type = HPT302, | |
2648e5d9 | 478 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
479 | .dpll_clk = 66, |
480 | .settings = hpt37x_settings | |
481 | }; | |
482 | ||
483 | static struct hpt_info hpt371 __devinitdata = { | |
484 | .chip_type = HPT371, | |
2648e5d9 | 485 | .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
486 | .dpll_clk = 66, |
487 | .settings = hpt37x_settings | |
488 | }; | |
489 | ||
490 | static struct hpt_info hpt372n __devinitdata = { | |
491 | .chip_type = HPT372N, | |
2648e5d9 | 492 | .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
493 | .dpll_clk = 77, |
494 | .settings = hpt37x_settings | |
495 | }; | |
496 | ||
497 | static struct hpt_info hpt302n __devinitdata = { | |
498 | .chip_type = HPT302N, | |
2648e5d9 | 499 | .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 | 500 | .dpll_clk = 77, |
38b66f84 | 501 | .settings = hpt37x_settings |
7b73ee05 SS |
502 | }; |
503 | ||
504 | static struct hpt_info hpt371n __devinitdata = { | |
505 | .chip_type = HPT371N, | |
2648e5d9 | 506 | .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5, |
7b73ee05 SS |
507 | .dpll_clk = 77, |
508 | .settings = hpt37x_settings | |
509 | }; | |
1da177e4 | 510 | |
e139b0b0 SS |
511 | static int check_in_drive_list(ide_drive_t *drive, const char **list) |
512 | { | |
513 | struct hd_driveid *id = drive->id; | |
514 | ||
515 | while (*list) | |
516 | if (!strcmp(*list++,id->model)) | |
517 | return 1; | |
518 | return 0; | |
519 | } | |
1da177e4 | 520 | |
1da177e4 | 521 | /* |
2808b0a9 SS |
522 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem |
523 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
1da177e4 | 524 | */ |
2d5eaa6d BZ |
525 | |
526 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) | |
1da177e4 | 527 | { |
2808b0a9 SS |
528 | ide_hwif_t *hwif = HWIF(drive); |
529 | struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); | |
530 | u8 mask = hwif->ultra_mask; | |
1da177e4 | 531 | |
2648e5d9 | 532 | switch (info->chip_type) { |
2648e5d9 SS |
533 | case HPT36x: |
534 | if (!HPT366_ALLOW_ATA66_4 || | |
535 | check_in_drive_list(drive, bad_ata66_4)) | |
2808b0a9 | 536 | mask = ATA_UDMA3; |
7b73ee05 | 537 | |
2648e5d9 SS |
538 | if (!HPT366_ALLOW_ATA66_3 || |
539 | check_in_drive_list(drive, bad_ata66_3)) | |
2808b0a9 | 540 | mask = ATA_UDMA2; |
2648e5d9 | 541 | break; |
2808b0a9 SS |
542 | case HPT370: |
543 | if (!HPT370_ALLOW_ATA100_5 || | |
544 | check_in_drive_list(drive, bad_ata100_5)) | |
545 | mask = ATA_UDMA4; | |
546 | break; | |
547 | case HPT370A: | |
548 | if (!HPT370_ALLOW_ATA100_5 || | |
549 | check_in_drive_list(drive, bad_ata100_5)) | |
550 | return ATA_UDMA4; | |
551 | case HPT372 : | |
552 | case HPT372A: | |
553 | case HPT372N: | |
554 | case HPT374 : | |
555 | if (ide_dev_is_sata(drive->id)) | |
556 | mask &= ~0x0e; | |
557 | /* Fall thru */ | |
2648e5d9 | 558 | default: |
2808b0a9 | 559 | return mask; |
1da177e4 | 560 | } |
2648e5d9 SS |
561 | |
562 | return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; | |
1da177e4 LT |
563 | } |
564 | ||
b4e44369 SS |
565 | static u8 hpt3xx_mdma_filter(ide_drive_t *drive) |
566 | { | |
567 | ide_hwif_t *hwif = HWIF(drive); | |
568 | struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); | |
569 | ||
570 | switch (info->chip_type) { | |
571 | case HPT372 : | |
572 | case HPT372A: | |
573 | case HPT372N: | |
574 | case HPT374 : | |
575 | if (ide_dev_is_sata(drive->id)) | |
576 | return 0x00; | |
577 | /* Fall thru */ | |
578 | default: | |
579 | return 0x07; | |
580 | } | |
581 | } | |
582 | ||
7b73ee05 | 583 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) |
1da177e4 | 584 | { |
471a0bda SS |
585 | int i; |
586 | ||
587 | /* | |
588 | * Lookup the transfer mode table to get the index into | |
589 | * the timing table. | |
590 | * | |
591 | * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. | |
592 | */ | |
593 | for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) | |
594 | if (xfer_speeds[i] == speed) | |
595 | break; | |
7b73ee05 SS |
596 | /* |
597 | * NOTE: info->settings only points to the pointer | |
598 | * to the list of the actual register values | |
599 | */ | |
600 | return (*info->settings)[i]; | |
1da177e4 LT |
601 | } |
602 | ||
88b2b32b | 603 | static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 604 | { |
abc4ad4c SS |
605 | ide_hwif_t *hwif = HWIF(drive); |
606 | struct pci_dev *dev = hwif->pci_dev; | |
7b73ee05 | 607 | struct hpt_info *info = pci_get_drvdata(dev); |
abc4ad4c | 608 | u8 itr_addr = drive->dn ? 0x44 : 0x40; |
26ccb802 | 609 | u32 old_itr = 0; |
2d5eaa6d BZ |
610 | u32 itr_mask, new_itr; |
611 | ||
2d5eaa6d BZ |
612 | itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 : |
613 | (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff); | |
614 | ||
615 | new_itr = get_speed_setting(speed, info); | |
b39b01ff | 616 | |
1da177e4 | 617 | /* |
abc4ad4c SS |
618 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
619 | * to avoid problems handling I/O errors later | |
1da177e4 | 620 | */ |
abc4ad4c SS |
621 | pci_read_config_dword(dev, itr_addr, &old_itr); |
622 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); | |
623 | new_itr &= ~0xc0000000; | |
1da177e4 | 624 | |
abc4ad4c | 625 | pci_write_config_dword(dev, itr_addr, new_itr); |
1da177e4 LT |
626 | } |
627 | ||
88b2b32b | 628 | static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 629 | { |
abc4ad4c SS |
630 | ide_hwif_t *hwif = HWIF(drive); |
631 | struct pci_dev *dev = hwif->pci_dev; | |
7b73ee05 | 632 | struct hpt_info *info = pci_get_drvdata(dev); |
abc4ad4c | 633 | u8 itr_addr = 0x40 + (drive->dn * 4); |
26ccb802 | 634 | u32 old_itr = 0; |
2d5eaa6d BZ |
635 | u32 itr_mask, new_itr; |
636 | ||
2d5eaa6d BZ |
637 | itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 : |
638 | (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff); | |
639 | ||
640 | new_itr = get_speed_setting(speed, info); | |
1da177e4 | 641 | |
abc4ad4c SS |
642 | pci_read_config_dword(dev, itr_addr, &old_itr); |
643 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); | |
1da177e4 | 644 | |
b39b01ff | 645 | if (speed < XFER_MW_DMA_0) |
abc4ad4c SS |
646 | new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ |
647 | pci_write_config_dword(dev, itr_addr, new_itr); | |
1da177e4 LT |
648 | } |
649 | ||
88b2b32b | 650 | static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 651 | { |
abc4ad4c | 652 | ide_hwif_t *hwif = HWIF(drive); |
7b73ee05 | 653 | struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); |
1da177e4 | 654 | |
7b73ee05 | 655 | if (info->chip_type >= HPT370) |
88b2b32b | 656 | hpt37x_set_mode(drive, speed); |
1da177e4 | 657 | else /* hpt368: hpt_minimum_revision(dev, 2) */ |
88b2b32b | 658 | hpt36x_set_mode(drive, speed); |
1da177e4 LT |
659 | } |
660 | ||
26bcb879 | 661 | static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 662 | { |
88b2b32b | 663 | hpt3xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
664 | } |
665 | ||
e139b0b0 | 666 | static int hpt3xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 667 | { |
e139b0b0 SS |
668 | struct hd_driveid *id = drive->id; |
669 | const char **list = quirk_drives; | |
670 | ||
671 | while (*list) | |
672 | if (strstr(id->model, *list++)) | |
673 | return 1; | |
674 | return 0; | |
1da177e4 LT |
675 | } |
676 | ||
26ccb802 | 677 | static void hpt3xx_intrproc(ide_drive_t *drive) |
1da177e4 | 678 | { |
1da177e4 LT |
679 | if (drive->quirk_list) |
680 | return; | |
31e8a465 | 681 | |
1da177e4 | 682 | /* drives in the quirk_list may not like intr setups/cleanups */ |
31e8a465 | 683 | outb(drive->ctl | 2, IDE_CONTROL_REG); |
1da177e4 LT |
684 | } |
685 | ||
26ccb802 | 686 | static void hpt3xx_maskproc(ide_drive_t *drive, int mask) |
1da177e4 | 687 | { |
abc4ad4c SS |
688 | ide_hwif_t *hwif = HWIF(drive); |
689 | struct pci_dev *dev = hwif->pci_dev; | |
7b73ee05 | 690 | struct hpt_info *info = pci_get_drvdata(dev); |
1da177e4 LT |
691 | |
692 | if (drive->quirk_list) { | |
7b73ee05 | 693 | if (info->chip_type >= HPT370) { |
abc4ad4c SS |
694 | u8 scr1 = 0; |
695 | ||
696 | pci_read_config_byte(dev, 0x5a, &scr1); | |
697 | if (((scr1 & 0x10) >> 4) != mask) { | |
698 | if (mask) | |
699 | scr1 |= 0x10; | |
700 | else | |
701 | scr1 &= ~0x10; | |
702 | pci_write_config_byte(dev, 0x5a, scr1); | |
703 | } | |
1da177e4 | 704 | } else { |
abc4ad4c | 705 | if (mask) |
b39b01ff | 706 | disable_irq(hwif->irq); |
abc4ad4c SS |
707 | else |
708 | enable_irq (hwif->irq); | |
1da177e4 | 709 | } |
abc4ad4c | 710 | } else |
31e8a465 BZ |
711 | outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
712 | IDE_CONTROL_REG); | |
1da177e4 LT |
713 | } |
714 | ||
1da177e4 | 715 | /* |
abc4ad4c | 716 | * This is specific to the HPT366 UDMA chipset |
1da177e4 LT |
717 | * by HighPoint|Triones Technologies, Inc. |
718 | */ | |
841d2a9b | 719 | static void hpt366_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 720 | { |
abc4ad4c SS |
721 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
722 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; | |
723 | ||
724 | pci_read_config_byte(dev, 0x50, &mcr1); | |
725 | pci_read_config_byte(dev, 0x52, &mcr3); | |
726 | pci_read_config_byte(dev, 0x5a, &scr1); | |
727 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", | |
728 | drive->name, __FUNCTION__, mcr1, mcr3, scr1); | |
729 | if (scr1 & 0x10) | |
730 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
841d2a9b | 731 | ide_dma_lost_irq(drive); |
1da177e4 LT |
732 | } |
733 | ||
4bf63de2 | 734 | static void hpt370_clear_engine(ide_drive_t *drive) |
1da177e4 | 735 | { |
abc4ad4c SS |
736 | ide_hwif_t *hwif = HWIF(drive); |
737 | ||
738 | pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37); | |
1da177e4 LT |
739 | udelay(10); |
740 | } | |
741 | ||
4bf63de2 SS |
742 | static void hpt370_irq_timeout(ide_drive_t *drive) |
743 | { | |
744 | ide_hwif_t *hwif = HWIF(drive); | |
745 | u16 bfifo = 0; | |
746 | u8 dma_cmd; | |
747 | ||
748 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); | |
749 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); | |
750 | ||
751 | /* get DMA command mode */ | |
31e8a465 | 752 | dma_cmd = inb(hwif->dma_command); |
4bf63de2 | 753 | /* stop DMA */ |
31e8a465 | 754 | outb(dma_cmd & ~0x1, hwif->dma_command); |
4bf63de2 SS |
755 | hpt370_clear_engine(drive); |
756 | } | |
757 | ||
1da177e4 LT |
758 | static void hpt370_ide_dma_start(ide_drive_t *drive) |
759 | { | |
760 | #ifdef HPT_RESET_STATE_ENGINE | |
761 | hpt370_clear_engine(drive); | |
762 | #endif | |
763 | ide_dma_start(drive); | |
764 | } | |
765 | ||
4bf63de2 | 766 | static int hpt370_ide_dma_end(ide_drive_t *drive) |
1da177e4 LT |
767 | { |
768 | ide_hwif_t *hwif = HWIF(drive); | |
31e8a465 | 769 | u8 dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
770 | |
771 | if (dma_stat & 0x01) { | |
772 | /* wait a little */ | |
773 | udelay(20); | |
31e8a465 | 774 | dma_stat = inb(hwif->dma_status); |
4bf63de2 SS |
775 | if (dma_stat & 0x01) |
776 | hpt370_irq_timeout(drive); | |
1da177e4 | 777 | } |
1da177e4 LT |
778 | return __ide_dma_end(drive); |
779 | } | |
780 | ||
c283f5db | 781 | static void hpt370_dma_timeout(ide_drive_t *drive) |
1da177e4 | 782 | { |
4bf63de2 | 783 | hpt370_irq_timeout(drive); |
c283f5db | 784 | ide_dma_timeout(drive); |
1da177e4 LT |
785 | } |
786 | ||
1da177e4 LT |
787 | /* returns 1 if DMA IRQ issued, 0 otherwise */ |
788 | static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |
789 | { | |
790 | ide_hwif_t *hwif = HWIF(drive); | |
791 | u16 bfifo = 0; | |
abc4ad4c | 792 | u8 dma_stat; |
1da177e4 | 793 | |
abc4ad4c | 794 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); |
1da177e4 LT |
795 | if (bfifo & 0x1FF) { |
796 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | |
797 | return 0; | |
798 | } | |
799 | ||
0ecdca26 | 800 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 801 | /* return 1 if INTR asserted */ |
abc4ad4c | 802 | if (dma_stat & 4) |
1da177e4 LT |
803 | return 1; |
804 | ||
805 | if (!drive->waiting_for_dma) | |
806 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
807 | drive->name, __FUNCTION__); | |
808 | return 0; | |
809 | } | |
810 | ||
abc4ad4c | 811 | static int hpt374_ide_dma_end(ide_drive_t *drive) |
1da177e4 | 812 | { |
1da177e4 | 813 | ide_hwif_t *hwif = HWIF(drive); |
abc4ad4c SS |
814 | struct pci_dev *dev = hwif->pci_dev; |
815 | u8 mcr = 0, mcr_addr = hwif->select_data; | |
816 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
817 | ||
818 | pci_read_config_byte(dev, 0x6a, &bwsr); | |
819 | pci_read_config_byte(dev, mcr_addr, &mcr); | |
820 | if (bwsr & mask) | |
821 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | |
1da177e4 LT |
822 | return __ide_dma_end(drive); |
823 | } | |
824 | ||
825 | /** | |
836c0063 SS |
826 | * hpt3xxn_set_clock - perform clock switching dance |
827 | * @hwif: hwif to switch | |
828 | * @mode: clocking mode (0x21 for write, 0x23 otherwise) | |
1da177e4 | 829 | * |
836c0063 | 830 | * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. |
1da177e4 | 831 | */ |
836c0063 SS |
832 | |
833 | static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) | |
1da177e4 | 834 | { |
31e8a465 | 835 | u8 scr2 = inb(hwif->dma_master + 0x7b); |
836c0063 SS |
836 | |
837 | if ((scr2 & 0x7f) == mode) | |
838 | return; | |
839 | ||
1da177e4 | 840 | /* Tristate the bus */ |
31e8a465 BZ |
841 | outb(0x80, hwif->dma_master + 0x73); |
842 | outb(0x80, hwif->dma_master + 0x77); | |
836c0063 | 843 | |
1da177e4 | 844 | /* Switch clock and reset channels */ |
31e8a465 BZ |
845 | outb(mode, hwif->dma_master + 0x7b); |
846 | outb(0xc0, hwif->dma_master + 0x79); | |
836c0063 | 847 | |
7b73ee05 SS |
848 | /* |
849 | * Reset the state machines. | |
850 | * NOTE: avoid accidentally enabling the disabled channels. | |
851 | */ | |
31e8a465 BZ |
852 | outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70); |
853 | outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74); | |
836c0063 | 854 | |
1da177e4 | 855 | /* Complete reset */ |
31e8a465 | 856 | outb(0x00, hwif->dma_master + 0x79); |
836c0063 | 857 | |
1da177e4 | 858 | /* Reconnect channels to bus */ |
31e8a465 BZ |
859 | outb(0x00, hwif->dma_master + 0x73); |
860 | outb(0x00, hwif->dma_master + 0x77); | |
1da177e4 LT |
861 | } |
862 | ||
863 | /** | |
836c0063 | 864 | * hpt3xxn_rw_disk - prepare for I/O |
1da177e4 LT |
865 | * @drive: drive for command |
866 | * @rq: block request structure | |
867 | * | |
836c0063 | 868 | * This is called when a disk I/O is issued to HPT3xxN. |
1da177e4 LT |
869 | * We need it because of the clock switching. |
870 | */ | |
871 | ||
836c0063 | 872 | static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) |
1da177e4 | 873 | { |
7b73ee05 | 874 | hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21); |
1da177e4 LT |
875 | } |
876 | ||
1da177e4 | 877 | /* |
33b18a60 | 878 | * Set/get power state for a drive. |
abc4ad4c | 879 | * NOTE: affects both drives on each channel. |
1da177e4 | 880 | * |
33b18a60 | 881 | * When we turn the power back on, we need to re-initialize things. |
1da177e4 LT |
882 | */ |
883 | #define TRISTATE_BIT 0x8000 | |
33b18a60 SS |
884 | |
885 | static int hpt3xx_busproc(ide_drive_t *drive, int state) | |
1da177e4 | 886 | { |
abc4ad4c | 887 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 | 888 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
889 | u8 mcr_addr = hwif->select_data + 2; |
890 | u8 resetmask = hwif->channel ? 0x80 : 0x40; | |
891 | u8 bsr2 = 0; | |
892 | u16 mcr = 0; | |
1da177e4 LT |
893 | |
894 | hwif->bus_state = state; | |
895 | ||
33b18a60 | 896 | /* Grab the status. */ |
abc4ad4c SS |
897 | pci_read_config_word(dev, mcr_addr, &mcr); |
898 | pci_read_config_byte(dev, 0x59, &bsr2); | |
1da177e4 | 899 | |
33b18a60 SS |
900 | /* |
901 | * Set the state. We don't set it if we don't need to do so. | |
902 | * Make sure that the drive knows that it has failed if it's off. | |
903 | */ | |
1da177e4 LT |
904 | switch (state) { |
905 | case BUSSTATE_ON: | |
abc4ad4c | 906 | if (!(bsr2 & resetmask)) |
1da177e4 | 907 | return 0; |
33b18a60 SS |
908 | hwif->drives[0].failures = hwif->drives[1].failures = 0; |
909 | ||
abc4ad4c SS |
910 | pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); |
911 | pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); | |
33b18a60 | 912 | return 0; |
1da177e4 | 913 | case BUSSTATE_OFF: |
abc4ad4c | 914 | if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) |
1da177e4 | 915 | return 0; |
abc4ad4c | 916 | mcr &= ~TRISTATE_BIT; |
1da177e4 LT |
917 | break; |
918 | case BUSSTATE_TRISTATE: | |
abc4ad4c | 919 | if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) |
1da177e4 | 920 | return 0; |
abc4ad4c | 921 | mcr |= TRISTATE_BIT; |
1da177e4 | 922 | break; |
33b18a60 SS |
923 | default: |
924 | return -EINVAL; | |
1da177e4 | 925 | } |
1da177e4 | 926 | |
33b18a60 SS |
927 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; |
928 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
929 | ||
abc4ad4c SS |
930 | pci_write_config_word(dev, mcr_addr, mcr); |
931 | pci_write_config_byte(dev, 0x59, bsr2 | resetmask); | |
1da177e4 LT |
932 | return 0; |
933 | } | |
934 | ||
7b73ee05 SS |
935 | /** |
936 | * hpt37x_calibrate_dpll - calibrate the DPLL | |
937 | * @dev: PCI device | |
938 | * | |
939 | * Perform a calibration cycle on the DPLL. | |
940 | * Returns 1 if this succeeds | |
941 | */ | |
942 | static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) | |
1da177e4 | 943 | { |
7b73ee05 SS |
944 | u32 dpll = (f_high << 16) | f_low | 0x100; |
945 | u8 scr2; | |
946 | int i; | |
b39b01ff | 947 | |
7b73ee05 | 948 | pci_write_config_dword(dev, 0x5c, dpll); |
b39b01ff | 949 | |
7b73ee05 SS |
950 | /* Wait for oscillator ready */ |
951 | for(i = 0; i < 0x5000; ++i) { | |
952 | udelay(50); | |
953 | pci_read_config_byte(dev, 0x5b, &scr2); | |
954 | if (scr2 & 0x80) | |
b39b01ff AC |
955 | break; |
956 | } | |
7b73ee05 SS |
957 | /* See if it stays ready (we'll just bail out if it's not yet) */ |
958 | for(i = 0; i < 0x1000; ++i) { | |
959 | pci_read_config_byte(dev, 0x5b, &scr2); | |
960 | /* DPLL destabilized? */ | |
961 | if(!(scr2 & 0x80)) | |
962 | return 0; | |
963 | } | |
964 | /* Turn off tuning, we have the DPLL set */ | |
965 | pci_read_config_dword (dev, 0x5c, &dpll); | |
966 | pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); | |
967 | return 1; | |
b39b01ff AC |
968 | } |
969 | ||
7b73ee05 | 970 | static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) |
b39b01ff | 971 | { |
7b73ee05 SS |
972 | struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL); |
973 | unsigned long io_base = pci_resource_start(dev, 4); | |
974 | u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ | |
72931368 | 975 | u8 chip_type; |
7b73ee05 SS |
976 | enum ata_clock clock; |
977 | ||
978 | if (info == NULL) { | |
979 | printk(KERN_ERR "%s: out of memory!\n", name); | |
980 | return -ENOMEM; | |
981 | } | |
982 | ||
1da177e4 | 983 | /* |
7b73ee05 SS |
984 | * Copy everything from a static "template" structure |
985 | * to just allocated per-chip hpt_info structure. | |
1da177e4 | 986 | */ |
72931368 SS |
987 | memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info)); |
988 | chip_type = info->chip_type; | |
1da177e4 | 989 | |
7b73ee05 SS |
990 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
991 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
992 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
993 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
26c068da | 994 | |
1da177e4 | 995 | /* |
7b73ee05 | 996 | * First, try to estimate the PCI clock frequency... |
1da177e4 | 997 | */ |
72931368 | 998 | if (chip_type >= HPT370) { |
7b73ee05 SS |
999 | u8 scr1 = 0; |
1000 | u16 f_cnt = 0; | |
1001 | u32 temp = 0; | |
1002 | ||
1003 | /* Interrupt force enable. */ | |
1004 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1005 | if (scr1 & 0x10) | |
1006 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1007 | ||
1008 | /* | |
1009 | * HighPoint does this for HPT372A. | |
1010 | * NOTE: This register is only writeable via I/O space. | |
1011 | */ | |
72931368 | 1012 | if (chip_type == HPT372A) |
7b73ee05 SS |
1013 | outb(0x0e, io_base + 0x9c); |
1014 | ||
1015 | /* | |
1016 | * Default to PCI clock. Make sure MA15/16 are set to output | |
1017 | * to prevent drives having problems with 40-pin cables. | |
1018 | */ | |
1019 | pci_write_config_byte(dev, 0x5b, 0x23); | |
836c0063 | 1020 | |
7b73ee05 SS |
1021 | /* |
1022 | * We'll have to read f_CNT value in order to determine | |
1023 | * the PCI clock frequency according to the following ratio: | |
1024 | * | |
1025 | * f_CNT = Fpci * 192 / Fdpll | |
1026 | * | |
1027 | * First try reading the register in which the HighPoint BIOS | |
1028 | * saves f_CNT value before reprogramming the DPLL from its | |
1029 | * default setting (which differs for the various chips). | |
7b73ee05 | 1030 | * |
72931368 SS |
1031 | * NOTE: This register is only accessible via I/O space; |
1032 | * HPT374 BIOS only saves it for the function 0, so we have to | |
1033 | * always read it from there -- no need to check the result of | |
1034 | * pci_get_slot() for the function 0 as the whole device has | |
1035 | * been already "pinned" (via function 1) in init_setup_hpt374() | |
1036 | */ | |
1037 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1038 | struct pci_dev *dev1 = pci_get_slot(dev->bus, | |
1039 | dev->devfn - 1); | |
1040 | unsigned long io_base = pci_resource_start(dev1, 4); | |
1041 | ||
1042 | temp = inl(io_base + 0x90); | |
1043 | pci_dev_put(dev1); | |
1044 | } else | |
1045 | temp = inl(io_base + 0x90); | |
1046 | ||
1047 | /* | |
1048 | * In case the signature check fails, we'll have to | |
1049 | * resort to reading the f_CNT register itself in hopes | |
1050 | * that nobody has touched the DPLL yet... | |
7b73ee05 | 1051 | */ |
7b73ee05 SS |
1052 | if ((temp & 0xFFFFF000) != 0xABCDE000) { |
1053 | int i; | |
1054 | ||
1055 | printk(KERN_WARNING "%s: no clock data saved by BIOS\n", | |
1056 | name); | |
1057 | ||
1058 | /* Calculate the average value of f_CNT. */ | |
1059 | for (temp = i = 0; i < 128; i++) { | |
1060 | pci_read_config_word(dev, 0x78, &f_cnt); | |
1061 | temp += f_cnt & 0x1ff; | |
1062 | mdelay(1); | |
1063 | } | |
1064 | f_cnt = temp / 128; | |
1065 | } else | |
1066 | f_cnt = temp & 0x1ff; | |
1067 | ||
1068 | dpll_clk = info->dpll_clk; | |
1069 | pci_clk = (f_cnt * dpll_clk) / 192; | |
1070 | ||
1071 | /* Clamp PCI clock to bands. */ | |
1072 | if (pci_clk < 40) | |
1073 | pci_clk = 33; | |
1074 | else if(pci_clk < 45) | |
1075 | pci_clk = 40; | |
1076 | else if(pci_clk < 55) | |
1077 | pci_clk = 50; | |
1da177e4 | 1078 | else |
7b73ee05 | 1079 | pci_clk = 66; |
836c0063 | 1080 | |
7b73ee05 SS |
1081 | printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, " |
1082 | "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk); | |
90778574 | 1083 | } else { |
7b73ee05 SS |
1084 | u32 itr1 = 0; |
1085 | ||
1086 | pci_read_config_dword(dev, 0x40, &itr1); | |
1087 | ||
1088 | /* Detect PCI clock by looking at cmd_high_time. */ | |
1089 | switch((itr1 >> 8) & 0x07) { | |
1090 | case 0x09: | |
1091 | pci_clk = 40; | |
6273d26a | 1092 | break; |
7b73ee05 SS |
1093 | case 0x05: |
1094 | pci_clk = 25; | |
6273d26a | 1095 | break; |
7b73ee05 SS |
1096 | case 0x07: |
1097 | default: | |
1098 | pci_clk = 33; | |
6273d26a | 1099 | break; |
1da177e4 LT |
1100 | } |
1101 | } | |
836c0063 | 1102 | |
7b73ee05 SS |
1103 | /* Let's assume we'll use PCI clock for the ATA clock... */ |
1104 | switch (pci_clk) { | |
1105 | case 25: | |
1106 | clock = ATA_CLOCK_25MHZ; | |
1107 | break; | |
1108 | case 33: | |
1109 | default: | |
1110 | clock = ATA_CLOCK_33MHZ; | |
1111 | break; | |
1112 | case 40: | |
1113 | clock = ATA_CLOCK_40MHZ; | |
1114 | break; | |
1115 | case 50: | |
1116 | clock = ATA_CLOCK_50MHZ; | |
1117 | break; | |
1118 | case 66: | |
1119 | clock = ATA_CLOCK_66MHZ; | |
1120 | break; | |
1121 | } | |
836c0063 | 1122 | |
1da177e4 | 1123 | /* |
7b73ee05 SS |
1124 | * Only try the DPLL if we don't have a table for the PCI clock that |
1125 | * we are running at for HPT370/A, always use it for anything newer... | |
b39b01ff | 1126 | * |
7b73ee05 SS |
1127 | * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. |
1128 | * We also don't like using the DPLL because this causes glitches | |
1129 | * on PRST-/SRST- when the state engine gets reset... | |
1da177e4 | 1130 | */ |
72931368 | 1131 | if (chip_type >= HPT374 || info->settings[clock] == NULL) { |
7b73ee05 SS |
1132 | u16 f_low, delta = pci_clk < 50 ? 2 : 4; |
1133 | int adjust; | |
1134 | ||
1135 | /* | |
1136 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is | |
1137 | * supported/enabled, use 50 MHz DPLL clock otherwise... | |
1138 | */ | |
2648e5d9 | 1139 | if (info->max_ultra == 6) { |
7b73ee05 SS |
1140 | dpll_clk = 66; |
1141 | clock = ATA_CLOCK_66MHZ; | |
1142 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ | |
1143 | dpll_clk = 50; | |
1144 | clock = ATA_CLOCK_50MHZ; | |
1145 | } | |
b39b01ff | 1146 | |
7b73ee05 SS |
1147 | if (info->settings[clock] == NULL) { |
1148 | printk(KERN_ERR "%s: unknown bus timing!\n", name); | |
1149 | kfree(info); | |
1150 | return -EIO; | |
1da177e4 | 1151 | } |
1da177e4 | 1152 | |
7b73ee05 SS |
1153 | /* Select the DPLL clock. */ |
1154 | pci_write_config_byte(dev, 0x5b, 0x21); | |
1155 | ||
1156 | /* | |
1157 | * Adjust the DPLL based upon PCI clock, enable it, | |
1158 | * and wait for stabilization... | |
1159 | */ | |
1160 | f_low = (pci_clk * 48) / dpll_clk; | |
1161 | ||
1162 | for (adjust = 0; adjust < 8; adjust++) { | |
1163 | if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) | |
1164 | break; | |
1165 | ||
1166 | /* | |
1167 | * See if it'll settle at a fractionally different clock | |
1168 | */ | |
1169 | if (adjust & 1) | |
1170 | f_low -= adjust >> 1; | |
1171 | else | |
1172 | f_low += adjust >> 1; | |
1173 | } | |
1174 | if (adjust == 8) { | |
1175 | printk(KERN_ERR "%s: DPLL did not stabilize!\n", name); | |
1176 | kfree(info); | |
1177 | return -EIO; | |
1178 | } | |
1179 | ||
1180 | printk("%s: using %d MHz DPLL clock\n", name, dpll_clk); | |
1181 | } else { | |
1182 | /* Mark the fact that we're not using the DPLL. */ | |
1183 | dpll_clk = 0; | |
1184 | ||
1185 | printk("%s: using %d MHz PCI clock\n", name, pci_clk); | |
1186 | } | |
b39b01ff | 1187 | |
9ec4ff42 | 1188 | /* |
7b73ee05 SS |
1189 | * Advance the table pointer to a slot which points to the list |
1190 | * of the register values settings matching the clock being used. | |
9ec4ff42 | 1191 | */ |
7b73ee05 | 1192 | info->settings += clock; |
1da177e4 | 1193 | |
7b73ee05 SS |
1194 | /* Store the clock frequencies. */ |
1195 | info->dpll_clk = dpll_clk; | |
1196 | info->pci_clk = pci_clk; | |
1da177e4 | 1197 | |
7b73ee05 SS |
1198 | /* Point to this chip's own instance of the hpt_info structure. */ |
1199 | pci_set_drvdata(dev, info); | |
b39b01ff | 1200 | |
72931368 | 1201 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1202 | u8 mcr1, mcr4; |
1203 | ||
1204 | /* | |
1205 | * Reset the state engines. | |
1206 | * NOTE: Avoid accidentally enabling the disabled channels. | |
1207 | */ | |
1208 | pci_read_config_byte (dev, 0x50, &mcr1); | |
1209 | pci_read_config_byte (dev, 0x54, &mcr4); | |
1210 | pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); | |
1211 | pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); | |
1212 | udelay(100); | |
26ccb802 | 1213 | } |
1da177e4 | 1214 | |
7b73ee05 SS |
1215 | /* |
1216 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
1217 | * the MISC. register to stretch the UltraDMA Tss timing. | |
1218 | * NOTE: This register is only writeable via I/O space. | |
1219 | */ | |
72931368 | 1220 | if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) |
7b73ee05 SS |
1221 | |
1222 | outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); | |
1223 | ||
1da177e4 LT |
1224 | return dev->irq; |
1225 | } | |
1226 | ||
1227 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |
1228 | { | |
2808b0a9 SS |
1229 | struct pci_dev *dev = hwif->pci_dev; |
1230 | struct hpt_info *info = pci_get_drvdata(dev); | |
1231 | int serialize = HPT_SERIALIZE_IO; | |
1232 | u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; | |
1233 | u8 chip_type = info->chip_type; | |
1234 | u8 new_mcr, old_mcr = 0; | |
abc4ad4c SS |
1235 | |
1236 | /* Cache the channel's MISC. control registers' offset */ | |
2808b0a9 | 1237 | hwif->select_data = hwif->channel ? 0x54 : 0x50; |
abc4ad4c | 1238 | |
26bcb879 | 1239 | hwif->set_pio_mode = &hpt3xx_set_pio_mode; |
88b2b32b | 1240 | hwif->set_dma_mode = &hpt3xx_set_mode; |
2808b0a9 SS |
1241 | hwif->quirkproc = &hpt3xx_quirkproc; |
1242 | hwif->intrproc = &hpt3xx_intrproc; | |
1243 | hwif->maskproc = &hpt3xx_maskproc; | |
1244 | hwif->busproc = &hpt3xx_busproc; | |
2648e5d9 | 1245 | |
2808b0a9 | 1246 | hwif->udma_filter = &hpt3xx_udma_filter; |
b4e44369 | 1247 | hwif->mdma_filter = &hpt3xx_mdma_filter; |
abc4ad4c | 1248 | |
836c0063 SS |
1249 | /* |
1250 | * HPT3xxN chips have some complications: | |
1251 | * | |
1252 | * - on 33 MHz PCI we must clock switch | |
1253 | * - on 66 MHz PCI we must NOT use the PCI clock | |
1254 | */ | |
7b73ee05 | 1255 | if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { |
836c0063 SS |
1256 | /* |
1257 | * Clock is shared between the channels, | |
1258 | * so we'll have to serialize them... :-( | |
1259 | */ | |
1260 | serialize = 1; | |
1261 | hwif->rw_disk = &hpt3xxn_rw_disk; | |
1262 | } | |
1da177e4 | 1263 | |
26ccb802 SS |
1264 | /* Serialize access to this device if needed */ |
1265 | if (serialize && hwif->mate) | |
1266 | hwif->serialized = hwif->mate->serialized = 1; | |
1267 | ||
1268 | /* | |
1269 | * Disable the "fast interrupt" prediction. Don't hold off | |
1270 | * on interrupts. (== 0x01 despite what the docs say) | |
1271 | */ | |
1272 | pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr); | |
1273 | ||
7b73ee05 | 1274 | if (info->chip_type >= HPT374) |
26ccb802 | 1275 | new_mcr = old_mcr & ~0x07; |
7b73ee05 | 1276 | else if (info->chip_type >= HPT370) { |
26ccb802 SS |
1277 | new_mcr = old_mcr; |
1278 | new_mcr &= ~0x02; | |
1279 | ||
1280 | #ifdef HPT_DELAY_INTERRUPT | |
1281 | new_mcr &= ~0x01; | |
1282 | #else | |
1283 | new_mcr |= 0x01; | |
1284 | #endif | |
1285 | } else /* HPT366 and HPT368 */ | |
1286 | new_mcr = old_mcr & ~0x80; | |
1287 | ||
1288 | if (new_mcr != old_mcr) | |
1289 | pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); | |
1290 | ||
a29ec3b2 BZ |
1291 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1292 | ||
1293 | if (hwif->dma_base == 0) | |
26ccb802 | 1294 | return; |
26ccb802 | 1295 | |
1da177e4 LT |
1296 | /* |
1297 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | |
abc4ad4c | 1298 | * address lines to access an external EEPROM. To read valid |
1da177e4 LT |
1299 | * cable detect state the pins must be enabled as inputs. |
1300 | */ | |
7b73ee05 | 1301 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { |
1da177e4 LT |
1302 | /* |
1303 | * HPT374 PCI function 1 | |
1304 | * - set bit 15 of reg 0x52 to enable TCBLID as input | |
1305 | * - set bit 15 of reg 0x56 to enable FCBLID as input | |
1306 | */ | |
abc4ad4c SS |
1307 | u8 mcr_addr = hwif->select_data + 2; |
1308 | u16 mcr; | |
1309 | ||
1310 | pci_read_config_word (dev, mcr_addr, &mcr); | |
1311 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); | |
1da177e4 | 1312 | /* now read cable id register */ |
abc4ad4c SS |
1313 | pci_read_config_byte (dev, 0x5a, &scr1); |
1314 | pci_write_config_word(dev, mcr_addr, mcr); | |
7b73ee05 | 1315 | } else if (chip_type >= HPT370) { |
1da177e4 LT |
1316 | /* |
1317 | * HPT370/372 and 374 pcifn 0 | |
abc4ad4c | 1318 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs |
1da177e4 | 1319 | */ |
abc4ad4c | 1320 | u8 scr2 = 0; |
1da177e4 | 1321 | |
abc4ad4c SS |
1322 | pci_read_config_byte (dev, 0x5b, &scr2); |
1323 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); | |
1324 | /* now read cable id register */ | |
1325 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1326 | pci_write_config_byte(dev, 0x5b, scr2); | |
1327 | } else | |
1328 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1da177e4 | 1329 | |
49521f97 BZ |
1330 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
1331 | hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 | 1332 | |
7b73ee05 | 1333 | if (chip_type >= HPT374) { |
26ccb802 SS |
1334 | hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; |
1335 | hwif->ide_dma_end = &hpt374_ide_dma_end; | |
7b73ee05 | 1336 | } else if (chip_type >= HPT370) { |
26ccb802 SS |
1337 | hwif->dma_start = &hpt370_ide_dma_start; |
1338 | hwif->ide_dma_end = &hpt370_ide_dma_end; | |
c283f5db | 1339 | hwif->dma_timeout = &hpt370_dma_timeout; |
26ccb802 | 1340 | } else |
841d2a9b | 1341 | hwif->dma_lost_irq = &hpt366_dma_lost_irq; |
1da177e4 LT |
1342 | } |
1343 | ||
1344 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | |
1345 | { | |
26ccb802 | 1346 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
1347 | u8 masterdma = 0, slavedma = 0; |
1348 | u8 dma_new = 0, dma_old = 0; | |
1da177e4 LT |
1349 | unsigned long flags; |
1350 | ||
31e8a465 | 1351 | dma_old = inb(dmabase + 2); |
1da177e4 LT |
1352 | |
1353 | local_irq_save(flags); | |
1354 | ||
1355 | dma_new = dma_old; | |
abc4ad4c SS |
1356 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1357 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); | |
1da177e4 LT |
1358 | |
1359 | if (masterdma & 0x30) dma_new |= 0x20; | |
abc4ad4c | 1360 | if ( slavedma & 0x30) dma_new |= 0x40; |
1da177e4 | 1361 | if (dma_new != dma_old) |
31e8a465 | 1362 | outb(dma_new, dmabase + 2); |
1da177e4 LT |
1363 | |
1364 | local_irq_restore(flags); | |
1365 | ||
1366 | ide_setup_dma(hwif, dmabase, 8); | |
1367 | } | |
1368 | ||
1369 | static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) | |
1370 | { | |
b4586715 | 1371 | struct pci_dev *dev2; |
1da177e4 LT |
1372 | |
1373 | if (PCI_FUNC(dev->devfn) & 1) | |
1374 | return -ENODEV; | |
1375 | ||
7b73ee05 SS |
1376 | pci_set_drvdata(dev, &hpt374); |
1377 | ||
b4586715 SS |
1378 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { |
1379 | int ret; | |
1380 | ||
7b73ee05 SS |
1381 | pci_set_drvdata(dev2, &hpt374); |
1382 | ||
b4586715 SS |
1383 | if (dev2->irq != dev->irq) { |
1384 | /* FIXME: we need a core pci_set_interrupt() */ | |
1385 | dev2->irq = dev->irq; | |
1386 | printk(KERN_WARNING "%s: PCI config space interrupt " | |
1387 | "fixed.\n", d->name); | |
1da177e4 | 1388 | } |
b4586715 SS |
1389 | ret = ide_setup_pci_devices(dev, dev2, d); |
1390 | if (ret < 0) | |
1391 | pci_dev_put(dev2); | |
1392 | return ret; | |
1da177e4 LT |
1393 | } |
1394 | return ide_setup_pci_device(dev, d); | |
1395 | } | |
1396 | ||
90778574 | 1397 | static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 | 1398 | { |
7b73ee05 SS |
1399 | pci_set_drvdata(dev, &hpt372n); |
1400 | ||
1da177e4 LT |
1401 | return ide_setup_pci_device(dev, d); |
1402 | } | |
1403 | ||
836c0063 SS |
1404 | static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d) |
1405 | { | |
7b73ee05 | 1406 | struct hpt_info *info; |
44c10138 | 1407 | u8 mcr1 = 0; |
90778574 | 1408 | |
44c10138 | 1409 | if (dev->revision > 1) { |
90778574 | 1410 | d->name = "HPT371N"; |
836c0063 | 1411 | |
7b73ee05 SS |
1412 | info = &hpt371n; |
1413 | } else | |
1414 | info = &hpt371; | |
1415 | ||
836c0063 SS |
1416 | /* |
1417 | * HPT371 chips physically have only one channel, the secondary one, | |
1418 | * but the primary channel registers do exist! Go figure... | |
1419 | * So, we manually disable the non-existing channel here | |
1420 | * (if the BIOS hasn't done this already). | |
1421 | */ | |
1422 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1423 | if (mcr1 & 0x04) | |
90778574 SS |
1424 | pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); |
1425 | ||
7b73ee05 SS |
1426 | pci_set_drvdata(dev, info); |
1427 | ||
90778574 SS |
1428 | return ide_setup_pci_device(dev, d); |
1429 | } | |
1430 | ||
1431 | static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d) | |
1432 | { | |
7b73ee05 | 1433 | struct hpt_info *info; |
90778574 | 1434 | |
44c10138 | 1435 | if (dev->revision > 1) { |
90778574 SS |
1436 | d->name = "HPT372N"; |
1437 | ||
7b73ee05 SS |
1438 | info = &hpt372n; |
1439 | } else | |
1440 | info = &hpt372a; | |
1441 | pci_set_drvdata(dev, info); | |
1442 | ||
90778574 SS |
1443 | return ide_setup_pci_device(dev, d); |
1444 | } | |
1445 | ||
1446 | static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d) | |
1447 | { | |
7b73ee05 | 1448 | struct hpt_info *info; |
90778574 | 1449 | |
44c10138 | 1450 | if (dev->revision > 1) { |
90778574 | 1451 | d->name = "HPT302N"; |
836c0063 | 1452 | |
7b73ee05 SS |
1453 | info = &hpt302n; |
1454 | } else | |
1455 | info = &hpt302; | |
1456 | pci_set_drvdata(dev, info); | |
1457 | ||
836c0063 SS |
1458 | return ide_setup_pci_device(dev, d); |
1459 | } | |
1460 | ||
1da177e4 LT |
1461 | static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) |
1462 | { | |
b4586715 | 1463 | struct pci_dev *dev2; |
44c10138 | 1464 | u8 rev = dev->revision; |
90778574 SS |
1465 | static char *chipset_names[] = { "HPT366", "HPT366", "HPT368", |
1466 | "HPT370", "HPT370A", "HPT372", | |
1467 | "HPT372N" }; | |
7b73ee05 SS |
1468 | static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x, |
1469 | &hpt370, &hpt370a, &hpt372, | |
1470 | &hpt372n }; | |
1da177e4 LT |
1471 | |
1472 | if (PCI_FUNC(dev->devfn) & 1) | |
1473 | return -ENODEV; | |
1474 | ||
2648e5d9 SS |
1475 | switch (rev) { |
1476 | case 0: | |
1477 | case 1: | |
1478 | case 2: | |
1479 | /* | |
1480 | * HPT36x chips have one channel per function and have | |
1481 | * both channel enable bits located differently and visible | |
1482 | * to both functions -- really stupid design decision... :-( | |
1483 | * Bit 4 is for the primary channel, bit 5 for the secondary. | |
1484 | */ | |
a5d8c5c8 | 1485 | d->host_flags |= IDE_HFLAG_SINGLE; |
2648e5d9 SS |
1486 | d->enablebits[0].mask = d->enablebits[0].val = 0x10; |
1487 | ||
2808b0a9 SS |
1488 | d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? |
1489 | ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2; | |
2648e5d9 SS |
1490 | break; |
1491 | case 3: | |
1492 | case 4: | |
2808b0a9 | 1493 | d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4; |
2648e5d9 SS |
1494 | break; |
1495 | default: | |
e139b0b0 | 1496 | rev = 6; |
2648e5d9 SS |
1497 | /* fall thru */ |
1498 | case 5: | |
1499 | case 6: | |
2808b0a9 | 1500 | d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5; |
2648e5d9 SS |
1501 | break; |
1502 | } | |
1503 | ||
90778574 | 1504 | d->name = chipset_names[rev]; |
1da177e4 | 1505 | |
7b73ee05 SS |
1506 | pci_set_drvdata(dev, info[rev]); |
1507 | ||
90778574 SS |
1508 | if (rev > 2) |
1509 | goto init_single; | |
1da177e4 | 1510 | |
b4586715 | 1511 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { |
96dcc08b | 1512 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; |
b4586715 SS |
1513 | int ret; |
1514 | ||
7b73ee05 SS |
1515 | pci_set_drvdata(dev2, info[rev]); |
1516 | ||
96dcc08b SS |
1517 | /* |
1518 | * Now we'll have to force both channels enabled if | |
1519 | * at least one of them has been enabled by BIOS... | |
1520 | */ | |
1521 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1522 | if (mcr1 & 0x30) | |
1523 | pci_write_config_byte(dev, 0x50, mcr1 | 0x30); | |
1524 | ||
b4586715 SS |
1525 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); |
1526 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); | |
1527 | if (pin1 != pin2 && dev->irq == dev2->irq) { | |
7cab14a7 | 1528 | d->host_flags |= IDE_HFLAG_BOOTABLE; |
b4586715 SS |
1529 | printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", |
1530 | d->name, pin1, pin2); | |
1da177e4 | 1531 | } |
b4586715 SS |
1532 | ret = ide_setup_pci_devices(dev, dev2, d); |
1533 | if (ret < 0) | |
1534 | pci_dev_put(dev2); | |
1535 | return ret; | |
1da177e4 LT |
1536 | } |
1537 | init_single: | |
1538 | return ide_setup_pci_device(dev, d); | |
1539 | } | |
1540 | ||
1541 | static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |
1542 | { /* 0 */ | |
1543 | .name = "HPT366", | |
1544 | .init_setup = init_setup_hpt366, | |
1545 | .init_chipset = init_chipset_hpt366, | |
1546 | .init_hwif = init_hwif_hpt366, | |
1547 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1548 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1549 | .extra = 240, |
7cab14a7 | 1550 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1551 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1552 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1553 | },{ /* 1 */ |
1554 | .name = "HPT372A", | |
90778574 | 1555 | .init_setup = init_setup_hpt372a, |
1da177e4 LT |
1556 | .init_chipset = init_chipset_hpt366, |
1557 | .init_hwif = init_hwif_hpt366, | |
1558 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1559 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1560 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
4099d143 | 1561 | .extra = 240, |
7cab14a7 | 1562 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1563 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1564 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1565 | },{ /* 2 */ |
1566 | .name = "HPT302", | |
90778574 | 1567 | .init_setup = init_setup_hpt302, |
1da177e4 LT |
1568 | .init_chipset = init_chipset_hpt366, |
1569 | .init_hwif = init_hwif_hpt366, | |
1570 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1571 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1572 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
4099d143 | 1573 | .extra = 240, |
7cab14a7 | 1574 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1575 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1576 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1577 | },{ /* 3 */ |
1578 | .name = "HPT371", | |
836c0063 | 1579 | .init_setup = init_setup_hpt371, |
1da177e4 LT |
1580 | .init_chipset = init_chipset_hpt366, |
1581 | .init_hwif = init_hwif_hpt366, | |
1582 | .init_dma = init_dma_hpt366, | |
836c0063 | 1583 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1584 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
4099d143 | 1585 | .extra = 240, |
7cab14a7 | 1586 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1587 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1588 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1589 | },{ /* 4 */ |
1590 | .name = "HPT374", | |
1591 | .init_setup = init_setup_hpt374, | |
1592 | .init_chipset = init_chipset_hpt366, | |
1593 | .init_hwif = init_hwif_hpt366, | |
1594 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1595 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1596 | .udma_mask = ATA_UDMA5, |
4099d143 | 1597 | .extra = 240, |
7cab14a7 | 1598 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1599 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1600 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1601 | },{ /* 5 */ |
1602 | .name = "HPT372N", | |
90778574 | 1603 | .init_setup = init_setup_hpt372n, |
1da177e4 LT |
1604 | .init_chipset = init_chipset_hpt366, |
1605 | .init_hwif = init_hwif_hpt366, | |
1606 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1607 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1608 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
4099d143 | 1609 | .extra = 240, |
7cab14a7 | 1610 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, |
4099d143 | 1611 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1612 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1613 | } |
1614 | }; | |
1615 | ||
1616 | /** | |
1617 | * hpt366_init_one - called when an HPT366 is found | |
1618 | * @dev: the hpt366 device | |
1619 | * @id: the matching pci id | |
1620 | * | |
1621 | * Called when the PCI registration layer (or the IDE initialization) | |
1622 | * finds a device matching our IDE device tables. | |
73d1dd93 SS |
1623 | * |
1624 | * NOTE: since we'll have to modify some fields of the ide_pci_device_t | |
1625 | * structure depending on the chip's revision, we'd better pass a local | |
1626 | * copy down the call chain... | |
1da177e4 | 1627 | */ |
1da177e4 LT |
1628 | static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1629 | { | |
73d1dd93 | 1630 | ide_pci_device_t d = hpt366_chipsets[id->driver_data]; |
1da177e4 | 1631 | |
73d1dd93 | 1632 | return d.init_setup(dev, &d); |
1da177e4 LT |
1633 | } |
1634 | ||
9cbcc5e3 BZ |
1635 | static const struct pci_device_id hpt366_pci_tbl[] = { |
1636 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, | |
1637 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, | |
1638 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, | |
1639 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, | |
1640 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, | |
1641 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, | |
1da177e4 LT |
1642 | { 0, }, |
1643 | }; | |
1644 | MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); | |
1645 | ||
1646 | static struct pci_driver driver = { | |
1647 | .name = "HPT366_IDE", | |
1648 | .id_table = hpt366_pci_tbl, | |
1649 | .probe = hpt366_init_one, | |
1650 | }; | |
1651 | ||
82ab1eec | 1652 | static int __init hpt366_ide_init(void) |
1da177e4 LT |
1653 | { |
1654 | return ide_pci_register_driver(&driver); | |
1655 | } | |
1656 | ||
1657 | module_init(hpt366_ide_init); | |
1658 | ||
1659 | MODULE_AUTHOR("Andre Hedrick"); | |
1660 | MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); | |
1661 | MODULE_LICENSE("GPL"); |