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da9091ee AC |
1 | |
2 | /* | |
52374f89 | 3 | * linux/drivers/ide/pci/it821x.c Version 0.16 Jul 3 2007 |
da9091ee AC |
4 | * |
5 | * Copyright (C) 2004 Red Hat <alan@redhat.com> | |
0e9b4e53 | 6 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
da9091ee AC |
7 | * |
8 | * May be copied or modified under the terms of the GNU General Public License | |
9 | * Based in part on the ITE vendor provided SCSI driver. | |
10 | * | |
11 | * Documentation available from | |
12 | * http://www.ite.com.tw/pc/IT8212F_V04.pdf | |
13 | * Some other documents are NDA. | |
14 | * | |
15 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
16 | * modes. In pass through mode then it is an IDE controller. In its smart | |
17 | * mode its actually quite a capable hardware raid controller disguised | |
18 | * as an IDE controller. Smart mode only understands DMA read/write and | |
19 | * identify, none of the fancier commands apply. The IT8211 is identical | |
20 | * in other respects but lacks the raid mode. | |
21 | * | |
22 | * Errata: | |
23 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
24 | * cannot do ATAPI MWDMA. | |
25 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
26 | * but also fails to set the LBA28 and other bits. We fix these in | |
27 | * the IDE probe quirk code. | |
28 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
29 | * raid then the controller firmware dies | |
30 | * o Smart mode without RAID doesn't clear all the necessary identify | |
31 | * bits to reduce the command set to the one used | |
32 | * | |
33 | * This has a few impacts on the driver | |
34 | * - In pass through mode we do all the work you would expect | |
35 | * - In smart mode the clocking set up is done by the controller generally | |
36 | * but we must watch the other limits and filter. | |
37 | * - There are a few extra vendor commands that actually talk to the | |
38 | * controller but only work PIO with no IRQ. | |
39 | * | |
40 | * Vendor areas of the identify block in smart mode are used for the | |
41 | * timing and policy set up. Each HDD in raid mode also has a serial | |
42 | * block on the disk. The hardware extra commands are get/set chip status, | |
43 | * rebuild, get rebuild status. | |
44 | * | |
45 | * In Linux the driver supports pass through mode as if the device was | |
46 | * just another IDE controller. If the smart mode is running then | |
47 | * volumes are managed by the controller firmware and each IDE "disk" | |
48 | * is a raid volume. Even more cute - the controller can do automated | |
49 | * hotplug and rebuild. | |
50 | * | |
51 | * The pass through controller itself is a little demented. It has a | |
52 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
53 | * non UDMA devices restrict each others performance. It also has a | |
54 | * single clock source per channel so mixed UDMA100/133 performance | |
55 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
56 | * matters in smart mode. ATAPI DMA is not currently supported. | |
57 | * | |
58 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
59 | * | |
60 | * TODO | |
61 | * - ATAPI UDMA is ok but not MWDMA it seems | |
62 | * - RAID configuration ioctls | |
63 | * - Move to libata once it grows up | |
64 | */ | |
65 | ||
da9091ee AC |
66 | #include <linux/types.h> |
67 | #include <linux/module.h> | |
68 | #include <linux/pci.h> | |
69 | #include <linux/delay.h> | |
70 | #include <linux/hdreg.h> | |
71 | #include <linux/ide.h> | |
72 | #include <linux/init.h> | |
73 | ||
74 | #include <asm/io.h> | |
75 | ||
76 | struct it821x_dev | |
77 | { | |
78 | unsigned int smart:1, /* Are we in smart raid mode */ | |
79 | timing10:1; /* Rev 0x10 */ | |
80 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
81 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
82 | /* We need these for switching the clock when DMA goes on/off | |
83 | The high byte is the 66Mhz timing */ | |
84 | u16 pio[2]; /* Cached PIO values */ | |
85 | u16 mwdma[2]; /* Cached MWDMA values */ | |
86 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
87 | }; | |
88 | ||
89 | #define ATA_66 0 | |
90 | #define ATA_50 1 | |
91 | #define ATA_ANY 2 | |
92 | ||
93 | #define UDMA_OFF 0 | |
94 | #define MWDMA_OFF 0 | |
95 | ||
96 | /* | |
97 | * We allow users to force the card into non raid mode without | |
3a4fa0a2 | 98 | * flashing the alternative BIOS. This is also necessary right now |
da9091ee AC |
99 | * for embedded platforms that cannot run a PC BIOS but are using this |
100 | * device. | |
101 | */ | |
102 | ||
103 | static int it8212_noraid; | |
104 | ||
105 | /** | |
106 | * it821x_program - program the PIO/MWDMA registers | |
107 | * @drive: drive to tune | |
0e9b4e53 | 108 | * @timing: timing info |
da9091ee AC |
109 | * |
110 | * Program the PIO/MWDMA timing for this channel according to the | |
111 | * current clock. | |
112 | */ | |
113 | ||
114 | static void it821x_program(ide_drive_t *drive, u16 timing) | |
115 | { | |
36501650 BZ |
116 | ide_hwif_t *hwif = drive->hwif; |
117 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
118 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
119 | int channel = hwif->channel; | |
120 | u8 conf; | |
121 | ||
122 | /* Program PIO/MWDMA timing bits */ | |
123 | if(itdev->clock_mode == ATA_66) | |
124 | conf = timing >> 8; | |
125 | else | |
126 | conf = timing & 0xFF; | |
36501650 BZ |
127 | |
128 | pci_write_config_byte(dev, 0x54 + 4 * channel, conf); | |
da9091ee AC |
129 | } |
130 | ||
131 | /** | |
132 | * it821x_program_udma - program the UDMA registers | |
133 | * @drive: drive to tune | |
0e9b4e53 | 134 | * @timing: timing info |
da9091ee AC |
135 | * |
136 | * Program the UDMA timing for this drive according to the | |
137 | * current clock. | |
138 | */ | |
139 | ||
140 | static void it821x_program_udma(ide_drive_t *drive, u16 timing) | |
141 | { | |
36501650 BZ |
142 | ide_hwif_t *hwif = drive->hwif; |
143 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
144 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
145 | int channel = hwif->channel; | |
146 | int unit = drive->select.b.unit; | |
147 | u8 conf; | |
148 | ||
149 | /* Program UDMA timing bits */ | |
150 | if(itdev->clock_mode == ATA_66) | |
151 | conf = timing >> 8; | |
152 | else | |
153 | conf = timing & 0xFF; | |
36501650 BZ |
154 | |
155 | if (itdev->timing10 == 0) | |
156 | pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); | |
da9091ee | 157 | else { |
36501650 BZ |
158 | pci_write_config_byte(dev, 0x56 + 4 * channel, conf); |
159 | pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); | |
da9091ee AC |
160 | } |
161 | } | |
162 | ||
da9091ee AC |
163 | /** |
164 | * it821x_clock_strategy | |
0e9b4e53 | 165 | * @drive: drive to set up |
da9091ee AC |
166 | * |
167 | * Select between the 50 and 66Mhz base clocks to get the best | |
168 | * results for this interface. | |
169 | */ | |
170 | ||
171 | static void it821x_clock_strategy(ide_drive_t *drive) | |
172 | { | |
173 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 174 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee AC |
175 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
176 | ||
177 | u8 unit = drive->select.b.unit; | |
178 | ide_drive_t *pair = &hwif->drives[1-unit]; | |
179 | ||
180 | int clock, altclock; | |
181 | u8 v; | |
182 | int sel = 0; | |
183 | ||
184 | if(itdev->want[0][0] > itdev->want[1][0]) { | |
185 | clock = itdev->want[0][1]; | |
186 | altclock = itdev->want[1][1]; | |
187 | } else { | |
188 | clock = itdev->want[1][1]; | |
189 | altclock = itdev->want[0][1]; | |
190 | } | |
191 | ||
0e9b4e53 BZ |
192 | /* |
193 | * if both clocks can be used for the mode with the higher priority | |
194 | * use the clock needed by the mode with the lower priority | |
195 | */ | |
196 | if (clock == ATA_ANY) | |
da9091ee AC |
197 | clock = altclock; |
198 | ||
199 | /* Nobody cares - keep the same clock */ | |
200 | if(clock == ATA_ANY) | |
201 | return; | |
202 | /* No change */ | |
203 | if(clock == itdev->clock_mode) | |
204 | return; | |
205 | ||
206 | /* Load this into the controller ? */ | |
207 | if(clock == ATA_66) | |
208 | itdev->clock_mode = ATA_66; | |
209 | else { | |
210 | itdev->clock_mode = ATA_50; | |
211 | sel = 1; | |
212 | } | |
36501650 BZ |
213 | |
214 | pci_read_config_byte(dev, 0x50, &v); | |
da9091ee AC |
215 | v &= ~(1 << (1 + hwif->channel)); |
216 | v |= sel << (1 + hwif->channel); | |
36501650 | 217 | pci_write_config_byte(dev, 0x50, v); |
da9091ee AC |
218 | |
219 | /* | |
220 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
221 | * MWDMA will be dealt with by the dma switcher | |
222 | */ | |
223 | if(pair && itdev->udma[1-unit] != UDMA_OFF) { | |
224 | it821x_program_udma(pair, itdev->udma[1-unit]); | |
225 | it821x_program(pair, itdev->pio[1-unit]); | |
226 | } | |
227 | /* | |
228 | * Reprogram the UDMA/PIO of our drive for the switch. | |
229 | * MWDMA will be dealt with by the dma switcher | |
230 | */ | |
231 | if(itdev->udma[unit] != UDMA_OFF) { | |
232 | it821x_program_udma(drive, itdev->udma[unit]); | |
233 | it821x_program(drive, itdev->pio[unit]); | |
234 | } | |
235 | } | |
236 | ||
da9091ee | 237 | /** |
88b2b32b BZ |
238 | * it821x_set_pio_mode - set host controller for PIO mode |
239 | * @drive: drive | |
240 | * @pio: PIO mode number | |
da9091ee | 241 | * |
88b2b32b BZ |
242 | * Tune the host to the desired PIO mode taking into the consideration |
243 | * the maximum PIO mode supported by the other device on the cable. | |
da9091ee AC |
244 | */ |
245 | ||
88b2b32b | 246 | static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
da9091ee AC |
247 | { |
248 | ide_hwif_t *hwif = drive->hwif; | |
249 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
250 | int unit = drive->select.b.unit; | |
0e9b4e53 | 251 | ide_drive_t *pair = &hwif->drives[1 - unit]; |
88b2b32b | 252 | u8 set_pio = pio; |
da9091ee AC |
253 | |
254 | /* Spec says 89 ref driver uses 88 */ | |
88b2b32b | 255 | static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
da9091ee AC |
256 | static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
257 | ||
0e9b4e53 BZ |
258 | /* |
259 | * Compute the best PIO mode we can for a given device. We must | |
260 | * pick a speed that does not cause problems with the other device | |
261 | * on the cable. | |
262 | */ | |
263 | if (pair) { | |
2134758d | 264 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
0e9b4e53 BZ |
265 | /* trim PIO to the slowest of the master/slave */ |
266 | if (pair_pio < set_pio) | |
267 | set_pio = pair_pio; | |
268 | } | |
269 | ||
da9091ee | 270 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
0e9b4e53 | 271 | itdev->want[unit][1] = pio_want[set_pio]; |
da9091ee | 272 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
88b2b32b | 273 | itdev->pio[unit] = pio_timings[set_pio]; |
da9091ee AC |
274 | it821x_clock_strategy(drive); |
275 | it821x_program(drive, itdev->pio[unit]); | |
276 | } | |
277 | ||
278 | /** | |
279 | * it821x_tune_mwdma - tune a channel for MWDMA | |
280 | * @drive: drive to set up | |
281 | * @mode_wanted: the target operating mode | |
282 | * | |
283 | * Load the timing settings for this device mode into the | |
284 | * controller when doing MWDMA in pass through mode. The caller | |
285 | * must manage the whole lack of per device MWDMA/PIO timings and | |
286 | * the shared MWDMA/PIO timing register. | |
287 | */ | |
288 | ||
289 | static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted) | |
290 | { | |
36501650 BZ |
291 | ide_hwif_t *hwif = drive->hwif; |
292 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
293 | struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
294 | int unit = drive->select.b.unit; | |
295 | int channel = hwif->channel; | |
296 | u8 conf; | |
297 | ||
298 | static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
299 | static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
300 | ||
301 | itdev->want[unit][1] = mwdma_want[mode_wanted]; | |
302 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
303 | itdev->mwdma[unit] = dma[mode_wanted]; | |
304 | itdev->udma[unit] = UDMA_OFF; | |
305 | ||
306 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
36501650 BZ |
307 | pci_read_config_byte(dev, 0x50, &conf); |
308 | if (itdev->timing10) | |
da9091ee AC |
309 | conf |= channel ? 0x60: 0x18; |
310 | else | |
311 | conf |= 1 << (3 + 2 * channel + unit); | |
36501650 | 312 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
313 | |
314 | it821x_clock_strategy(drive); | |
315 | /* FIXME: do we need to program this ? */ | |
316 | /* it821x_program(drive, itdev->mwdma[unit]); */ | |
317 | } | |
318 | ||
319 | /** | |
320 | * it821x_tune_udma - tune a channel for UDMA | |
321 | * @drive: drive to set up | |
322 | * @mode_wanted: the target operating mode | |
323 | * | |
324 | * Load the timing settings for this device mode into the | |
325 | * controller when doing UDMA modes in pass through. | |
326 | */ | |
327 | ||
328 | static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted) | |
329 | { | |
36501650 BZ |
330 | ide_hwif_t *hwif = drive->hwif; |
331 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
332 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
333 | int unit = drive->select.b.unit; | |
334 | int channel = hwif->channel; | |
335 | u8 conf; | |
336 | ||
337 | static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
338 | static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
339 | ||
340 | itdev->want[unit][1] = udma_want[mode_wanted]; | |
341 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
342 | itdev->mwdma[unit] = MWDMA_OFF; | |
343 | itdev->udma[unit] = udma[mode_wanted]; | |
344 | if(mode_wanted >= 5) | |
345 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
346 | ||
347 | /* UDMA on. Again revision 0x10 must do the pair */ | |
36501650 BZ |
348 | pci_read_config_byte(dev, 0x50, &conf); |
349 | if (itdev->timing10) | |
da9091ee AC |
350 | conf &= channel ? 0x9F: 0xE7; |
351 | else | |
352 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
36501650 | 353 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
354 | |
355 | it821x_clock_strategy(drive); | |
356 | it821x_program_udma(drive, itdev->udma[unit]); | |
357 | ||
358 | } | |
359 | ||
da9091ee AC |
360 | /** |
361 | * it821x_dma_read - DMA hook | |
362 | * @drive: drive for DMA | |
363 | * | |
364 | * The IT821x has a single timing register for MWDMA and for PIO | |
365 | * operations. As we flip back and forth we have to reload the | |
366 | * clock. In addition the rev 0x10 device only works if the same | |
367 | * timing value is loaded into the master and slave UDMA clock | |
368 | * so we must also reload that. | |
369 | * | |
370 | * FIXME: we could figure out in advance if we need to do reloads | |
371 | */ | |
372 | ||
373 | static void it821x_dma_start(ide_drive_t *drive) | |
374 | { | |
375 | ide_hwif_t *hwif = drive->hwif; | |
376 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
377 | int unit = drive->select.b.unit; | |
378 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
379 | it821x_program(drive, itdev->mwdma[unit]); | |
380 | else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
381 | it821x_program_udma(drive, itdev->udma[unit]); | |
382 | ide_dma_start(drive); | |
383 | } | |
384 | ||
385 | /** | |
386 | * it821x_dma_write - DMA hook | |
387 | * @drive: drive for DMA stop | |
388 | * | |
389 | * The IT821x has a single timing register for MWDMA and for PIO | |
390 | * operations. As we flip back and forth we have to reload the | |
391 | * clock. | |
392 | */ | |
393 | ||
394 | static int it821x_dma_end(ide_drive_t *drive) | |
395 | { | |
396 | ide_hwif_t *hwif = drive->hwif; | |
397 | int unit = drive->select.b.unit; | |
398 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
399 | int ret = __ide_dma_end(drive); | |
400 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
401 | it821x_program(drive, itdev->pio[unit]); | |
402 | return ret; | |
403 | } | |
404 | ||
da9091ee | 405 | /** |
88b2b32b BZ |
406 | * it821x_set_dma_mode - set host controller for DMA mode |
407 | * @drive: drive | |
408 | * @speed: DMA mode | |
da9091ee | 409 | * |
88b2b32b | 410 | * Tune the ITE chipset for the desired DMA mode. |
da9091ee AC |
411 | */ |
412 | ||
88b2b32b | 413 | static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
da9091ee | 414 | { |
88b2b32b BZ |
415 | /* |
416 | * MWDMA tuning is really hard because our MWDMA and PIO | |
417 | * timings are kept in the same place. We can switch in the | |
418 | * host dma on/off callbacks. | |
419 | */ | |
420 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) | |
421 | it821x_tune_udma(drive, speed - XFER_UDMA_0); | |
422 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | |
423 | it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); | |
da9091ee AC |
424 | } |
425 | ||
da9091ee AC |
426 | /** |
427 | * ata66_it821x - check for 80 pin cable | |
428 | * @hwif: interface to check | |
429 | * | |
430 | * Check for the presence of an ATA66 capable cable on the | |
431 | * interface. Problematic as it seems some cards don't have | |
432 | * the needed logic onboard. | |
433 | */ | |
434 | ||
49521f97 | 435 | static u8 __devinit ata66_it821x(ide_hwif_t *hwif) |
da9091ee AC |
436 | { |
437 | /* The reference driver also only does disk side */ | |
49521f97 | 438 | return ATA_CBL_PATA80; |
da9091ee AC |
439 | } |
440 | ||
441 | /** | |
f01393e4 BZ |
442 | * it821x_quirkproc - post init callback |
443 | * @drive: drive | |
da9091ee | 444 | * |
f01393e4 | 445 | * This callback is run after the drive has been probed but |
da9091ee AC |
446 | * before anything gets attached. It allows drivers to do any |
447 | * final tuning that is needed, or fixups to work around bugs. | |
448 | */ | |
449 | ||
f01393e4 | 450 | static void __devinit it821x_quirkproc(ide_drive_t *drive) |
da9091ee | 451 | { |
f01393e4 BZ |
452 | struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
453 | struct hd_driveid *id = drive->id; | |
454 | u16 *idbits = (u16 *)drive->id; | |
da9091ee | 455 | |
f01393e4 | 456 | if (!itdev->smart) { |
da9091ee AC |
457 | /* |
458 | * If we are in pass through mode then not much | |
459 | * needs to be done, but we do bother to clear the | |
460 | * IRQ mask as we may well be in PIO (eg rev 0x10) | |
461 | * for now and we know unmasking is safe on this chipset. | |
462 | */ | |
f01393e4 BZ |
463 | drive->unmask = 1; |
464 | } else { | |
da9091ee AC |
465 | /* |
466 | * Perform fixups on smart mode. We need to "lose" some | |
467 | * capabilities the firmware lacks but does not filter, and | |
468 | * also patch up some capability bits that it forgets to set | |
469 | * in RAID mode. | |
470 | */ | |
471 | ||
da9091ee AC |
472 | /* Check for RAID v native */ |
473 | if(strstr(id->model, "Integrated Technology Express")) { | |
474 | /* In raid mode the ident block is slightly buggy | |
475 | We need to set the bits so that the IDE layer knows | |
476 | LBA28. LBA48 and DMA ar valid */ | |
477 | id->capability |= 3; /* LBA28, DMA */ | |
478 | id->command_set_2 |= 0x0400; /* LBA48 valid */ | |
479 | id->cfs_enable_2 |= 0x0400; /* LBA48 on */ | |
480 | /* Reporting logic */ | |
481 | printk(KERN_INFO "%s: IT8212 %sRAID %d volume", | |
482 | drive->name, | |
483 | idbits[147] ? "Bootable ":"", | |
484 | idbits[129]); | |
485 | if(idbits[129] != 1) | |
486 | printk("(%dK stripe)", idbits[146]); | |
487 | printk(".\n"); | |
da9091ee AC |
488 | } else { |
489 | /* Non RAID volume. Fixups to stop the core code | |
490 | doing unsupported things */ | |
0380dad4 | 491 | id->field_valid &= 3; |
da9091ee AC |
492 | id->queue_depth = 0; |
493 | id->command_set_1 = 0; | |
494 | id->command_set_2 &= 0xC400; | |
495 | id->cfsse &= 0xC000; | |
496 | id->cfs_enable_1 = 0; | |
497 | id->cfs_enable_2 &= 0xC400; | |
498 | id->csf_default &= 0xC000; | |
499 | id->word127 = 0; | |
500 | id->dlf = 0; | |
501 | id->csfo = 0; | |
502 | id->cfa_power = 0; | |
503 | printk(KERN_INFO "%s: Performing identify fixups.\n", | |
504 | drive->name); | |
505 | } | |
0380dad4 BZ |
506 | |
507 | /* | |
508 | * Set MWDMA0 mode as enabled/support - just to tell | |
509 | * IDE core that DMA is supported (it821x hardware | |
510 | * takes care of DMA mode programming). | |
511 | */ | |
512 | if (id->capability & 1) { | |
513 | id->dma_mword |= 0x0101; | |
514 | drive->current_speed = XFER_MW_DMA_0; | |
515 | } | |
da9091ee AC |
516 | } |
517 | ||
518 | } | |
519 | ||
520 | /** | |
521 | * init_hwif_it821x - set up hwif structs | |
522 | * @hwif: interface to set up | |
523 | * | |
524 | * We do the basic set up of the interface structure. The IT8212 | |
525 | * requires several custom handlers so we override the default | |
526 | * ide DMA handlers appropriately | |
527 | */ | |
528 | ||
529 | static void __devinit init_hwif_it821x(ide_hwif_t *hwif) | |
530 | { | |
36501650 | 531 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
f5e3c2fa | 532 | struct it821x_dev *idev = kzalloc(sizeof(struct it821x_dev), GFP_KERNEL); |
da9091ee AC |
533 | u8 conf; |
534 | ||
f01393e4 BZ |
535 | hwif->quirkproc = &it821x_quirkproc; |
536 | ||
9ff6f72f | 537 | if (idev == NULL) { |
da9091ee | 538 | printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n"); |
9ff6f72f | 539 | return; |
da9091ee | 540 | } |
9ff6f72f | 541 | |
da9091ee AC |
542 | ide_set_hwifdata(hwif, idev); |
543 | ||
36501650 | 544 | pci_read_config_byte(dev, 0x50, &conf); |
33c1002e | 545 | if (conf & 1) { |
da9091ee | 546 | idev->smart = 1; |
33c1002e | 547 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
da9091ee AC |
548 | /* Long I/O's although allowed in LBA48 space cause the |
549 | onboard firmware to enter the twighlight zone */ | |
550 | hwif->rqsize = 256; | |
551 | } | |
552 | ||
553 | /* Pull the current clocks from 0x50 also */ | |
554 | if (conf & (1 << (1 + hwif->channel))) | |
555 | idev->clock_mode = ATA_50; | |
556 | else | |
557 | idev->clock_mode = ATA_66; | |
558 | ||
559 | idev->want[0][1] = ATA_ANY; | |
560 | idev->want[1][1] = ATA_ANY; | |
561 | ||
562 | /* | |
563 | * Not in the docs but according to the reference driver | |
3a4fa0a2 | 564 | * this is necessary. |
da9091ee AC |
565 | */ |
566 | ||
36501650 | 567 | pci_read_config_byte(dev, 0x08, &conf); |
33c1002e | 568 | if (conf == 0x10) { |
da9091ee | 569 | idev->timing10 = 1; |
33c1002e BZ |
570 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
571 | if (idev->smart == 0) | |
da9091ee AC |
572 | printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n"); |
573 | } | |
574 | ||
88b2b32b BZ |
575 | if (idev->smart == 0) { |
576 | hwif->set_pio_mode = &it821x_set_pio_mode; | |
577 | hwif->set_dma_mode = &it821x_set_dma_mode; | |
da9091ee | 578 | |
88b2b32b | 579 | /* MWDMA/PIO clock switching for pass through mode */ |
da9091ee AC |
580 | hwif->dma_start = &it821x_dma_start; |
581 | hwif->ide_dma_end = &it821x_dma_end; | |
88b2b32b BZ |
582 | } else |
583 | hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; | |
da9091ee | 584 | |
9ff6f72f BZ |
585 | if (hwif->dma_base == 0) |
586 | return; | |
da9091ee | 587 | |
5f8b6c34 BZ |
588 | hwif->ultra_mask = ATA_UDMA6; |
589 | hwif->mwdma_mask = ATA_MWDMA2; | |
da9091ee | 590 | |
49521f97 BZ |
591 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
592 | hwif->cbl = ata66_it821x(hwif); | |
da9091ee AC |
593 | } |
594 | ||
595 | static void __devinit it8212_disable_raid(struct pci_dev *dev) | |
596 | { | |
597 | /* Reset local CPU, and set BIOS not ready */ | |
598 | pci_write_config_byte(dev, 0x5E, 0x01); | |
599 | ||
600 | /* Set to bypass mode, and reset PCI bus */ | |
601 | pci_write_config_byte(dev, 0x50, 0x00); | |
602 | pci_write_config_word(dev, PCI_COMMAND, | |
603 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
604 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
605 | pci_write_config_word(dev, 0x40, 0xA0F3); | |
606 | ||
607 | pci_write_config_dword(dev,0x4C, 0x02040204); | |
608 | pci_write_config_byte(dev, 0x42, 0x36); | |
0c866b51 | 609 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
da9091ee AC |
610 | } |
611 | ||
612 | static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name) | |
613 | { | |
614 | u8 conf; | |
615 | static char *mode[2] = { "pass through", "smart" }; | |
616 | ||
617 | /* Force the card into bypass mode if so requested */ | |
618 | if (it8212_noraid) { | |
619 | printk(KERN_INFO "it8212: forcing bypass mode.\n"); | |
620 | it8212_disable_raid(dev); | |
621 | } | |
622 | pci_read_config_byte(dev, 0x50, &conf); | |
623 | printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]); | |
624 | return 0; | |
625 | } | |
626 | ||
627 | ||
628 | #define DECLARE_ITE_DEV(name_str) \ | |
629 | { \ | |
630 | .name = name_str, \ | |
631 | .init_chipset = init_chipset_it821x, \ | |
632 | .init_hwif = init_hwif_it821x, \ | |
7cab14a7 | 633 | .host_flags = IDE_HFLAG_BOOTABLE, \ |
4099d143 | 634 | .pio_mask = ATA_PIO4, \ |
da9091ee AC |
635 | } |
636 | ||
85620436 | 637 | static const struct ide_port_info it821x_chipsets[] __devinitdata = { |
da9091ee AC |
638 | /* 0 */ DECLARE_ITE_DEV("IT8212"), |
639 | }; | |
640 | ||
641 | /** | |
642 | * it821x_init_one - pci layer discovery entry | |
643 | * @dev: PCI device | |
644 | * @id: ident table entry | |
645 | * | |
646 | * Called by the PCI code when it finds an ITE821x controller. | |
647 | * We then use the IDE PCI generic helper to do most of the work. | |
648 | */ | |
649 | ||
650 | static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
651 | { | |
24ffbd62 | 652 | return ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]); |
da9091ee AC |
653 | } |
654 | ||
9cbcc5e3 BZ |
655 | static const struct pci_device_id it821x_pci_tbl[] = { |
656 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, | |
657 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, | |
da9091ee AC |
658 | { 0, }, |
659 | }; | |
660 | ||
661 | MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); | |
662 | ||
663 | static struct pci_driver driver = { | |
664 | .name = "ITE821x IDE", | |
665 | .id_table = it821x_pci_tbl, | |
666 | .probe = it821x_init_one, | |
667 | }; | |
668 | ||
669 | static int __init it821x_ide_init(void) | |
670 | { | |
671 | return ide_pci_register_driver(&driver); | |
672 | } | |
673 | ||
674 | module_init(it821x_ide_init); | |
675 | ||
676 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); | |
677 | MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode"); | |
678 | ||
679 | MODULE_AUTHOR("Alan Cox"); | |
680 | MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); | |
681 | MODULE_LICENSE("GPL"); |