ide: cleanup ide_fix_driveid()
[deliverable/linux.git] / drivers / ide / pci / it821x.c
CommitLineData
da9091ee 1/*
da9091ee 2 * Copyright (C) 2004 Red Hat <alan@redhat.com>
0e9b4e53 3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
da9091ee
AC
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
7 *
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
11 *
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
18 *
19 * Errata:
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
29 *
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
36 *
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
41 *
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
47 *
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
54 *
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
56 *
57 * TODO
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
61 */
62
da9091ee
AC
63#include <linux/types.h>
64#include <linux/module.h>
65#include <linux/pci.h>
da9091ee
AC
66#include <linux/hdreg.h>
67#include <linux/ide.h>
68#include <linux/init.h>
69
ced3ec8a
BZ
70#define DRV_NAME "it821x"
71
da9091ee
AC
72struct it821x_dev
73{
74 unsigned int smart:1, /* Are we in smart raid mode */
75 timing10:1; /* Rev 0x10 */
76 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
77 u8 want[2][2]; /* Mode/Pri log for master slave */
78 /* We need these for switching the clock when DMA goes on/off
79 The high byte is the 66Mhz timing */
80 u16 pio[2]; /* Cached PIO values */
81 u16 mwdma[2]; /* Cached MWDMA values */
82 u16 udma[2]; /* Cached UDMA values (per drive) */
83};
84
85#define ATA_66 0
86#define ATA_50 1
87#define ATA_ANY 2
88
89#define UDMA_OFF 0
90#define MWDMA_OFF 0
91
92/*
93 * We allow users to force the card into non raid mode without
3a4fa0a2 94 * flashing the alternative BIOS. This is also necessary right now
da9091ee
AC
95 * for embedded platforms that cannot run a PC BIOS but are using this
96 * device.
97 */
98
99static int it8212_noraid;
100
101/**
102 * it821x_program - program the PIO/MWDMA registers
103 * @drive: drive to tune
0e9b4e53 104 * @timing: timing info
da9091ee
AC
105 *
106 * Program the PIO/MWDMA timing for this channel according to the
107 * current clock.
108 */
109
110static void it821x_program(ide_drive_t *drive, u16 timing)
111{
36501650
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112 ide_hwif_t *hwif = drive->hwif;
113 struct pci_dev *dev = to_pci_dev(hwif->dev);
da9091ee
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114 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
115 int channel = hwif->channel;
116 u8 conf;
117
118 /* Program PIO/MWDMA timing bits */
119 if(itdev->clock_mode == ATA_66)
120 conf = timing >> 8;
121 else
122 conf = timing & 0xFF;
36501650
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123
124 pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
da9091ee
AC
125}
126
127/**
128 * it821x_program_udma - program the UDMA registers
129 * @drive: drive to tune
0e9b4e53 130 * @timing: timing info
da9091ee
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131 *
132 * Program the UDMA timing for this drive according to the
133 * current clock.
134 */
135
136static void it821x_program_udma(ide_drive_t *drive, u16 timing)
137{
36501650
BZ
138 ide_hwif_t *hwif = drive->hwif;
139 struct pci_dev *dev = to_pci_dev(hwif->dev);
da9091ee
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140 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
141 int channel = hwif->channel;
142 int unit = drive->select.b.unit;
143 u8 conf;
144
145 /* Program UDMA timing bits */
146 if(itdev->clock_mode == ATA_66)
147 conf = timing >> 8;
148 else
149 conf = timing & 0xFF;
36501650
BZ
150
151 if (itdev->timing10 == 0)
152 pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
da9091ee 153 else {
36501650
BZ
154 pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
155 pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
da9091ee
AC
156 }
157}
158
da9091ee
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159/**
160 * it821x_clock_strategy
0e9b4e53 161 * @drive: drive to set up
da9091ee
AC
162 *
163 * Select between the 50 and 66Mhz base clocks to get the best
164 * results for this interface.
165 */
166
167static void it821x_clock_strategy(ide_drive_t *drive)
168{
169 ide_hwif_t *hwif = drive->hwif;
36501650 170 struct pci_dev *dev = to_pci_dev(hwif->dev);
da9091ee
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171 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
172
173 u8 unit = drive->select.b.unit;
174 ide_drive_t *pair = &hwif->drives[1-unit];
175
176 int clock, altclock;
177 u8 v;
178 int sel = 0;
179
180 if(itdev->want[0][0] > itdev->want[1][0]) {
181 clock = itdev->want[0][1];
182 altclock = itdev->want[1][1];
183 } else {
184 clock = itdev->want[1][1];
185 altclock = itdev->want[0][1];
186 }
187
0e9b4e53
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188 /*
189 * if both clocks can be used for the mode with the higher priority
190 * use the clock needed by the mode with the lower priority
191 */
192 if (clock == ATA_ANY)
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AC
193 clock = altclock;
194
195 /* Nobody cares - keep the same clock */
196 if(clock == ATA_ANY)
197 return;
198 /* No change */
199 if(clock == itdev->clock_mode)
200 return;
201
202 /* Load this into the controller ? */
203 if(clock == ATA_66)
204 itdev->clock_mode = ATA_66;
205 else {
206 itdev->clock_mode = ATA_50;
207 sel = 1;
208 }
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209
210 pci_read_config_byte(dev, 0x50, &v);
da9091ee
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211 v &= ~(1 << (1 + hwif->channel));
212 v |= sel << (1 + hwif->channel);
36501650 213 pci_write_config_byte(dev, 0x50, v);
da9091ee
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214
215 /*
216 * Reprogram the UDMA/PIO of the pair drive for the switch
217 * MWDMA will be dealt with by the dma switcher
218 */
219 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
220 it821x_program_udma(pair, itdev->udma[1-unit]);
221 it821x_program(pair, itdev->pio[1-unit]);
222 }
223 /*
224 * Reprogram the UDMA/PIO of our drive for the switch.
225 * MWDMA will be dealt with by the dma switcher
226 */
227 if(itdev->udma[unit] != UDMA_OFF) {
228 it821x_program_udma(drive, itdev->udma[unit]);
229 it821x_program(drive, itdev->pio[unit]);
230 }
231}
232
da9091ee 233/**
88b2b32b
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234 * it821x_set_pio_mode - set host controller for PIO mode
235 * @drive: drive
236 * @pio: PIO mode number
da9091ee 237 *
88b2b32b
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238 * Tune the host to the desired PIO mode taking into the consideration
239 * the maximum PIO mode supported by the other device on the cable.
da9091ee
AC
240 */
241
88b2b32b 242static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
da9091ee
AC
243{
244 ide_hwif_t *hwif = drive->hwif;
245 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
246 int unit = drive->select.b.unit;
0e9b4e53 247 ide_drive_t *pair = &hwif->drives[1 - unit];
88b2b32b 248 u8 set_pio = pio;
da9091ee
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249
250 /* Spec says 89 ref driver uses 88 */
88b2b32b 251 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
da9091ee
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252 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
253
0e9b4e53
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254 /*
255 * Compute the best PIO mode we can for a given device. We must
256 * pick a speed that does not cause problems with the other device
257 * on the cable.
258 */
259 if (pair) {
2134758d 260 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
0e9b4e53
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261 /* trim PIO to the slowest of the master/slave */
262 if (pair_pio < set_pio)
263 set_pio = pair_pio;
264 }
265
da9091ee 266 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
0e9b4e53 267 itdev->want[unit][1] = pio_want[set_pio];
da9091ee 268 itdev->want[unit][0] = 1; /* PIO is lowest priority */
88b2b32b 269 itdev->pio[unit] = pio_timings[set_pio];
da9091ee
AC
270 it821x_clock_strategy(drive);
271 it821x_program(drive, itdev->pio[unit]);
272}
273
274/**
275 * it821x_tune_mwdma - tune a channel for MWDMA
276 * @drive: drive to set up
277 * @mode_wanted: the target operating mode
278 *
279 * Load the timing settings for this device mode into the
280 * controller when doing MWDMA in pass through mode. The caller
281 * must manage the whole lack of per device MWDMA/PIO timings and
282 * the shared MWDMA/PIO timing register.
283 */
284
285static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
286{
36501650
BZ
287 ide_hwif_t *hwif = drive->hwif;
288 struct pci_dev *dev = to_pci_dev(hwif->dev);
da9091ee
AC
289 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
290 int unit = drive->select.b.unit;
291 int channel = hwif->channel;
292 u8 conf;
293
294 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
295 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
296
297 itdev->want[unit][1] = mwdma_want[mode_wanted];
298 itdev->want[unit][0] = 2; /* MWDMA is low priority */
299 itdev->mwdma[unit] = dma[mode_wanted];
300 itdev->udma[unit] = UDMA_OFF;
301
302 /* UDMA bits off - Revision 0x10 do them in pairs */
36501650
BZ
303 pci_read_config_byte(dev, 0x50, &conf);
304 if (itdev->timing10)
da9091ee
AC
305 conf |= channel ? 0x60: 0x18;
306 else
307 conf |= 1 << (3 + 2 * channel + unit);
36501650 308 pci_write_config_byte(dev, 0x50, conf);
da9091ee
AC
309
310 it821x_clock_strategy(drive);
311 /* FIXME: do we need to program this ? */
312 /* it821x_program(drive, itdev->mwdma[unit]); */
313}
314
315/**
316 * it821x_tune_udma - tune a channel for UDMA
317 * @drive: drive to set up
318 * @mode_wanted: the target operating mode
319 *
320 * Load the timing settings for this device mode into the
321 * controller when doing UDMA modes in pass through.
322 */
323
324static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
325{
36501650
BZ
326 ide_hwif_t *hwif = drive->hwif;
327 struct pci_dev *dev = to_pci_dev(hwif->dev);
da9091ee
AC
328 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
329 int unit = drive->select.b.unit;
330 int channel = hwif->channel;
331 u8 conf;
332
333 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
334 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
335
336 itdev->want[unit][1] = udma_want[mode_wanted];
337 itdev->want[unit][0] = 3; /* UDMA is high priority */
338 itdev->mwdma[unit] = MWDMA_OFF;
339 itdev->udma[unit] = udma[mode_wanted];
340 if(mode_wanted >= 5)
341 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
342
343 /* UDMA on. Again revision 0x10 must do the pair */
36501650
BZ
344 pci_read_config_byte(dev, 0x50, &conf);
345 if (itdev->timing10)
da9091ee
AC
346 conf &= channel ? 0x9F: 0xE7;
347 else
348 conf &= ~ (1 << (3 + 2 * channel + unit));
36501650 349 pci_write_config_byte(dev, 0x50, conf);
da9091ee
AC
350
351 it821x_clock_strategy(drive);
352 it821x_program_udma(drive, itdev->udma[unit]);
353
354}
355
da9091ee
AC
356/**
357 * it821x_dma_read - DMA hook
358 * @drive: drive for DMA
359 *
360 * The IT821x has a single timing register for MWDMA and for PIO
361 * operations. As we flip back and forth we have to reload the
362 * clock. In addition the rev 0x10 device only works if the same
363 * timing value is loaded into the master and slave UDMA clock
364 * so we must also reload that.
365 *
366 * FIXME: we could figure out in advance if we need to do reloads
367 */
368
369static void it821x_dma_start(ide_drive_t *drive)
370{
371 ide_hwif_t *hwif = drive->hwif;
372 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
373 int unit = drive->select.b.unit;
374 if(itdev->mwdma[unit] != MWDMA_OFF)
375 it821x_program(drive, itdev->mwdma[unit]);
376 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
377 it821x_program_udma(drive, itdev->udma[unit]);
378 ide_dma_start(drive);
379}
380
381/**
382 * it821x_dma_write - DMA hook
383 * @drive: drive for DMA stop
384 *
385 * The IT821x has a single timing register for MWDMA and for PIO
386 * operations. As we flip back and forth we have to reload the
387 * clock.
388 */
389
390static int it821x_dma_end(ide_drive_t *drive)
391{
392 ide_hwif_t *hwif = drive->hwif;
393 int unit = drive->select.b.unit;
394 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
395 int ret = __ide_dma_end(drive);
396 if(itdev->mwdma[unit] != MWDMA_OFF)
397 it821x_program(drive, itdev->pio[unit]);
398 return ret;
399}
400
da9091ee 401/**
88b2b32b
BZ
402 * it821x_set_dma_mode - set host controller for DMA mode
403 * @drive: drive
404 * @speed: DMA mode
da9091ee 405 *
88b2b32b 406 * Tune the ITE chipset for the desired DMA mode.
da9091ee
AC
407 */
408
88b2b32b 409static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
da9091ee 410{
88b2b32b
BZ
411 /*
412 * MWDMA tuning is really hard because our MWDMA and PIO
413 * timings are kept in the same place. We can switch in the
414 * host dma on/off callbacks.
415 */
416 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
417 it821x_tune_udma(drive, speed - XFER_UDMA_0);
418 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
419 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
da9091ee
AC
420}
421
da9091ee 422/**
ac95beed 423 * it821x_cable_detect - cable detection
da9091ee
AC
424 * @hwif: interface to check
425 *
426 * Check for the presence of an ATA66 capable cable on the
427 * interface. Problematic as it seems some cards don't have
428 * the needed logic onboard.
429 */
430
f454cbe8 431static u8 it821x_cable_detect(ide_hwif_t *hwif)
da9091ee
AC
432{
433 /* The reference driver also only does disk side */
49521f97 434 return ATA_CBL_PATA80;
da9091ee
AC
435}
436
437/**
f01393e4
BZ
438 * it821x_quirkproc - post init callback
439 * @drive: drive
da9091ee 440 *
f01393e4 441 * This callback is run after the drive has been probed but
da9091ee
AC
442 * before anything gets attached. It allows drivers to do any
443 * final tuning that is needed, or fixups to work around bugs.
444 */
445
36de9948 446static void it821x_quirkproc(ide_drive_t *drive)
da9091ee 447{
f01393e4
BZ
448 struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
449 struct hd_driveid *id = drive->id;
450 u16 *idbits = (u16 *)drive->id;
da9091ee 451
f01393e4 452 if (!itdev->smart) {
da9091ee
AC
453 /*
454 * If we are in pass through mode then not much
455 * needs to be done, but we do bother to clear the
456 * IRQ mask as we may well be in PIO (eg rev 0x10)
457 * for now and we know unmasking is safe on this chipset.
458 */
f01393e4
BZ
459 drive->unmask = 1;
460 } else {
da9091ee
AC
461 /*
462 * Perform fixups on smart mode. We need to "lose" some
463 * capabilities the firmware lacks but does not filter, and
464 * also patch up some capability bits that it forgets to set
465 * in RAID mode.
466 */
467
da9091ee
AC
468 /* Check for RAID v native */
469 if(strstr(id->model, "Integrated Technology Express")) {
470 /* In raid mode the ident block is slightly buggy
471 We need to set the bits so that the IDE layer knows
472 LBA28. LBA48 and DMA ar valid */
473 id->capability |= 3; /* LBA28, DMA */
474 id->command_set_2 |= 0x0400; /* LBA48 valid */
475 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
476 /* Reporting logic */
477 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
478 drive->name,
479 idbits[147] ? "Bootable ":"",
480 idbits[129]);
481 if(idbits[129] != 1)
482 printk("(%dK stripe)", idbits[146]);
483 printk(".\n");
da9091ee
AC
484 } else {
485 /* Non RAID volume. Fixups to stop the core code
486 doing unsupported things */
0380dad4 487 id->field_valid &= 3;
da9091ee
AC
488 id->queue_depth = 0;
489 id->command_set_1 = 0;
490 id->command_set_2 &= 0xC400;
491 id->cfsse &= 0xC000;
492 id->cfs_enable_1 = 0;
493 id->cfs_enable_2 &= 0xC400;
494 id->csf_default &= 0xC000;
495 id->word127 = 0;
496 id->dlf = 0;
497 id->csfo = 0;
498 id->cfa_power = 0;
499 printk(KERN_INFO "%s: Performing identify fixups.\n",
500 drive->name);
501 }
0380dad4
BZ
502
503 /*
504 * Set MWDMA0 mode as enabled/support - just to tell
505 * IDE core that DMA is supported (it821x hardware
506 * takes care of DMA mode programming).
507 */
508 if (id->capability & 1) {
509 id->dma_mword |= 0x0101;
510 drive->current_speed = XFER_MW_DMA_0;
511 }
da9091ee
AC
512 }
513
514}
515
5e37bdc0 516static struct ide_dma_ops it821x_pass_through_dma_ops = {
84e0f3f6
DG
517 .dma_host_set = ide_dma_host_set,
518 .dma_setup = ide_dma_setup,
519 .dma_exec_cmd = ide_dma_exec_cmd,
5e37bdc0
BZ
520 .dma_start = it821x_dma_start,
521 .dma_end = it821x_dma_end,
84e0f3f6
DG
522 .dma_test_irq = ide_dma_test_irq,
523 .dma_timeout = ide_dma_timeout,
524 .dma_lost_irq = ide_dma_lost_irq,
5e37bdc0
BZ
525};
526
da9091ee
AC
527/**
528 * init_hwif_it821x - set up hwif structs
529 * @hwif: interface to set up
530 *
531 * We do the basic set up of the interface structure. The IT8212
532 * requires several custom handlers so we override the default
533 * ide DMA handlers appropriately
534 */
535
536static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
537{
36501650 538 struct pci_dev *dev = to_pci_dev(hwif->dev);
1d76d9dc
BZ
539 struct ide_host *host = pci_get_drvdata(dev);
540 struct it821x_dev *itdevs = host->host_priv;
541 struct it821x_dev *idev = itdevs + hwif->channel;
da9091ee
AC
542 u8 conf;
543
da9091ee
AC
544 ide_set_hwifdata(hwif, idev);
545
36501650 546 pci_read_config_byte(dev, 0x50, &conf);
33c1002e 547 if (conf & 1) {
da9091ee 548 idev->smart = 1;
33c1002e 549 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
da9091ee
AC
550 /* Long I/O's although allowed in LBA48 space cause the
551 onboard firmware to enter the twighlight zone */
552 hwif->rqsize = 256;
553 }
554
555 /* Pull the current clocks from 0x50 also */
556 if (conf & (1 << (1 + hwif->channel)))
557 idev->clock_mode = ATA_50;
558 else
559 idev->clock_mode = ATA_66;
560
561 idev->want[0][1] = ATA_ANY;
562 idev->want[1][1] = ATA_ANY;
563
564 /*
565 * Not in the docs but according to the reference driver
3a4fa0a2 566 * this is necessary.
da9091ee
AC
567 */
568
36501650 569 pci_read_config_byte(dev, 0x08, &conf);
33c1002e 570 if (conf == 0x10) {
da9091ee 571 idev->timing10 = 1;
33c1002e
BZ
572 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
573 if (idev->smart == 0)
ced3ec8a 574 printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
28cfd8af 575 "workarounds activated\n", pci_name(dev));
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576 }
577
88b2b32b 578 if (idev->smart == 0) {
88b2b32b 579 /* MWDMA/PIO clock switching for pass through mode */
5e37bdc0 580 hwif->dma_ops = &it821x_pass_through_dma_ops;
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581 } else
582 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
da9091ee 583
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584 if (hwif->dma_base == 0)
585 return;
da9091ee 586
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587 hwif->ultra_mask = ATA_UDMA6;
588 hwif->mwdma_mask = ATA_MWDMA2;
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589}
590
591static void __devinit it8212_disable_raid(struct pci_dev *dev)
592{
593 /* Reset local CPU, and set BIOS not ready */
594 pci_write_config_byte(dev, 0x5E, 0x01);
595
596 /* Set to bypass mode, and reset PCI bus */
597 pci_write_config_byte(dev, 0x50, 0x00);
598 pci_write_config_word(dev, PCI_COMMAND,
599 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
600 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
601 pci_write_config_word(dev, 0x40, 0xA0F3);
602
603 pci_write_config_dword(dev,0x4C, 0x02040204);
604 pci_write_config_byte(dev, 0x42, 0x36);
0c866b51 605 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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606}
607
a326b02b 608static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev)
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609{
610 u8 conf;
611 static char *mode[2] = { "pass through", "smart" };
612
613 /* Force the card into bypass mode if so requested */
614 if (it8212_noraid) {
ced3ec8a 615 printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
28cfd8af 616 pci_name(dev));
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617 it8212_disable_raid(dev);
618 }
619 pci_read_config_byte(dev, 0x50, &conf);
ced3ec8a 620 printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
28cfd8af 621 pci_name(dev), mode[conf & 1]);
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622 return 0;
623}
624
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625static const struct ide_port_ops it821x_port_ops = {
626 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
627 .set_pio_mode = it821x_set_pio_mode,
628 .set_dma_mode = it821x_set_dma_mode,
629 .quirkproc = it821x_quirkproc,
630 .cable_detect = it821x_cable_detect,
631};
da9091ee 632
04ba6e73 633static const struct ide_port_info it821x_chipset __devinitdata = {
ced3ec8a 634 .name = DRV_NAME,
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635 .init_chipset = init_chipset_it821x,
636 .init_hwif = init_hwif_it821x,
637 .port_ops = &it821x_port_ops,
638 .pio_mask = ATA_PIO4,
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639};
640
641/**
642 * it821x_init_one - pci layer discovery entry
643 * @dev: PCI device
644 * @id: ident table entry
645 *
646 * Called by the PCI code when it finds an ITE821x controller.
647 * We then use the IDE PCI generic helper to do most of the work.
648 */
649
650static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
651{
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652 struct it821x_dev *itdevs;
653 int rc;
eb7a07e8 654
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655 itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
656 if (itdevs == NULL) {
ced3ec8a 657 printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
1d76d9dc 658 return -ENOMEM;
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659 }
660
04ba6e73 661 rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
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662 if (rc)
663 kfree(itdevs);
eb7a07e8 664
1d76d9dc 665 return rc;
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666}
667
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668static void __devexit it821x_remove(struct pci_dev *dev)
669{
670 struct ide_host *host = pci_get_drvdata(dev);
671 struct it821x_dev *itdevs = host->host_priv;
672
673 ide_pci_remove(dev);
674 kfree(itdevs);
675}
676
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677static const struct pci_device_id it821x_pci_tbl[] = {
678 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
679 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
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680 { 0, },
681};
682
683MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
684
685static struct pci_driver driver = {
686 .name = "ITE821x IDE",
687 .id_table = it821x_pci_tbl,
688 .probe = it821x_init_one,
a69999e2 689 .remove = __devexit_p(it821x_remove),
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690};
691
692static int __init it821x_ide_init(void)
693{
694 return ide_pci_register_driver(&driver);
695}
696
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697static void __exit it821x_ide_exit(void)
698{
699 pci_unregister_driver(&driver);
700}
701
da9091ee 702module_init(it821x_ide_init);
87d8b613 703module_exit(it821x_ide_exit);
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704
705module_param_named(noraid, it8212_noraid, int, S_IRUGO);
da195665 706MODULE_PARM_DESC(noraid, "Force card into bypass mode");
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707
708MODULE_AUTHOR("Alan Cox");
709MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
710MODULE_LICENSE("GPL");
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