[deliverable/linux.git] / drivers / ide / pci / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
 * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

static unsigned long superio_ide_status[2];
static unsigned long superio_ide_select[2];
static unsigned long superio_ide_dma_status[2];

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	if (port == superio_ide_status[0] ||
	    port == superio_ide_status[1] ||
	    port == superio_ide_select[0] ||
	    port == superio_ide_select[1] ||
	    port == superio_ide_dma_status[0] ||
	    port == superio_ide_dma_status[1]) {
		u8 tmp;
		int retries = SUPERIO_IDE_MAX_RETRIES;

		/* printk(" [ reading port 0x%x with retry ] ", port); */

		do {
			tmp = inb(port);
			if (tmp == 0)
				udelay(50);
		} while (tmp == 0 && retries-- > 0);

		return tmp;
	}

	return inb(port);
}

static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 base, dmabase;
	u8 port = hwif->channel, tmp;

	base = pci_resource_start(pdev, port * 2) & ~3;
	dmabase = pci_resource_start(pdev, 4) & ~3;

	superio_ide_status[port] = base + IDE_STATUS_OFFSET;
	superio_ide_select[port] = base + IDE_SELECT_OFFSET;
	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	outb(tmp | 0x66, superio_ide_dma_status[port]);

	/* We need to override inb to workaround a SuperIO errata */
	hwif->INB = superio_ide_inb;
}

static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_SLOT(dev->devfn) == 0xE)
		/* Built-in - assume it's under superio. */
		superio_ide_init_iops(hwif);
}
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to drive->present)
 * the IRQ associated with the port (HWIF(drive)),
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);
	new = drive->present ? (new & ~bit) : (new | bit);

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive (drive, drive->using_dma);
}

static int ns87415_ide_dma_end (ide_drive_t *drive)
{
	ide_hwif_t      *hwif = HWIF(drive);
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->INB(hwif->dma_status);
	/* get dma command mode */
	dma_cmd = hwif->INB(hwif->dma_command);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_command);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = hwif->INB(hwif->dma_command);
	outb(dma_cmd | 6, hwif->dma_command);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_ide_dma_setup(ide_drive_t *drive)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (!ide_dma_setup(drive))
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	hwif->selectproc = &ns87415_selectproc;

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond
		 *      to SELECT_DRIVE() properly during first probe_hwif().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
		udelay(10);
		outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
		do {
			udelay(50);
			stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
                	if (stat == 0xff)
                        	break;
        	} while ((stat & BUSY_STAT) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		hwif->irq = hwif->mate->irq;	/* share IRQ with mate */

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_status);
	hwif->dma_setup = &ns87415_ide_dma_setup;
	hwif->ide_dma_end = &ns87415_ide_dma_end;
}

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= "NS87415",
#ifdef CONFIG_SUPERIO
	.init_iops	= init_iops_ns87415,
#endif
	.init_hwif	= init_hwif_ns87415,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA |
			  IDE_HFLAG_BOOTABLE,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &ns87415_chipset);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(ns87415_ide_init);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
	3	* Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
	4	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <davem@redhat.com>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
	13	#include <linux/timer.h>
	14	#include <linux/mm.h>
	15	#include <linux/ioport.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/blkdev.h>
	18	#include <linux/hdreg.h>
	19	#include <linux/pci.h>
	20	#include <linux/delay.h>
	21	#include <linux/ide.h>
	22	#include <linux/init.h>
	23
	24	#include <asm/io.h>
	25
	26	#ifdef CONFIG_SUPERIO
	27	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	28	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	29	* which use the integrated NS87514 cell for CD-ROM support.
	30	* i.e we have to support for CD-ROM installs.
	31	* See drivers/parisc/superio.c for more gory details.
	32	*/
	33	#include <asm/superio.h>
	34
	35	static unsigned long superio_ide_status[2];
	36	static unsigned long superio_ide_select[2];
	37	static unsigned long superio_ide_dma_status[2];
	38
	39	#define SUPERIO_IDE_MAX_RETRIES 25
	40
	41	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	42	* registers, IDE status register and the IDE select register need to be
	43	* retried
	44	*/
	45	static u8 superio_ide_inb (unsigned long port)
	46	{
	47	if (port == superio_ide_status[0] \|\|
	48	port == superio_ide_status[1] \|\|
	49	port == superio_ide_select[0] \|\|
	50	port == superio_ide_select[1] \|\|
	51	port == superio_ide_dma_status[0] \|\|
	52	port == superio_ide_dma_status[1]) {
	53	u8 tmp;
	54	int retries = SUPERIO_IDE_MAX_RETRIES;
	55
	56	/* printk(" [ reading port 0x%x with retry ] ", port); */
	57
	58	do {
	59	tmp = inb(port);
	60	if (tmp == 0)
	61	udelay(50);
	62	} while (tmp == 0 && retries-- > 0);
	63
	64	return tmp;
	65	}
	66
	67	return inb(port);
	68	}
	69
	70	static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
	71	{
36501650	72	struct pci_dev *pdev = to_pci_dev(hwif->dev);
1da177e4	73	u32 base, dmabase;
36501650	74	u8 port = hwif->channel, tmp;
1da177e4 LT	75
	76	base = pci_resource_start(pdev, port * 2) & ~3;
	77	dmabase = pci_resource_start(pdev, 4) & ~3;
	78
	79	superio_ide_status[port] = base + IDE_STATUS_OFFSET;
	80	superio_ide_select[port] = base + IDE_SELECT_OFFSET;
	81	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
	82
	83	/* Clear error/interrupt, enable dma */
	84	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	85	outb(tmp \| 0x66, superio_ide_dma_status[port]);
	86
	87	/* We need to override inb to workaround a SuperIO errata */
	88	hwif->INB = superio_ide_inb;
	89	}
	90
	91	static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
	92	{
36501650 BZ	93	struct pci_dev *dev = to_pci_dev(hwif->dev);
	94
	95	if (PCI_SLOT(dev->devfn) == 0xE)
1da177e4 LT	96	/* Built-in - assume it's under superio. */
1da177e4 LT	97	superio_ide_init_iops(hwif);
1da177e4 LT	98	}
	99	#endif
	100
	101	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	102
	103	/*
	104	* This routine either enables/disables (according to drive->present)
	105	* the IRQ associated with the port (HWIF(drive)),
	106	* and selects either PIO or DMA handshaking for the next I/O operation.
	107	*/
	108	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	109	{
	110	ide_hwif_t *hwif = HWIF(drive);
36501650	111	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	112	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	113	unsigned long flags;
	114
	115	local_irq_save(flags);
	116	new = *old;
	117
	118	/* Adjust IRQ enable bit */
	119	bit = 1 << (8 + hwif->channel);
	120	new = drive->present ? (new & ~bit) : (new \| bit);
	121
	122	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	123	bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
	124	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	125	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	126
	127	if (new != *old) {
	128	unsigned char stat;
	129
	130	/*
	131	* Don't change DMA engine settings while Write Buffers
	132	* are busy.
	133	*/
	134	(void) pci_read_config_byte(dev, 0x43, &stat);
	135	while (stat & 0x03) {
	136	udelay(1);
	137	(void) pci_read_config_byte(dev, 0x43, &stat);
	138	}
	139
	140	*old = new;
	141	(void) pci_write_config_dword(dev, 0x40, new);
	142
	143	/*
	144	* And let things settle...
	145	*/
	146	udelay(10);
	147	}
	148
	149	local_irq_restore(flags);
	150	}
	151
	152	static void ns87415_selectproc (ide_drive_t *drive)
	153	{
	154	ns87415_prepare_drive (drive, drive->using_dma);
	155	}
	156
	157	static int ns87415_ide_dma_end (ide_drive_t *drive)
	158	{
	159	ide_hwif_t *hwif = HWIF(drive);
	160	u8 dma_stat = 0, dma_cmd = 0;
	161
	162	drive->waiting_for_dma = 0;
	163	dma_stat = hwif->INB(hwif->dma_status);
	164	/* get dma command mode */
	165	dma_cmd = hwif->INB(hwif->dma_command);
	166	/* stop DMA */
0ecdca26	167	outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 LT	168	/* from ERRATA: clear the INTR & ERROR bits */
1da177e4 LT	169	dma_cmd = hwif->INB(hwif->dma_command);
0ecdca26	170	outb(dma_cmd \| 6, hwif->dma_command);
1da177e4 LT	171	/* and free any DMA resources */
	172	ide_destroy_dmatable(drive);
	173	/* verify good DMA status */
	174	return (dma_stat & 7) != 4;
	175	}
	176
	177	static int ns87415_ide_dma_setup(ide_drive_t *drive)
	178	{
	179	/* select DMA xfer */
	180	ns87415_prepare_drive(drive, 1);
	181	if (!ide_dma_setup(drive))
	182	return 0;
	183	/* DMA failed: select PIO xfer */
	184	ns87415_prepare_drive(drive, 0);
	185	return 1;
	186	}
	187
c20530ed	188	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	189	{
36501650	190	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	191	unsigned int ctrl, using_inta;
	192	u8 progif;
	193	#ifdef __sparc_v9__
	194	int timeout;
	195	u8 stat;
	196	#endif
	197
1da177e4 LT	198	hwif->selectproc = &ns87415_selectproc;
	199
	200	/*
	201	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	202	* Also, leave IRQ masked during drive probing, to prevent infinite
	203	* interrupts from a potentially floating INTA..
	204	*
	205	* IRQs get unmasked in selectproc when drive is first used.
	206	*/
	207	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	208	(void) pci_read_config_byte(dev, 0x09, &progif);
	209	/* is irq in "native" mode? */
	210	using_inta = progif & (1 << (hwif->channel << 1));
	211	if (!using_inta)
	212	using_inta = ctrl & (1 << (4 + hwif->channel));
	213	if (hwif->mate) {
	214	hwif->select_data = hwif->mate->select_data;
	215	} else {
	216	hwif->select_data = (unsigned long)
	217	&ns87415_control[ns87415_count++];
	218	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	219	if (using_inta)
	220	ctrl &= ~(1 << 6); /* unmask INTA */
	221	((unsigned int )hwif->select_data) = ctrl;
	222	(void) pci_write_config_dword(dev, 0x40, ctrl);
	223
	224	/*
	225	* Set prefetch size to 512 bytes for both ports,
	226	* but don't turn on/off prefetching here.
	227	*/
	228	pci_write_config_byte(dev, 0x55, 0xee);
	229
	230	#ifdef __sparc_v9__
	231	/*
	232	* XXX: Reset the device, if we don't it will not respond
	233	* to SELECT_DRIVE() properly during first probe_hwif().
	234	*/
	235	timeout = 10000;
0ecdca26	236	outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
1da177e4	237	udelay(10);
0ecdca26	238	outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
1da177e4 LT	239	do {
	240	udelay(50);
	241	stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
	242	if (stat == 0xff)
	243	break;
	244	} while ((stat & BUSY_STAT) && --timeout);
	245	#endif
	246	}
	247
	248	if (!using_inta)
	249	hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
	250	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	251	hwif->irq = hwif->mate->irq; /* share IRQ with mate */
	252
	253	if (!hwif->dma_base)
	254	return;
	255
0ecdca26	256	outb(0x60, hwif->dma_status);
1da177e4	257	hwif->dma_setup = &ns87415_ide_dma_setup;
1da177e4	258	hwif->ide_dma_end = &ns87415_ide_dma_end;
1da177e4 LT	259	}
1da177e4 LT	260
85620436	261	static const struct ide_port_info ns87415_chipset __devinitdata = {
1da177e4 LT	262	.name = "NS87415",
	263	#ifdef CONFIG_SUPERIO
	264	.init_iops = init_iops_ns87415,
	265	#endif
	266	.init_hwif = init_hwif_ns87415,
33c1002e	267	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
7cab14a7 BZ	268	IDE_HFLAG_NO_ATAPI_DMA \|
7cab14a7 BZ	269	IDE_HFLAG_BOOTABLE,
1da177e4 LT	270	};
	271
	272	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	273	{
	274	return ide_setup_pci_device(dev, &ns87415_chipset);
	275	}
	276
9cbcc5e3 BZ	277	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	278	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	279	{ 0, },
	280	};
	281	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	282
	283	static struct pci_driver driver = {
	284	.name = "NS87415_IDE",
	285	.id_table = ns87415_pci_tbl,
	286	.probe = ns87415_init_one,
	287	};
	288
82ab1eec	289	static int __init ns87415_ide_init(void)
1da177e4 LT	290	{
	291	return ide_pci_register_driver(&driver);
	292	}
	293
	294	module_init(ns87415_ide_init);
	295
	296	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	297	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	298	MODULE_LICENSE("GPL");