[deliverable/linux.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_vendor1);
	value = inb(hwif->dma_vendor3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_vendor1);
	outb(value, hwif->dma_vendor3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;

	/*
	 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
	 * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 *
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(hwif->pci_dev) == 4) {
		u8 mode = speed & 0x07;

		switch (speed) {
			case XFER_UDMA_6:
			case XFER_UDMA_5:
			case XFER_UDMA_4:
			case XFER_UDMA_3:
			case XFER_UDMA_2:
			case XFER_UDMA_1:
			case XFER_UDMA_0:
				set_indexed_reg(hwif, 0x10 + adj,
						udma_timings[mode].reg10);
				set_indexed_reg(hwif, 0x11 + adj,
						udma_timings[mode].reg11);
				set_indexed_reg(hwif, 0x12 + adj,
						udma_timings[mode].reg12);
				break;

			case XFER_MW_DMA_2:
			case XFER_MW_DMA_1:
			case XFER_MW_DMA_0:
				set_indexed_reg(hwif, 0x0e + adj,
						mwdma_timings[mode].reg0e);
				set_indexed_reg(hwif, 0x0f + adj,
						mwdma_timings[mode].reg0f);
				break;
			case XFER_PIO_4:
			case XFER_PIO_3:
			case XFER_PIO_2:
			case XFER_PIO_1:
			case XFER_PIO_0:
				set_indexed_reg(hwif, 0x0c + adj,
						pio_timings[mode].reg0c);
				set_indexed_reg(hwif, 0x0d + adj,
						pio_timings[mode].reg0d);
				set_indexed_reg(hwif, 0x13 + adj,
						pio_timings[mode].reg13);
				break;
			default:
				printk(KERN_ERR "pdc202xx_new: "
				       "Unknown speed %d ignored\n", speed);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}
}

static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdcnew_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static int pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	struct timeval start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	do_gettimeofday(&start_time);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	do_gettimeofday(&end_time);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
		(end_time.tv_usec - start_time.tv_usec);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	unsigned int class_rev = 0;
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xff;

	if (class_rev >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &pdcnew_set_pio_mode;
	hwif->set_dma_mode = &pdcnew_set_mode;

	hwif->quirkproc = &pdcnew_quirkproc;
	hwif->resetproc = &pdcnew_reset;

	hwif->err_stops_fifo = 1;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = pdcnew_cable_detect(hwif);
}

static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *bridge = dev->bus->self;

	if (bridge != NULL &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
							PCI_FUNC(dev->devfn)));
		if (dev2 != NULL &&
		    dev2->vendor == dev->vendor &&
		    dev2->device == dev->device) {
			int ret;

			if (dev2->irq != dev->irq) {
				dev2->irq = dev->irq;

				printk(KERN_WARNING "%s: PCI config space "
				       "interrupt fixed.\n", d->name);
			}

			ret = ide_setup_pci_devices(dev, dev2, d);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *bridge = dev->bus->self;

	if (bridge != NULL &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	   (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	    bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {

		printk(KERN_INFO "%s: attached to I2O RAID controller, "
				 "skipping.\n", d->name);
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20268",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 1 */
		.name		= "PDC20269",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 2 */
		.name		= "PDC20270",
		.init_setup	= init_setup_pdc20270,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 3 */
		.name		= "PDC20271",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 4 */
		.name		= "PDC20275",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 5 */
		.name		= "PDC20276",
		.init_setup	= init_setup_pdc20276,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	},{	/* 6 */
		.name		= "PDC20277",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
		.host_flags	= IDE_HFLAG_POST_SET_MODE,
	}
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static const struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202new_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	12	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
	22	#include <linux/timer.h>
	23	#include <linux/mm.h>
	24	#include <linux/ioport.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/ide.h>
	31
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34
	35	#ifdef CONFIG_PPC_PMAC
	36	#include <asm/prom.h>
	37	#include <asm/pci-bridge.h>
	38	#endif
	39
47694bb8 SS	40	#undef DEBUG
	41
	42	#ifdef DEBUG
	43	#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
	44	#else
	45	#define DBG(fmt, args...)
	46	#endif
	47
3c6bee1d	48	static const char *pdc_quirk_drives[] = {
1da177e4 LT	49	"QUANTUM FIREBALLlct08 08",
	50	"QUANTUM FIREBALLP KA6.4",
	51	"QUANTUM FIREBALLP KA9.1",
	52	"QUANTUM FIREBALLP LM20.4",
	53	"QUANTUM FIREBALLP KX13.6",
	54	"QUANTUM FIREBALLP KX20.5",
	55	"QUANTUM FIREBALLP KX27.3",
	56	"QUANTUM FIREBALLP LM20.5",
	57	NULL
	58	};
	59
47694bb8	60	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	61	{
	62	u8 mode;
	63
47694bb8	64	switch(pdev->device) {
1da177e4 LT	65	case PCI_DEVICE_ID_PROMISE_20277:
	66	case PCI_DEVICE_ID_PROMISE_20276:
	67	case PCI_DEVICE_ID_PROMISE_20275:
	68	case PCI_DEVICE_ID_PROMISE_20271:
	69	case PCI_DEVICE_ID_PROMISE_20269:
	70	mode = 4;
	71	break;
	72	case PCI_DEVICE_ID_PROMISE_20270:
	73	case PCI_DEVICE_ID_PROMISE_20268:
	74	mode = 3;
	75	break;
	76	default:
	77	return 0;
	78	}
47694bb8	79
1da177e4 LT	80	return mode;
	81	}
	82
47694bb8 SS	83	/**
	84	* get_indexed_reg - Get indexed register
	85	* @hwif: for the port address
	86	* @index: index of the indexed register
	87	*/
	88	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	89	{
	90	u8 value;
	91
0ecdca26 BZ	92	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	93	value = inb(hwif->dma_vendor3);
47694bb8 SS	94
	95	DBG("index[%02X] value[%02X]\n", index, value);
	96	return value;
	97	}
	98
	99	/**
	100	* set_indexed_reg - Set indexed register
	101	* @hwif: for the port address
	102	* @index: index of the indexed register
	103	*/
	104	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	105	{
0ecdca26 BZ	106	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	107	outb(value, hwif->dma_vendor3);
47694bb8 SS	108	DBG("index[%02X] value[%02X]\n", index, value);
	109	}
	110
	111	/*
	112	* ATA Timing Tables based on 133 MHz PLL output clock.
	113	*
	114	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	115	* the timing registers automatically when "set features" command is
	116	* issued to the device. However, if the PLL output clock is 133 MHz,
	117	* the following tables must be used.
	118	*/
	119	static struct pio_timing {
	120	u8 reg0c, reg0d, reg13;
	121	} pio_timings [] = {
	122	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	123	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	124	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	125	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	126	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	127	};
	128
	129	static struct mwdma_timing {
	130	u8 reg0e, reg0f;
	131	} mwdma_timings [] = {
	132	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	133	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	134	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	135	};
	136
	137	static struct udma_timing {
	138	u8 reg10, reg11, reg12;
	139	} udma_timings [] = {
	140	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	141	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	142	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	143	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	144	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	145	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	146	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	147	};
	148
88b2b32b	149	static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	150	{
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
47694bb8	152	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
1da177e4	153
47694bb8	154	/*
88b2b32b BZ	155	* IDE core issues SETFEATURES_XFER to the drive first (thanks to
88b2b32b BZ	156	* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
47694bb8	157	* automatically set the timing registers based on 100 MHz PLL output.
88b2b32b	158	*
47694bb8 SS	159	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	160	* chips, we must override the default register settings...
	161	*/
	162	if (max_dma_rate(hwif->pci_dev) == 4) {
	163	u8 mode = speed & 0x07;
	164
	165	switch (speed) {
	166	case XFER_UDMA_6:
	167	case XFER_UDMA_5:
	168	case XFER_UDMA_4:
	169	case XFER_UDMA_3:
	170	case XFER_UDMA_2:
	171	case XFER_UDMA_1:
	172	case XFER_UDMA_0:
	173	set_indexed_reg(hwif, 0x10 + adj,
	174	udma_timings[mode].reg10);
	175	set_indexed_reg(hwif, 0x11 + adj,
	176	udma_timings[mode].reg11);
	177	set_indexed_reg(hwif, 0x12 + adj,
	178	udma_timings[mode].reg12);
	179	break;
	180
	181	case XFER_MW_DMA_2:
	182	case XFER_MW_DMA_1:
	183	case XFER_MW_DMA_0:
	184	set_indexed_reg(hwif, 0x0e + adj,
	185	mwdma_timings[mode].reg0e);
	186	set_indexed_reg(hwif, 0x0f + adj,
	187	mwdma_timings[mode].reg0f);
	188	break;
	189	case XFER_PIO_4:
	190	case XFER_PIO_3:
	191	case XFER_PIO_2:
	192	case XFER_PIO_1:
	193	case XFER_PIO_0:
	194	set_indexed_reg(hwif, 0x0c + adj,
	195	pio_timings[mode].reg0c);
	196	set_indexed_reg(hwif, 0x0d + adj,
	197	pio_timings[mode].reg0d);
	198	set_indexed_reg(hwif, 0x13 + adj,
	199	pio_timings[mode].reg13);
	200	break;
	201	default:
	202	printk(KERN_ERR "pdc202xx_new: "
	203	"Unknown speed %d ignored\n", speed);
	204	}
	205	} else if (speed == XFER_UDMA_2) {
	206	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	207	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	208
	209	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	210	}
1da177e4 LT	211	}
1da177e4 LT	212
26bcb879	213	static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	214	{
88b2b32b	215	pdcnew_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	216	}
1da177e4 LT	217
47694bb8	218	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	219	{
49521f97 BZ	220	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	221	return ATA_CBL_PATA40;
	222	else
	223	return ATA_CBL_PATA80;
1da177e4	224	}
47694bb8	225
47694bb8	226	static int pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	227	{
d24ec426 SS	228	const char *list, model = drive->id->model;
	229
	230	for (list = pdc_quirk_drives; *list != NULL; list++)
	231	if (strstr(model, *list) != NULL)
	232	return 2;
	233	return 0;
1da177e4 LT	234	}
1da177e4 LT	235
47694bb8	236	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	237	{
	238	/*
	239	* Deleted this because it is redundant from the caller.
	240	*/
47694bb8	241	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	242	HWIF(drive)->channel ? "Secondary" : "Primary");
	243	}
	244
47694bb8 SS	245	/**
	246	* read_counter - Read the byte count registers
	247	* @dma_base: for the port address
	248	*/
	249	static long __devinit read_counter(u32 dma_base)
	250	{
	251	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	252	u8 cnt0, cnt1, cnt2, cnt3;
	253	long count = 0, last;
	254	int retry = 3;
	255
	256	do {
	257	last = count;
	258
	259	/* Read the current count */
	260	outb(0x20, pri_dma_base + 0x01);
	261	cnt0 = inb(pri_dma_base + 0x03);
	262	outb(0x21, pri_dma_base + 0x01);
	263	cnt1 = inb(pri_dma_base + 0x03);
	264	outb(0x20, sec_dma_base + 0x01);
	265	cnt2 = inb(sec_dma_base + 0x03);
	266	outb(0x21, sec_dma_base + 0x01);
	267	cnt3 = inb(sec_dma_base + 0x03);
	268
	269	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	270
	271	/*
	272	* The 30-bit decrementing counter is read in 4 pieces.
	273	* Incorrect value may be read when the most significant bytes
	274	* are changing...
	275	*/
	276	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	277
	278	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	279	cnt0, cnt1, cnt2, cnt3);
	280
	281	return count;
	282	}
	283
	284	/**
	285	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	286	* @dma_base: for the port address
	287	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	288	*/
	289	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	290	{
8006bf56	291	struct timeval start_time, end_time;
47694bb8	292	long start_count, end_count;
8006bf56	293	long pll_input, usec_elapsed;
47694bb8 SS	294	u8 scr1;
	295
	296	start_count = read_counter(dma_base);
8006bf56	297	do_gettimeofday(&start_time);
47694bb8 SS	298
	299	/* Start the test mode */
	300	outb(0x01, dma_base + 0x01);
	301	scr1 = inb(dma_base + 0x03);
	302	DBG("scr1[%02X]\n", scr1);
	303	outb(scr1 \| 0x40, dma_base + 0x03);
	304
	305	/* Let the counter run for 10 ms. */
	306	mdelay(10);
	307
	308	end_count = read_counter(dma_base);
8006bf56	309	do_gettimeofday(&end_time);
47694bb8 SS	310
	311	/* Stop the test mode */
	312	outb(0x01, dma_base + 0x01);
	313	scr1 = inb(dma_base + 0x03);
	314	DBG("scr1[%02X]\n", scr1);
	315	outb(scr1 & ~0x40, dma_base + 0x03);
	316
	317	/*
	318	* Calculate the input clock in Hz
	319	* (the clock counter is 30 bit wide and counts down)
	320	*/
8006bf56 AL	321	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
8006bf56 AL	322	(end_time.tv_usec - start_time.tv_usec);
56fe23d5	323	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	324	(10000000 / usec_elapsed);
47694bb8 SS	325
	326	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	327
	328	return pll_input;
	329	}
	330
1da177e4 LT	331	#ifdef CONFIG_PPC_PMAC
	332	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	333	{
	334	struct device_node *np = pci_device_to_OF_node(pdev);
	335	unsigned int class_rev = 0;
1da177e4 LT	336	u8 conf;
1da177e4 LT	337
55b61fec	338	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	339	return;
	340
	341	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	342	class_rev &= 0xff;
	343
	344	if (class_rev >= 0x03) {
	345	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	346	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	347	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	348	}
1da177e4 LT	349	}
	350	#endif /* CONFIG_PPC_PMAC */
	351
	352	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	353	{
47694bb8 SS	354	unsigned long dma_base = pci_resource_start(dev, 4);
	355	unsigned long sec_dma_base = dma_base + 0x08;
	356	long pll_input, pll_output, ratio;
	357	int f, r;
	358	u8 pll_ctl0, pll_ctl1;
	359
01cc643a BZ	360	if (dma_base == 0)
	361	return -EFAULT;
	362
1da177e4 LT	363	#ifdef CONFIG_PPC_PMAC
	364	apple_kiwi_init(dev);
	365	#endif
	366
47694bb8 SS	367	/* Calculate the required PLL output frequency */
	368	switch(max_dma_rate(dev)) {
	369	case 4: /* it's 133 MHz for Ultra133 chips */
	370	pll_output = 133333333;
	371	break;
	372	case 3: /* and 100 MHz for Ultra100 chips */
	373	default:
	374	pll_output = 100000000;
	375	break;
	376	}
	377
	378	/*
	379	* Detect PLL input clock.
	380	* On some systems, where PCI bus is running at non-standard clock rate
	381	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	382	* PDC20268 and newer chips employ PLL circuit to help correct timing
	383	* registers setting.
	384	*/
	385	pll_input = detect_pll_input_clock(dma_base);
	386	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	387
	388	/* Sanity check */
	389	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	390	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	391	name, pll_input);
	392	goto out;
	393	}
	394
	395	#ifdef DEBUG
	396	DBG("pll_output is %ld Hz\n", pll_output);
	397
	398	/* Show the current clock value of PLL control register
	399	* (maybe already configured by the BIOS)
	400	*/
	401	outb(0x02, sec_dma_base + 0x01);
	402	pll_ctl0 = inb(sec_dma_base + 0x03);
	403	outb(0x03, sec_dma_base + 0x01);
	404	pll_ctl1 = inb(sec_dma_base + 0x03);
	405
	406	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	407	#endif
	408
	409	/*
	410	* Calculate the ratio of F, R and NO
	411	* POUT = (F + 2) / (( R + 2) * NO)
	412	*/
	413	ratio = pll_output / (pll_input / 1000);
	414	if (ratio < 8600L) { /* 8.6x */
	415	/* Using NO = 0x01, R = 0x0d */
	416	r = 0x0d;
	417	} else if (ratio < 12900L) { /* 12.9x */
	418	/* Using NO = 0x01, R = 0x08 */
	419	r = 0x08;
	420	} else if (ratio < 16100L) { /* 16.1x */
	421	/* Using NO = 0x01, R = 0x06 */
	422	r = 0x06;
	423	} else if (ratio < 64000L) { /* 64x */
	424	r = 0x00;
	425	} else {
	426	/* Invalid ratio */
	427	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	428	goto out;
	429	}
	430
431	f = (ratio * (r + 2)) / 1000 - 2;
432
433	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
434
435	if (unlikely(f < 0 \|\| f > 127)) {
436	/* Invalid F */
437	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
438	goto out;
439	}
440
441	pll_ctl0 = (u8) f;
442	pll_ctl1 = (u8) r;
443
444	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
445
446	outb(0x02, sec_dma_base + 0x01);
447	outb(pll_ctl0, sec_dma_base + 0x03);
448	outb(0x03, sec_dma_base + 0x01);
449	outb(pll_ctl1, sec_dma_base + 0x03);
450
451	/* Wait the PLL circuit to be stable */
452	mdelay(30);
453
454	#ifdef DEBUG
455	/*
456	* Show the current clock value of PLL control register
457	*/
458	outb(0x02, sec_dma_base + 0x01);
459	pll_ctl0 = inb(sec_dma_base + 0x03);
460	outb(0x03, sec_dma_base + 0x01);
461	pll_ctl1 = inb(sec_dma_base + 0x03);
462
463	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
464	#endif
465
466	out:
1da177e4 LT	467	return dev->irq;
	468	}
	469
	470	static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
	471	{
26bcb879	472	hwif->set_pio_mode = &pdcnew_set_pio_mode;
88b2b32b	473	hwif->set_dma_mode = &pdcnew_set_mode;
26bcb879	474
1da177e4	475	hwif->quirkproc = &pdcnew_quirkproc;
47694bb8	476	hwif->resetproc = &pdcnew_reset;
1da177e4	477
01cc643a BZ	478	hwif->err_stops_fifo = 1;
01cc643a BZ	479
1da177e4 LT	480	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4 LT	481
01cc643a BZ	482	if (hwif->dma_base == 0)
	483	return;
	484
18137207	485	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4 LT	486	hwif->mwdma_mask = 0x07;
1da177e4 LT	487
49521f97 BZ	488	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	489	hwif->cbl = pdcnew_cable_detect(hwif);
1da177e4 LT	490	}
	491
	492	static int __devinit init_setup_pdcnew(struct pci_dev dev, ide_pci_device_t d)
	493	{
	494	return ide_setup_pci_device(dev, d);
	495	}
	496
07047935	497	static int __devinit init_setup_pdc20270(struct pci_dev dev, ide_pci_device_t d)
1da177e4	498	{
07047935 SS	499	struct pci_dev *bridge = dev->bus->self;
	500
	501	if (bridge != NULL &&
	502	bridge->vendor == PCI_VENDOR_ID_DEC &&
	503	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	504	struct pci_dev *dev2;
1da177e4	505
1da177e4 LT	506	if (PCI_SLOT(dev->devfn) & 2)
1da177e4 LT	507	return -ENODEV;
35198234	508
07047935 SS	509	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
	510	PCI_FUNC(dev->devfn)));
	511	if (dev2 != NULL &&
	512	dev2->vendor == dev->vendor &&
	513	dev2->device == dev->device) {
	514	int ret;
	515
	516	if (dev2->irq != dev->irq) {
	517	dev2->irq = dev->irq;
	518
	519	printk(KERN_WARNING "%s: PCI config space "
	520	"interrupt fixed.\n", d->name);
1da177e4	521	}
07047935 SS	522
	523	ret = ide_setup_pci_devices(dev, dev2, d);
	524	if (ret < 0)
	525	pci_dev_put(dev2);
	526	return ret;
1da177e4 LT	527	}
	528	}
	529	return ide_setup_pci_device(dev, d);
	530	}
	531
07047935	532	static int __devinit init_setup_pdc20276(struct pci_dev dev, ide_pci_device_t d)
1da177e4	533	{
07047935 SS	534	struct pci_dev *bridge = dev->bus->self;
	535
	536	if (bridge != NULL &&
	537	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	538	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	539	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	540
	541	printk(KERN_INFO "%s: attached to I2O RAID controller, "
	542	"skipping.\n", d->name);
1da177e4 LT	543	return -ENODEV;
	544	}
	545	return ide_setup_pci_device(dev, d);
	546	}
	547
	548	static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	549	{ /* 0 */
	550	.name = "PDC20268",
	551	.init_setup = init_setup_pdcnew,
	552	.init_chipset = init_chipset_pdcnew,
	553	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	554	.autodma = AUTODMA,
1da177e4 LT	555	.bootable = OFF_BOARD,
4099d143	556	.pio_mask = ATA_PIO4,
18137207	557	.udma_mask = 0x3f, /* udma0-5 */
88b2b32b	558	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	559	},{ /* 1 */
	560	.name = "PDC20269",
	561	.init_setup = init_setup_pdcnew,
	562	.init_chipset = init_chipset_pdcnew,
	563	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	564	.autodma = AUTODMA,
1da177e4 LT	565	.bootable = OFF_BOARD,
4099d143	566	.pio_mask = ATA_PIO4,
18137207	567	.udma_mask = 0x7f, /* udma0-6*/
88b2b32b	568	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	569	},{ /* 2 */
	570	.name = "PDC20270",
	571	.init_setup = init_setup_pdc20270,
	572	.init_chipset = init_chipset_pdcnew,
	573	.init_hwif = init_hwif_pdc202new,
1da177e4	574	.autodma = AUTODMA,
1da177e4	575	.bootable = OFF_BOARD,
4099d143	576	.pio_mask = ATA_PIO4,
18137207	577	.udma_mask = 0x3f, /* udma0-5 */
88b2b32b	578	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	579	},{ /* 3 */
	580	.name = "PDC20271",
	581	.init_setup = init_setup_pdcnew,
	582	.init_chipset = init_chipset_pdcnew,
	583	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	584	.autodma = AUTODMA,
1da177e4 LT	585	.bootable = OFF_BOARD,
4099d143	586	.pio_mask = ATA_PIO4,
18137207	587	.udma_mask = 0x7f, /* udma0-6*/
88b2b32b	588	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	589	},{ /* 4 */
	590	.name = "PDC20275",
	591	.init_setup = init_setup_pdcnew,
	592	.init_chipset = init_chipset_pdcnew,
	593	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	594	.autodma = AUTODMA,
1da177e4 LT	595	.bootable = OFF_BOARD,
4099d143	596	.pio_mask = ATA_PIO4,
18137207	597	.udma_mask = 0x7f, /* udma0-6*/
88b2b32b	598	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	599	},{ /* 5 */
	600	.name = "PDC20276",
	601	.init_setup = init_setup_pdc20276,
	602	.init_chipset = init_chipset_pdcnew,
	603	.init_hwif = init_hwif_pdc202new,
1da177e4	604	.autodma = AUTODMA,
1da177e4	605	.bootable = OFF_BOARD,
4099d143	606	.pio_mask = ATA_PIO4,
18137207	607	.udma_mask = 0x7f, /* udma0-6*/
88b2b32b	608	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	609	},{ /* 6 */
	610	.name = "PDC20277",
	611	.init_setup = init_setup_pdcnew,
	612	.init_chipset = init_chipset_pdcnew,
	613	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	614	.autodma = AUTODMA,
1da177e4 LT	615	.bootable = OFF_BOARD,
4099d143	616	.pio_mask = ATA_PIO4,
18137207	617	.udma_mask = 0x7f, /* udma0-6*/
88b2b32b	618	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	619	}
	620	};
	621
	622	/**
	623	* pdc202new_init_one - called when a pdc202xx is found
	624	* @dev: the pdc202new device
	625	* @id: the matching pci id
	626	*
	627	* Called when the PCI registration layer (or the IDE initialization)
	628	* finds a device matching our IDE device tables.
	629	*/
	630
	631	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	632	{
	633	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
	634
	635	return d->init_setup(dev, d);
	636	}
	637
9cbcc5e3 BZ	638	static const struct pci_device_id pdc202new_pci_tbl[] = {
	639	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	640	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	641	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	642	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	643	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	644	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	645	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
1da177e4 LT	646	{ 0, },
	647	};
	648	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	649
	650	static struct pci_driver driver = {
	651	.name = "Promise_IDE",
	652	.id_table = pdc202new_pci_tbl,
	653	.probe = pdc202new_init_one,
	654	};
	655
82ab1eec	656	static int __init pdc202new_ide_init(void)
1da177e4 LT	657	{
	658	return ide_pci_register_driver(&driver);
	659	}
	660
	661	module_init(pdc202new_ide_init);
	662
	663	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	664	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	665	MODULE_LICENSE("GPL");