[deliverable/linux.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_vendor1);
	value = inb(hwif->dma_vendor3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_vendor1);
	outb(value, hwif->dma_vendor3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;

	/*
	 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
	 * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 *
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(dev) == 4) {
		u8 mode = speed & 0x07;

		if (speed >= XFER_UDMA_0) {
			set_indexed_reg(hwif, 0x10 + adj,
					udma_timings[mode].reg10);
			set_indexed_reg(hwif, 0x11 + adj,
					udma_timings[mode].reg11);
			set_indexed_reg(hwif, 0x12 + adj,
					udma_timings[mode].reg12);
		} else {
			set_indexed_reg(hwif, 0x0e + adj,
					mwdma_timings[mode].reg0e);
			set_indexed_reg(hwif, 0x0f + adj,
					mwdma_timings[mode].reg0f);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}
}

static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;

	if (max_dma_rate(dev) == 4) {
		set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
		set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
		set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	}
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static void pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	struct timeval start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	do_gettimeofday(&start_time);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	do_gettimeofday(&end_time);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
		(end_time.tv_usec - start_time.tv_usec);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	if (pdev->revision >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &pdcnew_set_pio_mode;
	hwif->set_dma_mode = &pdcnew_set_dma_mode;

	hwif->quirkproc = &pdcnew_quirkproc;
	hwif->resetproc = &pdcnew_reset;

	if (hwif->dma_base == 0)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = pdcnew_cable_detect(hwif);
}

static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
{
	struct pci_dev *dev2;

	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
						PCI_FUNC(dev->devfn)));

	if (dev2 &&
	    dev2->vendor == dev->vendor &&
	    dev2->device == dev->device) {

		if (dev2->irq != dev->irq) {
			dev2->irq = dev->irq;
			printk(KERN_INFO "PDC20270: PCI config space "
					 "interrupt fixed\n");
		}

		return dev2;
	}

	return NULL;
}

#define DECLARE_PDCNEW_DEV(name_str, udma) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_pdcnew, \
		.init_hwif	= init_hwif_pdc202new, \
		.host_flags	= IDE_HFLAG_POST_SET_MODE | \
				  IDE_HFLAG_ERROR_STOPS_FIFO | \
				  IDE_HFLAG_OFF_BOARD, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	struct pci_dev *bridge = dev->bus->self;
	u8 idx = id->driver_data;

	d = &pdcnew_chipsets[idx];

	if (idx == 2 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pdc20270_get_dev2(dev);

		if (dev2) {
			int ret = ide_setup_pci_devices(dev, dev2, d);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}

	if (idx == 5 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
		printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
				 "skipping\n");
		return -ENODEV;
	}

	return ide_setup_pci_device(dev, d);
}

static const struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202new_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	12	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
	22	#include <linux/timer.h>
	23	#include <linux/mm.h>
	24	#include <linux/ioport.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/ide.h>
	31
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34
	35	#ifdef CONFIG_PPC_PMAC
	36	#include <asm/prom.h>
	37	#include <asm/pci-bridge.h>
	38	#endif
	39
47694bb8 SS	40	#undef DEBUG
	41
	42	#ifdef DEBUG
	43	#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
	44	#else
	45	#define DBG(fmt, args...)
	46	#endif
	47
3c6bee1d	48	static const char *pdc_quirk_drives[] = {
1da177e4 LT	49	"QUANTUM FIREBALLlct08 08",
	50	"QUANTUM FIREBALLP KA6.4",
	51	"QUANTUM FIREBALLP KA9.1",
	52	"QUANTUM FIREBALLP LM20.4",
	53	"QUANTUM FIREBALLP KX13.6",
	54	"QUANTUM FIREBALLP KX20.5",
	55	"QUANTUM FIREBALLP KX27.3",
	56	"QUANTUM FIREBALLP LM20.5",
	57	NULL
	58	};
	59
47694bb8	60	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	61	{
	62	u8 mode;
	63
47694bb8	64	switch(pdev->device) {
1da177e4 LT	65	case PCI_DEVICE_ID_PROMISE_20277:
	66	case PCI_DEVICE_ID_PROMISE_20276:
	67	case PCI_DEVICE_ID_PROMISE_20275:
	68	case PCI_DEVICE_ID_PROMISE_20271:
	69	case PCI_DEVICE_ID_PROMISE_20269:
	70	mode = 4;
	71	break;
	72	case PCI_DEVICE_ID_PROMISE_20270:
	73	case PCI_DEVICE_ID_PROMISE_20268:
	74	mode = 3;
	75	break;
	76	default:
	77	return 0;
	78	}
47694bb8	79
1da177e4 LT	80	return mode;
	81	}
	82
47694bb8 SS	83	/**
	84	* get_indexed_reg - Get indexed register
	85	* @hwif: for the port address
	86	* @index: index of the indexed register
	87	*/
	88	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	89	{
	90	u8 value;
	91
0ecdca26 BZ	92	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	93	value = inb(hwif->dma_vendor3);
47694bb8 SS	94
	95	DBG("index[%02X] value[%02X]\n", index, value);
	96	return value;
	97	}
	98
	99	/**
	100	* set_indexed_reg - Set indexed register
	101	* @hwif: for the port address
	102	* @index: index of the indexed register
	103	*/
	104	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	105	{
0ecdca26 BZ	106	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	107	outb(value, hwif->dma_vendor3);
47694bb8 SS	108	DBG("index[%02X] value[%02X]\n", index, value);
	109	}
	110
	111	/*
	112	* ATA Timing Tables based on 133 MHz PLL output clock.
	113	*
	114	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	115	* the timing registers automatically when "set features" command is
	116	* issued to the device. However, if the PLL output clock is 133 MHz,
	117	* the following tables must be used.
	118	*/
	119	static struct pio_timing {
	120	u8 reg0c, reg0d, reg13;
	121	} pio_timings [] = {
	122	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	123	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	124	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	125	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	126	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	127	};
	128
	129	static struct mwdma_timing {
	130	u8 reg0e, reg0f;
	131	} mwdma_timings [] = {
	132	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	133	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	134	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	135	};
	136
	137	static struct udma_timing {
	138	u8 reg10, reg11, reg12;
	139	} udma_timings [] = {
	140	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	141	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	142	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	143	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	144	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	145	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	146	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	147	};
	148
ad4ba7dc	149	static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	150	{
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
36501650	152	struct pci_dev *dev = to_pci_dev(hwif->dev);
47694bb8	153	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
1da177e4	154
47694bb8	155	/*
88b2b32b BZ	156	* IDE core issues SETFEATURES_XFER to the drive first (thanks to
88b2b32b BZ	157	* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
47694bb8	158	* automatically set the timing registers based on 100 MHz PLL output.
88b2b32b	159	*
47694bb8 SS	160	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	161	* chips, we must override the default register settings...
	162	*/
36501650	163	if (max_dma_rate(dev) == 4) {
47694bb8 SS	164	u8 mode = speed & 0x07;
47694bb8 SS	165
4db90a14 BZ	166	if (speed >= XFER_UDMA_0) {
	167	set_indexed_reg(hwif, 0x10 + adj,
	168	udma_timings[mode].reg10);
	169	set_indexed_reg(hwif, 0x11 + adj,
	170	udma_timings[mode].reg11);
	171	set_indexed_reg(hwif, 0x12 + adj,
	172	udma_timings[mode].reg12);
	173	} else {
	174	set_indexed_reg(hwif, 0x0e + adj,
	175	mwdma_timings[mode].reg0e);
	176	set_indexed_reg(hwif, 0x0f + adj,
	177	mwdma_timings[mode].reg0f);
47694bb8 SS	178	}
	179	} else if (speed == XFER_UDMA_2) {
	180	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	181	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	182
	183	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	184	}
1da177e4 LT	185	}
1da177e4 LT	186
26bcb879	187	static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	188	{
ad4ba7dc	189	ide_hwif_t *hwif = drive->hwif;
36501650	190	struct pci_dev *dev = to_pci_dev(hwif->dev);
ad4ba7dc BZ	191	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
ad4ba7dc BZ	192
36501650	193	if (max_dma_rate(dev) == 4) {
ad4ba7dc BZ	194	set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
	195	set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
	196	set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	197	}
1da177e4 LT	198	}
1da177e4 LT	199
47694bb8	200	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	201	{
49521f97 BZ	202	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	203	return ATA_CBL_PATA40;
	204	else
	205	return ATA_CBL_PATA80;
1da177e4	206	}
47694bb8	207
f01393e4	208	static void pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	209	{
d24ec426 SS	210	const char *list, model = drive->id->model;
	211
	212	for (list = pdc_quirk_drives; *list != NULL; list++)
f01393e4 BZ	213	if (strstr(model, *list) != NULL) {
	214	drive->quirk_list = 2;
	215	return;
	216	}
	217
	218	drive->quirk_list = 0;
1da177e4 LT	219	}
1da177e4 LT	220
47694bb8	221	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	222	{
	223	/*
	224	* Deleted this because it is redundant from the caller.
	225	*/
47694bb8	226	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	227	HWIF(drive)->channel ? "Secondary" : "Primary");
	228	}
	229
47694bb8 SS	230	/**
	231	* read_counter - Read the byte count registers
	232	* @dma_base: for the port address
	233	*/
	234	static long __devinit read_counter(u32 dma_base)
	235	{
	236	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	237	u8 cnt0, cnt1, cnt2, cnt3;
	238	long count = 0, last;
	239	int retry = 3;
	240
	241	do {
	242	last = count;
	243
	244	/* Read the current count */
	245	outb(0x20, pri_dma_base + 0x01);
	246	cnt0 = inb(pri_dma_base + 0x03);
	247	outb(0x21, pri_dma_base + 0x01);
	248	cnt1 = inb(pri_dma_base + 0x03);
	249	outb(0x20, sec_dma_base + 0x01);
	250	cnt2 = inb(sec_dma_base + 0x03);
	251	outb(0x21, sec_dma_base + 0x01);
	252	cnt3 = inb(sec_dma_base + 0x03);
	253
	254	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	255
	256	/*
	257	* The 30-bit decrementing counter is read in 4 pieces.
	258	* Incorrect value may be read when the most significant bytes
	259	* are changing...
	260	*/
	261	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	262
	263	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	264	cnt0, cnt1, cnt2, cnt3);
	265
	266	return count;
	267	}
	268
	269	/**
	270	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	271	* @dma_base: for the port address
	272	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	273	*/
	274	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	275	{
8006bf56	276	struct timeval start_time, end_time;
47694bb8	277	long start_count, end_count;
8006bf56	278	long pll_input, usec_elapsed;
47694bb8 SS	279	u8 scr1;
	280
	281	start_count = read_counter(dma_base);
8006bf56	282	do_gettimeofday(&start_time);
47694bb8 SS	283
	284	/* Start the test mode */
	285	outb(0x01, dma_base + 0x01);
	286	scr1 = inb(dma_base + 0x03);
	287	DBG("scr1[%02X]\n", scr1);
	288	outb(scr1 \| 0x40, dma_base + 0x03);
	289
	290	/* Let the counter run for 10 ms. */
	291	mdelay(10);
	292
	293	end_count = read_counter(dma_base);
8006bf56	294	do_gettimeofday(&end_time);
47694bb8 SS	295
	296	/* Stop the test mode */
	297	outb(0x01, dma_base + 0x01);
	298	scr1 = inb(dma_base + 0x03);
	299	DBG("scr1[%02X]\n", scr1);
	300	outb(scr1 & ~0x40, dma_base + 0x03);
	301
	302	/*
	303	* Calculate the input clock in Hz
	304	* (the clock counter is 30 bit wide and counts down)
	305	*/
8006bf56 AL	306	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
8006bf56 AL	307	(end_time.tv_usec - start_time.tv_usec);
56fe23d5	308	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	309	(10000000 / usec_elapsed);
47694bb8 SS	310
	311	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	312
	313	return pll_input;
	314	}
	315
1da177e4 LT	316	#ifdef CONFIG_PPC_PMAC
	317	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	318	{
	319	struct device_node *np = pci_device_to_OF_node(pdev);
1da177e4 LT	320	u8 conf;
1da177e4 LT	321
55b61fec	322	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	323	return;
1da177e4 LT	324
fc212bb1	325	if (pdev->revision >= 0x03) {
1da177e4	326	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	327	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	328	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	329	}
1da177e4 LT	330	}
	331	#endif /* CONFIG_PPC_PMAC */
	332
	333	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	334	{
47694bb8 SS	335	unsigned long dma_base = pci_resource_start(dev, 4);
	336	unsigned long sec_dma_base = dma_base + 0x08;
	337	long pll_input, pll_output, ratio;
	338	int f, r;
	339	u8 pll_ctl0, pll_ctl1;
	340
01cc643a BZ	341	if (dma_base == 0)
	342	return -EFAULT;
	343
1da177e4 LT	344	#ifdef CONFIG_PPC_PMAC
	345	apple_kiwi_init(dev);
	346	#endif
	347
47694bb8 SS	348	/* Calculate the required PLL output frequency */
	349	switch(max_dma_rate(dev)) {
	350	case 4: /* it's 133 MHz for Ultra133 chips */
	351	pll_output = 133333333;
	352	break;
	353	case 3: /* and 100 MHz for Ultra100 chips */
	354	default:
	355	pll_output = 100000000;
	356	break;
	357	}
	358
	359	/*
	360	* Detect PLL input clock.
	361	* On some systems, where PCI bus is running at non-standard clock rate
	362	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	363	* PDC20268 and newer chips employ PLL circuit to help correct timing
	364	* registers setting.
	365	*/
	366	pll_input = detect_pll_input_clock(dma_base);
	367	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	368
	369	/* Sanity check */
	370	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	371	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	372	name, pll_input);
	373	goto out;
	374	}
	375
	376	#ifdef DEBUG
	377	DBG("pll_output is %ld Hz\n", pll_output);
	378
	379	/* Show the current clock value of PLL control register
	380	* (maybe already configured by the BIOS)
	381	*/
	382	outb(0x02, sec_dma_base + 0x01);
	383	pll_ctl0 = inb(sec_dma_base + 0x03);
	384	outb(0x03, sec_dma_base + 0x01);
	385	pll_ctl1 = inb(sec_dma_base + 0x03);
	386
	387	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	388	#endif
	389
	390	/*
	391	* Calculate the ratio of F, R and NO
	392	* POUT = (F + 2) / (( R + 2) * NO)
	393	*/
	394	ratio = pll_output / (pll_input / 1000);
	395	if (ratio < 8600L) { /* 8.6x */
	396	/* Using NO = 0x01, R = 0x0d */
	397	r = 0x0d;
	398	} else if (ratio < 12900L) { /* 12.9x */
	399	/* Using NO = 0x01, R = 0x08 */
	400	r = 0x08;
	401	} else if (ratio < 16100L) { /* 16.1x */
	402	/* Using NO = 0x01, R = 0x06 */
	403	r = 0x06;
	404	} else if (ratio < 64000L) { /* 64x */
	405	r = 0x00;
	406	} else {
	407	/* Invalid ratio */
	408	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	409	goto out;
	410	}
	411
412	f = (ratio * (r + 2)) / 1000 - 2;
413
414	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
415
416	if (unlikely(f < 0 \|\| f > 127)) {
417	/* Invalid F */
418	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
419	goto out;
420	}
421
422	pll_ctl0 = (u8) f;
423	pll_ctl1 = (u8) r;
424
425	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
426
427	outb(0x02, sec_dma_base + 0x01);
428	outb(pll_ctl0, sec_dma_base + 0x03);
429	outb(0x03, sec_dma_base + 0x01);
430	outb(pll_ctl1, sec_dma_base + 0x03);
431
432	/* Wait the PLL circuit to be stable */
433	mdelay(30);
434
435	#ifdef DEBUG
436	/*
437	* Show the current clock value of PLL control register
438	*/
439	outb(0x02, sec_dma_base + 0x01);
440	pll_ctl0 = inb(sec_dma_base + 0x03);
441	outb(0x03, sec_dma_base + 0x01);
442	pll_ctl1 = inb(sec_dma_base + 0x03);
443
444	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
445	#endif
446
447	out:
1da177e4 LT	448	return dev->irq;
	449	}
	450
	451	static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
	452	{
26bcb879	453	hwif->set_pio_mode = &pdcnew_set_pio_mode;
ad4ba7dc	454	hwif->set_dma_mode = &pdcnew_set_dma_mode;
26bcb879	455
1da177e4	456	hwif->quirkproc = &pdcnew_quirkproc;
47694bb8	457	hwif->resetproc = &pdcnew_reset;
1da177e4	458
01cc643a BZ	459	if (hwif->dma_base == 0)
	460	return;
	461
49521f97 BZ	462	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	463	hwif->cbl = pdcnew_cable_detect(hwif);
1da177e4 LT	464	}
1da177e4 LT	465
099b1f42	466	static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
1da177e4	467	{
099b1f42 BZ	468	struct pci_dev *dev2;
099b1f42 BZ	469
eadb6ecf	470	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
099b1f42	471	PCI_FUNC(dev->devfn)));
eadb6ecf	472
099b1f42 BZ	473	if (dev2 &&
	474	dev2->vendor == dev->vendor &&
	475	dev2->device == dev->device) {
	476
	477	if (dev2->irq != dev->irq) {
	478	dev2->irq = dev->irq;
	479	printk(KERN_INFO "PDC20270: PCI config space "
	480	"interrupt fixed\n");
1da177e4	481	}
07047935	482
099b1f42	483	return dev2;
1da177e4	484	}
099b1f42 BZ	485
099b1f42 BZ	486	return NULL;
1da177e4 LT	487	}
1da177e4 LT	488
05d7e6cb BZ	489	#define DECLARE_PDCNEW_DEV(name_str, udma) \
	490	{ \
	491	.name = name_str, \
	492	.init_chipset = init_chipset_pdcnew, \
	493	.init_hwif = init_hwif_pdc202new, \
	494	.host_flags = IDE_HFLAG_POST_SET_MODE \| \
ed67b923	495	IDE_HFLAG_ERROR_STOPS_FIFO \| \
05d7e6cb BZ	496	IDE_HFLAG_OFF_BOARD, \
	497	.pio_mask = ATA_PIO4, \
	498	.mwdma_mask = ATA_MWDMA2, \
	499	.udma_mask = udma, \
1da177e4	500	}
05d7e6cb	501
85620436	502	static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
05d7e6cb BZ	503	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	504	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	505	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	506	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	507	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	508	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	509	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
1da177e4 LT	510	};
	511
	512	/**
	513	* pdc202new_init_one - called when a pdc202xx is found
	514	* @dev: the pdc202new device
	515	* @id: the matching pci id
	516	*
	517	* Called when the PCI registration layer (or the IDE initialization)
	518	* finds a device matching our IDE device tables.
	519	*/
	520
	521	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	522	{
85620436	523	const struct ide_port_info *d;
099b1f42 BZ	524	struct pci_dev *bridge = dev->bus->self;
	525	u8 idx = id->driver_data;
	526
	527	d = &pdcnew_chipsets[idx];
	528
	529	if (idx == 2 && bridge &&
	530	bridge->vendor == PCI_VENDOR_ID_DEC &&
	531	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	532	struct pci_dev *dev2;
	533
	534	if (PCI_SLOT(dev->devfn) & 2)
	535	return -ENODEV;
1da177e4	536
099b1f42 BZ	537	dev2 = pdc20270_get_dev2(dev);
	538
	539	if (dev2) {
	540	int ret = ide_setup_pci_devices(dev, dev2, d);
	541	if (ret < 0)
	542	pci_dev_put(dev2);
	543	return ret;
	544	}
	545	}
	546
	547	if (idx == 5 && bridge &&
	548	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	549	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	550	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	551	printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
	552	"skipping\n");
	553	return -ENODEV;
	554	}
	555
	556	return ide_setup_pci_device(dev, d);
1da177e4 LT	557	}
1da177e4 LT	558
9cbcc5e3 BZ	559	static const struct pci_device_id pdc202new_pci_tbl[] = {
	560	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	561	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	562	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	563	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	564	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	565	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	566	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
1da177e4 LT	567	{ 0, },
	568	};
	569	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	570
	571	static struct pci_driver driver = {
	572	.name = "Promise_IDE",
	573	.id_table = pdc202new_pci_tbl,
	574	.probe = pdc202new_init_one,
	575	};
	576
82ab1eec	577	static int __init pdc202new_ide_init(void)
1da177e4 LT	578	{
	579	return ide_pci_register_driver(&driver);
	580	}
	581
	582	module_init(pdc202new_ide_init);
	583
	584	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	585	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	586	MODULE_LICENSE("GPL");