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pdc202xx_new: remove check_in_drive_lists abomination
[deliverable/linux.git] / drivers / ide / pci / pdc202xx_new.c
CommitLineData
1da177e4
LT		 1/*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
b10a0686 12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
1da177e4
LT		 13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/mm.h>
24#include <linux/ioport.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/ide.h>
31
32#include <asm/io.h>
33#include <asm/irq.h>
34
35#ifdef CONFIG_PPC_PMAC
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif
39
40#define PDC202_DEBUG_CABLE 0
41
47694bb8
SS		 42#undef DEBUG
43
44#ifdef DEBUG
45#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
46#else
47#define DBG(fmt, args...)
48#endif
49
3c6bee1d 50static const char *pdc_quirk_drives[] = {
1da177e4
LT		 51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
59 NULL
60};
61
47694bb8 62static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4
LT		 63{
64 u8 mode;
65
47694bb8 66 switch(pdev->device) {
1da177e4
LT		 67 case PCI_DEVICE_ID_PROMISE_20277:
68 case PCI_DEVICE_ID_PROMISE_20276:
69 case PCI_DEVICE_ID_PROMISE_20275:
70 case PCI_DEVICE_ID_PROMISE_20271:
71 case PCI_DEVICE_ID_PROMISE_20269:
72 mode = 4;
73 break;
74 case PCI_DEVICE_ID_PROMISE_20270:
75 case PCI_DEVICE_ID_PROMISE_20268:
76 mode = 3;
77 break;
78 default:
79 return 0;
80 }
47694bb8 81
1da177e4
LT		 82 return mode;
83}
84
47694bb8
SS		 85static u8 pdcnew_ratemask(ide_drive_t *drive)
86{
87 u8 mode = max_dma_rate(HWIF(drive)->pci_dev);
88
89 if (!eighty_ninty_three(drive))
90 mode = min_t(u8, mode, 1);
91
92 return mode;
93}
94
47694bb8
SS		 95/**
96 * get_indexed_reg - Get indexed register
97 * @hwif: for the port address
98 * @index: index of the indexed register
99 */
100static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
101{
102 u8 value;
103
104 hwif->OUTB(index, hwif->dma_vendor1);
105 value = hwif->INB(hwif->dma_vendor3);
106
107 DBG("index[%02X] value[%02X]\n", index, value);
108 return value;
109}
110
111/**
112 * set_indexed_reg - Set indexed register
113 * @hwif: for the port address
114 * @index: index of the indexed register
115 */
116static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
117{
118 hwif->OUTB(index, hwif->dma_vendor1);
119 hwif->OUTB(value, hwif->dma_vendor3);
120 DBG("index[%02X] value[%02X]\n", index, value);
121}
122
123/*
124 * ATA Timing Tables based on 133 MHz PLL output clock.
125 *
126 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
127 * the timing registers automatically when "set features" command is
128 * issued to the device. However, if the PLL output clock is 133 MHz,
129 * the following tables must be used.
130 */
131static struct pio_timing {
132 u8 reg0c, reg0d, reg13;
133} pio_timings [] = {
134 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
135 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
136 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
137 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
138 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
139};
140
141static struct mwdma_timing {
142 u8 reg0e, reg0f;
143} mwdma_timings [] = {
144 { 0xdf, 0x5f }, /* MWDMA mode 0 */
145 { 0x6b, 0x27 }, /* MWDMA mode 1 */
146 { 0x69, 0x25 }, /* MWDMA mode 2 */
147};
148
149static struct udma_timing {
150 u8 reg10, reg11, reg12;
151} udma_timings [] = {
152 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
153 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
154 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
155 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
156 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
157 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
158 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
159};
160
161static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
1da177e4
LT		 162{
163 ide_hwif_t *hwif = HWIF(drive);
47694bb8
SS		 164 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
165 int err;
1da177e4 166
47694bb8 167 speed = ide_rate_filter(pdcnew_ratemask(drive), speed);
1da177e4 168
47694bb8
SS		 169 /*
170 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
171 * automatically set the timing registers based on 100 MHz PLL output.
172 */
173 err = ide_config_drive_speed(drive, speed);
174
175 /*
176 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
177 * chips, we must override the default register settings...
178 */
179 if (max_dma_rate(hwif->pci_dev) == 4) {
180 u8 mode = speed & 0x07;
181
182 switch (speed) {
183 case XFER_UDMA_6:
184 case XFER_UDMA_5:
185 case XFER_UDMA_4:
186 case XFER_UDMA_3:
187 case XFER_UDMA_2:
188 case XFER_UDMA_1:
189 case XFER_UDMA_0:
190 set_indexed_reg(hwif, 0x10 + adj,
191 udma_timings[mode].reg10);
192 set_indexed_reg(hwif, 0x11 + adj,
193 udma_timings[mode].reg11);
194 set_indexed_reg(hwif, 0x12 + adj,
195 udma_timings[mode].reg12);
196 break;
197
198 case XFER_MW_DMA_2:
199 case XFER_MW_DMA_1:
200 case XFER_MW_DMA_0:
201 set_indexed_reg(hwif, 0x0e + adj,
202 mwdma_timings[mode].reg0e);
203 set_indexed_reg(hwif, 0x0f + adj,
204 mwdma_timings[mode].reg0f);
205 break;
206 case XFER_PIO_4:
207 case XFER_PIO_3:
208 case XFER_PIO_2:
209 case XFER_PIO_1:
210 case XFER_PIO_0:
211 set_indexed_reg(hwif, 0x0c + adj,
212 pio_timings[mode].reg0c);
213 set_indexed_reg(hwif, 0x0d + adj,
214 pio_timings[mode].reg0d);
215 set_indexed_reg(hwif, 0x13 + adj,
216 pio_timings[mode].reg13);
217 break;
218 default:
219 printk(KERN_ERR "pdc202xx_new: "
220 "Unknown speed %d ignored\n", speed);
221 }
222 } else if (speed == XFER_UDMA_2) {
223 /* Set tHOLD bit to 0 if using UDMA mode 2 */
224 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
225
226 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
227 }
228
229 return err;
1da177e4
LT		 230}
231
1da177e4
LT		 232static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
233{
b10a0686 234 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
47694bb8 235 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4
LT		 236}
237
47694bb8 238static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4 239{
47694bb8 240 return get_indexed_reg(hwif, 0x0b) & 0x04;
1da177e4 241}
47694bb8
SS		 242
243static int config_chipset_for_dma(ide_drive_t *drive)
1da177e4
LT		 244{
245 struct hd_driveid *id = drive->id;
246 ide_hwif_t *hwif = HWIF(drive);
47694bb8
SS		 247 u8 ultra_66 = (id->dma_ultra & 0x0078) ? 1 : 0;
248 u8 cable = pdcnew_cable_detect(hwif);
249 u8 speed;
1da177e4
LT		 250
251 if (ultra_66 && cable) {
47694bb8
SS		 252 printk(KERN_WARNING "Warning: %s channel "
253 "requires an 80-pin cable for operation.\n",
254 hwif->channel ? "Secondary" : "Primary");
1da177e4
LT		 255 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
256 }
257
258 if (drive->media != ide_disk)
259 return 0;
47694bb8
SS		 260
261 if (id->capability & 4) {
262 /*
263 * Set IORDY_EN & PREFETCH_EN (this seems to have
264 * NO real effect since this register is reloaded
265 * by hardware when the transfer mode is selected)
266 */
267 u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
268
269 tmp = get_indexed_reg(hwif, 0x13 + adj);
270 set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
1da177e4
LT		 271 }
272
273 speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
274
b10a0686 275 if (!speed)
1da177e4 276 return 0;
1da177e4
LT		 277
278 (void) hwif->speedproc(drive, speed);
279 return ide_dma_enable(drive);
280}
281
47694bb8 282static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
1da177e4
LT		 283{
284 ide_hwif_t *hwif = HWIF(drive);
285 struct hd_driveid *id = drive->id;
286
287 drive->init_speed = 0;
288
27210314 289 if ((id->capability & 1) && drive->autodma) {
1da177e4 290
27210314
SS		 291 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
292 return hwif->ide_dma_on(drive);
1da177e4
LT		 293
294 goto fast_ata_pio;
295
296 } else if ((id->capability & 8) || (id->field_valid & 2)) {
297fast_ata_pio:
b10a0686 298 hwif->tuneproc(drive, 255);
1da177e4
LT		 299 return hwif->ide_dma_off_quietly(drive);
300 }
301 /* IORDY not supported */
302 return 0;
303}
304
47694bb8 305static int pdcnew_quirkproc(ide_drive_t *drive)
1da177e4 306{
d24ec426
SS		 307 const char **list, *model = drive->id->model;
308
309 for (list = pdc_quirk_drives; *list != NULL; list++)
310 if (strstr(model, *list) != NULL)
311 return 2;
312 return 0;
1da177e4
LT		 313}
314
47694bb8 315static void pdcnew_reset(ide_drive_t *drive)
1da177e4
LT		 316{
317 /*
318 * Deleted this because it is redundant from the caller.
319 */
47694bb8 320 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4
LT		 321 HWIF(drive)->channel ? "Secondary" : "Primary");
322}
323
47694bb8
SS		 324/**
325 * read_counter - Read the byte count registers
326 * @dma_base: for the port address
327 */
328static long __devinit read_counter(u32 dma_base)
329{
330 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
331 u8 cnt0, cnt1, cnt2, cnt3;
332 long count = 0, last;
333 int retry = 3;
334
335 do {
336 last = count;
337
338 /* Read the current count */
339 outb(0x20, pri_dma_base + 0x01);
340 cnt0 = inb(pri_dma_base + 0x03);
341 outb(0x21, pri_dma_base + 0x01);
342 cnt1 = inb(pri_dma_base + 0x03);
343 outb(0x20, sec_dma_base + 0x01);
344 cnt2 = inb(sec_dma_base + 0x03);
345 outb(0x21, sec_dma_base + 0x01);
346 cnt3 = inb(sec_dma_base + 0x03);
347
348 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
349
350 /*
351 * The 30-bit decrementing counter is read in 4 pieces.
352 * Incorrect value may be read when the most significant bytes
353 * are changing...
354 */
355 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
356
357 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
358 cnt0, cnt1, cnt2, cnt3);
359
360 return count;
361}
362
363/**
364 * detect_pll_input_clock - Detect the PLL input clock in Hz.
365 * @dma_base: for the port address
366 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
367 */
368static long __devinit detect_pll_input_clock(unsigned long dma_base)
369{
370 long start_count, end_count;
371 long pll_input;
372 u8 scr1;
373
374 start_count = read_counter(dma_base);
375
376 /* Start the test mode */
377 outb(0x01, dma_base + 0x01);
378 scr1 = inb(dma_base + 0x03);
379 DBG("scr1[%02X]\n", scr1);
380 outb(scr1 | 0x40, dma_base + 0x03);
381
382 /* Let the counter run for 10 ms. */
383 mdelay(10);
384
385 end_count = read_counter(dma_base);
386
387 /* Stop the test mode */
388 outb(0x01, dma_base + 0x01);
389 scr1 = inb(dma_base + 0x03);
390 DBG("scr1[%02X]\n", scr1);
391 outb(scr1 & ~0x40, dma_base + 0x03);
392
393 /*
394 * Calculate the input clock in Hz
395 * (the clock counter is 30 bit wide and counts down)
396 */
397 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
398
399 DBG("start[%ld] end[%ld]\n", start_count, end_count);
400
401 return pll_input;
402}
403
1da177e4
LT		 404#ifdef CONFIG_PPC_PMAC
405static void __devinit apple_kiwi_init(struct pci_dev *pdev)
406{
407 struct device_node *np = pci_device_to_OF_node(pdev);
408 unsigned int class_rev = 0;
1da177e4
LT		 409 u8 conf;
410
411 if (np == NULL || !device_is_compatible(np, "kiwi-root"))
412 return;
413
414 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
415 class_rev &= 0xff;
416
417 if (class_rev >= 0x03) {
418 /* Setup chip magic config stuff (from darwin) */
47694bb8
SS		 419 pci_read_config_byte (pdev, 0x40, &conf);
420 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
1da177e4 421 }
1da177e4
LT		 422}
423#endif /* CONFIG_PPC_PMAC */
424
425static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
426{
47694bb8
SS		 427 unsigned long dma_base = pci_resource_start(dev, 4);
428 unsigned long sec_dma_base = dma_base + 0x08;
429 long pll_input, pll_output, ratio;
430 int f, r;
431 u8 pll_ctl0, pll_ctl1;
432
1da177e4
LT		 433 if (dev->resource[PCI_ROM_RESOURCE].start) {
434 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
435 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
08f46de9
GKH		 436 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
437 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
1da177e4
LT		 438 }
439
440#ifdef CONFIG_PPC_PMAC
441 apple_kiwi_init(dev);
442#endif
443
47694bb8
SS		 444 /* Calculate the required PLL output frequency */
445 switch(max_dma_rate(dev)) {
446 case 4: /* it's 133 MHz for Ultra133 chips */
447 pll_output = 133333333;
448 break;
449 case 3: /* and 100 MHz for Ultra100 chips */
450 default:
451 pll_output = 100000000;
452 break;
453 }
454
455 /*
456 * Detect PLL input clock.
457 * On some systems, where PCI bus is running at non-standard clock rate
458 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
459 * PDC20268 and newer chips employ PLL circuit to help correct timing
460 * registers setting.
461 */
462 pll_input = detect_pll_input_clock(dma_base);
463 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
464
465 /* Sanity check */
466 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
467 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
468 name, pll_input);
469 goto out;
470 }
471
472#ifdef DEBUG
473 DBG("pll_output is %ld Hz\n", pll_output);
474
475 /* Show the current clock value of PLL control register
476 * (maybe already configured by the BIOS)
477 */
478 outb(0x02, sec_dma_base + 0x01);
479 pll_ctl0 = inb(sec_dma_base + 0x03);
480 outb(0x03, sec_dma_base + 0x01);
481 pll_ctl1 = inb(sec_dma_base + 0x03);
482
483 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
484#endif
485
486 /*
487 * Calculate the ratio of F, R and NO
488 * POUT = (F + 2) / (( R + 2) * NO)
489 */
490 ratio = pll_output / (pll_input / 1000);
491 if (ratio < 8600L) { /* 8.6x */
492 /* Using NO = 0x01, R = 0x0d */
493 r = 0x0d;
494 } else if (ratio < 12900L) { /* 12.9x */
495 /* Using NO = 0x01, R = 0x08 */
496 r = 0x08;
497 } else if (ratio < 16100L) { /* 16.1x */
498 /* Using NO = 0x01, R = 0x06 */
499 r = 0x06;
500 } else if (ratio < 64000L) { /* 64x */
501 r = 0x00;
502 } else {
503 /* Invalid ratio */
504 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
505 goto out;
506 }
507
508 f = (ratio * (r + 2)) / 1000 - 2;
509
510 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
511
512 if (unlikely(f < 0 || f > 127)) {
513 /* Invalid F */
514 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
515 goto out;
516 }
517
518 pll_ctl0 = (u8) f;
519 pll_ctl1 = (u8) r;
520
521 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
522
523 outb(0x02, sec_dma_base + 0x01);
524 outb(pll_ctl0, sec_dma_base + 0x03);
525 outb(0x03, sec_dma_base + 0x01);
526 outb(pll_ctl1, sec_dma_base + 0x03);
527
528 /* Wait the PLL circuit to be stable */
529 mdelay(30);
530
531#ifdef DEBUG
532 /*
533 * Show the current clock value of PLL control register
534 */
535 outb(0x02, sec_dma_base + 0x01);
536 pll_ctl0 = inb(sec_dma_base + 0x03);
537 outb(0x03, sec_dma_base + 0x01);
538 pll_ctl1 = inb(sec_dma_base + 0x03);
539
540 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
541#endif
542
543 out:
1da177e4
LT		 544 return dev->irq;
545}
546
547static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
548{
549 hwif->autodma = 0;
550
551 hwif->tuneproc = &pdcnew_tune_drive;
552 hwif->quirkproc = &pdcnew_quirkproc;
47694bb8
SS		 553 hwif->speedproc = &pdcnew_tune_chipset;
554 hwif->resetproc = &pdcnew_reset;
1da177e4
LT		 555
556 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
557
558 hwif->ultra_mask = 0x7f;
559 hwif->mwdma_mask = 0x07;
560
3706a872
AC		 561 hwif->err_stops_fifo = 1;
562
1da177e4 563 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
47694bb8
SS		 564
565 if (!hwif->udma_four)
566 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
567
1da177e4
LT		 568 if (!noautodma)
569 hwif->autodma = 1;
570 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
47694bb8 571
1da177e4
LT		 572#if PDC202_DEBUG_CABLE
573 printk(KERN_DEBUG "%s: %s-pin cable\n",
574 hwif->name, hwif->udma_four ? "80" : "40");
575#endif /* PDC202_DEBUG_CABLE */
576}
577
578static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
579{
580 return ide_setup_pci_device(dev, d);
581}
582
583static int __devinit init_setup_pdc20270(struct pci_dev *dev,
584 ide_pci_device_t *d)
585{
586 struct pci_dev *findev = NULL;
b1489009 587 int ret;
1da177e4
LT		 588
589 if ((dev->bus->self &&
590 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
591 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
592 if (PCI_SLOT(dev->devfn) & 2)
593 return -ENODEV;
594 d->extra = 0;
b1489009 595 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1da177e4
LT		 596 if ((findev->vendor == dev->vendor) &&
597 (findev->device == dev->device) &&
598 (PCI_SLOT(findev->devfn) & 2)) {
599 if (findev->irq != dev->irq) {
600 findev->irq = dev->irq;
601 }
b1489009
AC		 602 ret = ide_setup_pci_devices(dev, findev, d);
603 pci_dev_put(findev);
604 return ret;
1da177e4
LT		 605 }
606 }
607 }
608 return ide_setup_pci_device(dev, d);
609}
610
611static int __devinit init_setup_pdc20276(struct pci_dev *dev,
612 ide_pci_device_t *d)
613{
614 if ((dev->bus->self) &&
615 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
616 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
617 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
618 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
619 "attached to I2O RAID controller.\n");
620 return -ENODEV;
621 }
622 return ide_setup_pci_device(dev, d);
623}
624
625static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
626 { /* 0 */
627 .name = "PDC20268",
628 .init_setup = init_setup_pdcnew,
629 .init_chipset = init_chipset_pdcnew,
630 .init_hwif = init_hwif_pdc202new,
631 .channels = 2,
632 .autodma = AUTODMA,
633 .bootable = OFF_BOARD,
634 },{ /* 1 */
635 .name = "PDC20269",
636 .init_setup = init_setup_pdcnew,
637 .init_chipset = init_chipset_pdcnew,
638 .init_hwif = init_hwif_pdc202new,
639 .channels = 2,
640 .autodma = AUTODMA,
641 .bootable = OFF_BOARD,
642 },{ /* 2 */
643 .name = "PDC20270",
644 .init_setup = init_setup_pdc20270,
645 .init_chipset = init_chipset_pdcnew,
646 .init_hwif = init_hwif_pdc202new,
647 .channels = 2,
648 .autodma = AUTODMA,
1da177e4
LT		 649 .bootable = OFF_BOARD,
650 },{ /* 3 */
651 .name = "PDC20271",
652 .init_setup = init_setup_pdcnew,
653 .init_chipset = init_chipset_pdcnew,
654 .init_hwif = init_hwif_pdc202new,
655 .channels = 2,
656 .autodma = AUTODMA,
657 .bootable = OFF_BOARD,
658 },{ /* 4 */
659 .name = "PDC20275",
660 .init_setup = init_setup_pdcnew,
661 .init_chipset = init_chipset_pdcnew,
662 .init_hwif = init_hwif_pdc202new,
663 .channels = 2,
664 .autodma = AUTODMA,
665 .bootable = OFF_BOARD,
666 },{ /* 5 */
667 .name = "PDC20276",
668 .init_setup = init_setup_pdc20276,
669 .init_chipset = init_chipset_pdcnew,
670 .init_hwif = init_hwif_pdc202new,
671 .channels = 2,
672 .autodma = AUTODMA,
1da177e4
LT		 673 .bootable = OFF_BOARD,
674 },{ /* 6 */
675 .name = "PDC20277",
676 .init_setup = init_setup_pdcnew,
677 .init_chipset = init_chipset_pdcnew,
678 .init_hwif = init_hwif_pdc202new,
679 .channels = 2,
680 .autodma = AUTODMA,
681 .bootable = OFF_BOARD,
682 }
683};
684
685/**
686 * pdc202new_init_one - called when a pdc202xx is found
687 * @dev: the pdc202new device
688 * @id: the matching pci id
689 *
690 * Called when the PCI registration layer (or the IDE initialization)
691 * finds a device matching our IDE device tables.
692 */
693
694static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
695{
696 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
697
698 return d->init_setup(dev, d);
699}
700
701static struct pci_device_id pdc202new_pci_tbl[] = {
702 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
703 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
704 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
705 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
706 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
707 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
708 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
709 { 0, },
710};
711MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
712
713static struct pci_driver driver = {
714 .name = "Promise_IDE",
715 .id_table = pdc202new_pci_tbl,
716 .probe = pdc202new_init_one,
717};
718
82ab1eec 719static int __init pdc202new_ide_init(void)
1da177e4
LT		 720{
721 return ide_pci_register_driver(&driver);
722}
723
724module_init(pdc202new_ide_init);
725
726MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
727MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
728MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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