[deliverable/linux.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_vendor1);
	value = inb(hwif->dma_vendor3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_vendor1);
	outb(value, hwif->dma_vendor3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;
	int			err;

	/*
	 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 */
 	err = ide_config_drive_speed(drive, speed);

	/*
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(hwif->pci_dev) == 4) {
		u8 mode = speed & 0x07;

		switch (speed) {
			case XFER_UDMA_6:
			case XFER_UDMA_5:
			case XFER_UDMA_4:
			case XFER_UDMA_3:
			case XFER_UDMA_2:
			case XFER_UDMA_1:
			case XFER_UDMA_0:
				set_indexed_reg(hwif, 0x10 + adj,
						udma_timings[mode].reg10);
				set_indexed_reg(hwif, 0x11 + adj,
						udma_timings[mode].reg11);
				set_indexed_reg(hwif, 0x12 + adj,
						udma_timings[mode].reg12);
				break;

			case XFER_MW_DMA_2:
			case XFER_MW_DMA_1:
			case XFER_MW_DMA_0:
				set_indexed_reg(hwif, 0x0e + adj,
						mwdma_timings[mode].reg0e);
				set_indexed_reg(hwif, 0x0f + adj,
						mwdma_timings[mode].reg0f);
				break;
			case XFER_PIO_4:
			case XFER_PIO_3:
			case XFER_PIO_2:
			case XFER_PIO_1:
			case XFER_PIO_0:
				set_indexed_reg(hwif, 0x0c + adj,
						pio_timings[mode].reg0c);
				set_indexed_reg(hwif, 0x0d + adj,
						pio_timings[mode].reg0d);
				set_indexed_reg(hwif, 0x13 + adj,
						pio_timings[mode].reg13);
				break;
			default:
				printk(KERN_ERR "pdc202xx_new: "
				       "Unknown speed %d ignored\n", speed);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}

	return err;
}

static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 4);
	(void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		pdcnew_tune_drive(drive, 255);

	return -1;
}

static int pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	struct timeval start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	do_gettimeofday(&start_time);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	do_gettimeofday(&end_time);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
		(end_time.tv_usec - start_time.tv_usec);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	unsigned int class_rev = 0;
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xff;

	if (class_rev >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
{
	hwif->autodma = 0;

	hwif->tuneproc  = &pdcnew_tune_drive;
	hwif->quirkproc = &pdcnew_quirkproc;
	hwif->speedproc = &pdcnew_tune_chipset;
	hwif->resetproc = &pdcnew_reset;

	hwif->err_stops_fifo = 1;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->atapi_dma  = 1;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = pdcnew_cable_detect(hwif);

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *bridge = dev->bus->self;

	if (bridge != NULL &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
							PCI_FUNC(dev->devfn)));
		if (dev2 != NULL &&
		    dev2->vendor == dev->vendor &&
		    dev2->device == dev->device) {
			int ret;

			if (dev2->irq != dev->irq) {
				dev2->irq = dev->irq;

				printk(KERN_WARNING "%s: PCI config space "
				       "interrupt fixed.\n", d->name);
			}

			ret = ide_setup_pci_devices(dev, dev2, d);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *bridge = dev->bus->self;

	if (bridge != NULL &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	   (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	    bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {

		printk(KERN_INFO "%s: attached to I2O RAID controller, "
				 "skipping.\n", d->name);
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20268",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 1 */
		.name		= "PDC20269",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 2 */
		.name		= "PDC20270",
		.init_setup	= init_setup_pdc20270,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 3 */
		.name		= "PDC20271",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 4 */
		.name		= "PDC20275",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 5 */
		.name		= "PDC20276",
		.init_setup	= init_setup_pdc20276,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
	},{	/* 6 */
		.name		= "PDC20277",
		.init_setup	= init_setup_pdcnew,
		.init_chipset	= init_chipset_pdcnew,
		.init_hwif	= init_hwif_pdc202new,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x7f, /* udma0-6*/
	}
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202new_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	12	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
	22	#include <linux/timer.h>
	23	#include <linux/mm.h>
	24	#include <linux/ioport.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/ide.h>
	31
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34
	35	#ifdef CONFIG_PPC_PMAC
	36	#include <asm/prom.h>
	37	#include <asm/pci-bridge.h>
	38	#endif
	39
47694bb8 SS	40	#undef DEBUG
	41
	42	#ifdef DEBUG
	43	#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
	44	#else
	45	#define DBG(fmt, args...)
	46	#endif
	47
3c6bee1d	48	static const char *pdc_quirk_drives[] = {
1da177e4 LT	49	"QUANTUM FIREBALLlct08 08",
	50	"QUANTUM FIREBALLP KA6.4",
	51	"QUANTUM FIREBALLP KA9.1",
	52	"QUANTUM FIREBALLP LM20.4",
	53	"QUANTUM FIREBALLP KX13.6",
	54	"QUANTUM FIREBALLP KX20.5",
	55	"QUANTUM FIREBALLP KX27.3",
	56	"QUANTUM FIREBALLP LM20.5",
	57	NULL
	58	};
	59
47694bb8	60	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	61	{
	62	u8 mode;
	63
47694bb8	64	switch(pdev->device) {
1da177e4 LT	65	case PCI_DEVICE_ID_PROMISE_20277:
	66	case PCI_DEVICE_ID_PROMISE_20276:
	67	case PCI_DEVICE_ID_PROMISE_20275:
	68	case PCI_DEVICE_ID_PROMISE_20271:
	69	case PCI_DEVICE_ID_PROMISE_20269:
	70	mode = 4;
	71	break;
	72	case PCI_DEVICE_ID_PROMISE_20270:
	73	case PCI_DEVICE_ID_PROMISE_20268:
	74	mode = 3;
	75	break;
	76	default:
	77	return 0;
	78	}
47694bb8	79
1da177e4 LT	80	return mode;
	81	}
	82
47694bb8 SS	83	/**
	84	* get_indexed_reg - Get indexed register
	85	* @hwif: for the port address
	86	* @index: index of the indexed register
	87	*/
	88	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	89	{
	90	u8 value;
	91
0ecdca26 BZ	92	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	93	value = inb(hwif->dma_vendor3);
47694bb8 SS	94
	95	DBG("index[%02X] value[%02X]\n", index, value);
	96	return value;
	97	}
	98
	99	/**
	100	* set_indexed_reg - Set indexed register
	101	* @hwif: for the port address
	102	* @index: index of the indexed register
	103	*/
	104	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	105	{
0ecdca26 BZ	106	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	107	outb(value, hwif->dma_vendor3);
47694bb8 SS	108	DBG("index[%02X] value[%02X]\n", index, value);
	109	}
	110
	111	/*
	112	* ATA Timing Tables based on 133 MHz PLL output clock.
	113	*
	114	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	115	* the timing registers automatically when "set features" command is
	116	* issued to the device. However, if the PLL output clock is 133 MHz,
	117	* the following tables must be used.
	118	*/
	119	static struct pio_timing {
	120	u8 reg0c, reg0d, reg13;
	121	} pio_timings [] = {
	122	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	123	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	124	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	125	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	126	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	127	};
	128
	129	static struct mwdma_timing {
	130	u8 reg0e, reg0f;
	131	} mwdma_timings [] = {
	132	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	133	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	134	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	135	};
	136
	137	static struct udma_timing {
	138	u8 reg10, reg11, reg12;
	139	} udma_timings [] = {
	140	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	141	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	142	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	143	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	144	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	145	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	146	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	147	};
	148
f212ff28	149	static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4 LT	150	{
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
47694bb8 SS	152	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
47694bb8 SS	153	int err;
1da177e4	154
47694bb8 SS	155	/*
	156	* Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
	157	* automatically set the timing registers based on 100 MHz PLL output.
	158	*/
	159	err = ide_config_drive_speed(drive, speed);
	160
	161	/*
	162	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	163	* chips, we must override the default register settings...
	164	*/
	165	if (max_dma_rate(hwif->pci_dev) == 4) {
	166	u8 mode = speed & 0x07;
	167
	168	switch (speed) {
	169	case XFER_UDMA_6:
	170	case XFER_UDMA_5:
	171	case XFER_UDMA_4:
	172	case XFER_UDMA_3:
	173	case XFER_UDMA_2:
	174	case XFER_UDMA_1:
	175	case XFER_UDMA_0:
	176	set_indexed_reg(hwif, 0x10 + adj,
	177	udma_timings[mode].reg10);
	178	set_indexed_reg(hwif, 0x11 + adj,
	179	udma_timings[mode].reg11);
	180	set_indexed_reg(hwif, 0x12 + adj,
	181	udma_timings[mode].reg12);
	182	break;
	183
	184	case XFER_MW_DMA_2:
	185	case XFER_MW_DMA_1:
	186	case XFER_MW_DMA_0:
	187	set_indexed_reg(hwif, 0x0e + adj,
	188	mwdma_timings[mode].reg0e);
	189	set_indexed_reg(hwif, 0x0f + adj,
	190	mwdma_timings[mode].reg0f);
	191	break;
	192	case XFER_PIO_4:
	193	case XFER_PIO_3:
	194	case XFER_PIO_2:
	195	case XFER_PIO_1:
	196	case XFER_PIO_0:
	197	set_indexed_reg(hwif, 0x0c + adj,
	198	pio_timings[mode].reg0c);
	199	set_indexed_reg(hwif, 0x0d + adj,
	200	pio_timings[mode].reg0d);
	201	set_indexed_reg(hwif, 0x13 + adj,
	202	pio_timings[mode].reg13);
	203	break;
	204	default:
	205	printk(KERN_ERR "pdc202xx_new: "
	206	"Unknown speed %d ignored\n", speed);
	207	}
	208	} else if (speed == XFER_UDMA_2) {
	209	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	210	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	211
	212	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	213	}
	214
	215	return err;
1da177e4 LT	216	}
1da177e4 LT	217
1da177e4 LT	218	static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4 LT	219	{
2134758d	220	pio = ide_get_best_pio_mode(drive, pio, 4);
47694bb8	221	(void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4 LT	222	}
1da177e4 LT	223
47694bb8	224	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	225	{
49521f97 BZ	226	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	227	return ATA_CBL_PATA40;
	228	else
	229	return ATA_CBL_PATA80;
1da177e4	230	}
47694bb8	231
47694bb8	232	static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
1da177e4	233	{
1da177e4 LT	234	drive->init_speed = 0;
1da177e4 LT	235
7f86723a	236	if (ide_tune_dma(drive))
3608b5d7	237	return 0;
1da177e4	238
d8f4469d	239	if (ide_use_fast_pio(drive))
3608b5d7	240	pdcnew_tune_drive(drive, 255);
d8f4469d	241
3608b5d7	242	return -1;
1da177e4 LT	243	}
1da177e4 LT	244
47694bb8	245	static int pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	246	{
d24ec426 SS	247	const char *list, model = drive->id->model;
	248
	249	for (list = pdc_quirk_drives; *list != NULL; list++)
	250	if (strstr(model, *list) != NULL)
	251	return 2;
	252	return 0;
1da177e4 LT	253	}
1da177e4 LT	254
47694bb8	255	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	256	{
	257	/*
	258	* Deleted this because it is redundant from the caller.
	259	*/
47694bb8	260	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	261	HWIF(drive)->channel ? "Secondary" : "Primary");
	262	}
	263
47694bb8 SS	264	/**
	265	* read_counter - Read the byte count registers
	266	* @dma_base: for the port address
	267	*/
	268	static long __devinit read_counter(u32 dma_base)
	269	{
	270	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	271	u8 cnt0, cnt1, cnt2, cnt3;
	272	long count = 0, last;
	273	int retry = 3;
	274
	275	do {
	276	last = count;
	277
	278	/* Read the current count */
	279	outb(0x20, pri_dma_base + 0x01);
	280	cnt0 = inb(pri_dma_base + 0x03);
	281	outb(0x21, pri_dma_base + 0x01);
	282	cnt1 = inb(pri_dma_base + 0x03);
	283	outb(0x20, sec_dma_base + 0x01);
	284	cnt2 = inb(sec_dma_base + 0x03);
	285	outb(0x21, sec_dma_base + 0x01);
	286	cnt3 = inb(sec_dma_base + 0x03);
	287
	288	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	289
	290	/*
	291	* The 30-bit decrementing counter is read in 4 pieces.
	292	* Incorrect value may be read when the most significant bytes
	293	* are changing...
	294	*/
	295	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	296
	297	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	298	cnt0, cnt1, cnt2, cnt3);
	299
	300	return count;
	301	}
	302
	303	/**
	304	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	305	* @dma_base: for the port address
	306	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	307	*/
	308	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	309	{
8006bf56	310	struct timeval start_time, end_time;
47694bb8	311	long start_count, end_count;
8006bf56	312	long pll_input, usec_elapsed;
47694bb8 SS	313	u8 scr1;
	314
	315	start_count = read_counter(dma_base);
8006bf56	316	do_gettimeofday(&start_time);
47694bb8 SS	317
	318	/* Start the test mode */
	319	outb(0x01, dma_base + 0x01);
	320	scr1 = inb(dma_base + 0x03);
	321	DBG("scr1[%02X]\n", scr1);
	322	outb(scr1 \| 0x40, dma_base + 0x03);
	323
	324	/* Let the counter run for 10 ms. */
	325	mdelay(10);
	326
	327	end_count = read_counter(dma_base);
8006bf56	328	do_gettimeofday(&end_time);
47694bb8 SS	329
	330	/* Stop the test mode */
	331	outb(0x01, dma_base + 0x01);
	332	scr1 = inb(dma_base + 0x03);
	333	DBG("scr1[%02X]\n", scr1);
	334	outb(scr1 & ~0x40, dma_base + 0x03);
	335
	336	/*
	337	* Calculate the input clock in Hz
	338	* (the clock counter is 30 bit wide and counts down)
	339	*/
8006bf56 AL	340	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
8006bf56 AL	341	(end_time.tv_usec - start_time.tv_usec);
56fe23d5	342	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	343	(10000000 / usec_elapsed);
47694bb8 SS	344
	345	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	346
	347	return pll_input;
	348	}
	349
1da177e4 LT	350	#ifdef CONFIG_PPC_PMAC
	351	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	352	{
	353	struct device_node *np = pci_device_to_OF_node(pdev);
	354	unsigned int class_rev = 0;
1da177e4 LT	355	u8 conf;
1da177e4 LT	356
55b61fec	357	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	358	return;
	359
	360	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	361	class_rev &= 0xff;
	362
	363	if (class_rev >= 0x03) {
	364	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	365	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	366	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	367	}
1da177e4 LT	368	}
	369	#endif /* CONFIG_PPC_PMAC */
	370
	371	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	372	{
47694bb8 SS	373	unsigned long dma_base = pci_resource_start(dev, 4);
	374	unsigned long sec_dma_base = dma_base + 0x08;
	375	long pll_input, pll_output, ratio;
	376	int f, r;
	377	u8 pll_ctl0, pll_ctl1;
	378
01cc643a BZ	379	if (dma_base == 0)
	380	return -EFAULT;
	381
1da177e4 LT	382	#ifdef CONFIG_PPC_PMAC
	383	apple_kiwi_init(dev);
	384	#endif
	385
47694bb8 SS	386	/* Calculate the required PLL output frequency */
	387	switch(max_dma_rate(dev)) {
	388	case 4: /* it's 133 MHz for Ultra133 chips */
	389	pll_output = 133333333;
	390	break;
	391	case 3: /* and 100 MHz for Ultra100 chips */
	392	default:
	393	pll_output = 100000000;
	394	break;
	395	}
	396
	397	/*
	398	* Detect PLL input clock.
	399	* On some systems, where PCI bus is running at non-standard clock rate
	400	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	401	* PDC20268 and newer chips employ PLL circuit to help correct timing
	402	* registers setting.
	403	*/
	404	pll_input = detect_pll_input_clock(dma_base);
	405	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	406
	407	/* Sanity check */
	408	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	409	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	410	name, pll_input);
	411	goto out;
	412	}
	413
	414	#ifdef DEBUG
	415	DBG("pll_output is %ld Hz\n", pll_output);
	416
	417	/* Show the current clock value of PLL control register
	418	* (maybe already configured by the BIOS)
	419	*/
	420	outb(0x02, sec_dma_base + 0x01);
	421	pll_ctl0 = inb(sec_dma_base + 0x03);
	422	outb(0x03, sec_dma_base + 0x01);
	423	pll_ctl1 = inb(sec_dma_base + 0x03);
	424
	425	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	426	#endif
	427
	428	/*
	429	* Calculate the ratio of F, R and NO
	430	* POUT = (F + 2) / (( R + 2) * NO)
	431	*/
	432	ratio = pll_output / (pll_input / 1000);
	433	if (ratio < 8600L) { /* 8.6x */
	434	/* Using NO = 0x01, R = 0x0d */
	435	r = 0x0d;
	436	} else if (ratio < 12900L) { /* 12.9x */
	437	/* Using NO = 0x01, R = 0x08 */
	438	r = 0x08;
	439	} else if (ratio < 16100L) { /* 16.1x */
	440	/* Using NO = 0x01, R = 0x06 */
	441	r = 0x06;
	442	} else if (ratio < 64000L) { /* 64x */
	443	r = 0x00;
	444	} else {
	445	/* Invalid ratio */
	446	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	447	goto out;
	448	}
	449
450	f = (ratio * (r + 2)) / 1000 - 2;
451
452	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
453
454	if (unlikely(f < 0 \|\| f > 127)) {
455	/* Invalid F */
456	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
457	goto out;
458	}
459
460	pll_ctl0 = (u8) f;
461	pll_ctl1 = (u8) r;
462
463	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
464
465	outb(0x02, sec_dma_base + 0x01);
466	outb(pll_ctl0, sec_dma_base + 0x03);
467	outb(0x03, sec_dma_base + 0x01);
468	outb(pll_ctl1, sec_dma_base + 0x03);
469
470	/* Wait the PLL circuit to be stable */
471	mdelay(30);
472
473	#ifdef DEBUG
474	/*
475	* Show the current clock value of PLL control register
476	*/
477	outb(0x02, sec_dma_base + 0x01);
478	pll_ctl0 = inb(sec_dma_base + 0x03);
479	outb(0x03, sec_dma_base + 0x01);
480	pll_ctl1 = inb(sec_dma_base + 0x03);
481
482	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
483	#endif
484
485	out:
1da177e4 LT	486	return dev->irq;
	487	}
	488
	489	static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
	490	{
	491	hwif->autodma = 0;
	492
	493	hwif->tuneproc = &pdcnew_tune_drive;
	494	hwif->quirkproc = &pdcnew_quirkproc;
47694bb8 SS	495	hwif->speedproc = &pdcnew_tune_chipset;
47694bb8 SS	496	hwif->resetproc = &pdcnew_reset;
1da177e4	497
01cc643a BZ	498	hwif->err_stops_fifo = 1;
01cc643a BZ	499
1da177e4 LT	500	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4 LT	501
01cc643a BZ	502	if (hwif->dma_base == 0)
	503	return;
	504
362ebd83	505	hwif->atapi_dma = 1;
18137207 BZ	506
18137207 BZ	507	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4 LT	508	hwif->mwdma_mask = 0x07;
	509
	510	hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
47694bb8	511
49521f97 BZ	512	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	513	hwif->cbl = pdcnew_cable_detect(hwif);
47694bb8	514
1da177e4 LT	515	if (!noautodma)
	516	hwif->autodma = 1;
	517	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	518	}
	519
	520	static int __devinit init_setup_pdcnew(struct pci_dev dev, ide_pci_device_t d)
	521	{
	522	return ide_setup_pci_device(dev, d);
	523	}
	524
07047935	525	static int __devinit init_setup_pdc20270(struct pci_dev dev, ide_pci_device_t d)
1da177e4	526	{
07047935 SS	527	struct pci_dev *bridge = dev->bus->self;
	528
	529	if (bridge != NULL &&
	530	bridge->vendor == PCI_VENDOR_ID_DEC &&
	531	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	532	struct pci_dev *dev2;
1da177e4	533
1da177e4 LT	534	if (PCI_SLOT(dev->devfn) & 2)
1da177e4 LT	535	return -ENODEV;
35198234	536
07047935 SS	537	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
	538	PCI_FUNC(dev->devfn)));
	539	if (dev2 != NULL &&
	540	dev2->vendor == dev->vendor &&
	541	dev2->device == dev->device) {
	542	int ret;
	543
	544	if (dev2->irq != dev->irq) {
	545	dev2->irq = dev->irq;
	546
	547	printk(KERN_WARNING "%s: PCI config space "
	548	"interrupt fixed.\n", d->name);
1da177e4	549	}
07047935 SS	550
	551	ret = ide_setup_pci_devices(dev, dev2, d);
	552	if (ret < 0)
	553	pci_dev_put(dev2);
	554	return ret;
1da177e4 LT	555	}
	556	}
	557	return ide_setup_pci_device(dev, d);
	558	}
	559
07047935	560	static int __devinit init_setup_pdc20276(struct pci_dev dev, ide_pci_device_t d)
1da177e4	561	{
07047935 SS	562	struct pci_dev *bridge = dev->bus->self;
	563
	564	if (bridge != NULL &&
	565	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	566	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	567	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	568
	569	printk(KERN_INFO "%s: attached to I2O RAID controller, "
	570	"skipping.\n", d->name);
1da177e4 LT	571	return -ENODEV;
	572	}
	573	return ide_setup_pci_device(dev, d);
	574	}
	575
	576	static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
	577	{ /* 0 */
	578	.name = "PDC20268",
	579	.init_setup = init_setup_pdcnew,
	580	.init_chipset = init_chipset_pdcnew,
	581	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	582	.autodma = AUTODMA,
1da177e4 LT	583	.bootable = OFF_BOARD,
4099d143	584	.pio_mask = ATA_PIO4,
18137207	585	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	586	},{ /* 1 */
	587	.name = "PDC20269",
	588	.init_setup = init_setup_pdcnew,
	589	.init_chipset = init_chipset_pdcnew,
	590	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	591	.autodma = AUTODMA,
1da177e4 LT	592	.bootable = OFF_BOARD,
4099d143	593	.pio_mask = ATA_PIO4,
18137207	594	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	595	},{ /* 2 */
	596	.name = "PDC20270",
	597	.init_setup = init_setup_pdc20270,
	598	.init_chipset = init_chipset_pdcnew,
	599	.init_hwif = init_hwif_pdc202new,
1da177e4	600	.autodma = AUTODMA,
1da177e4	601	.bootable = OFF_BOARD,
4099d143	602	.pio_mask = ATA_PIO4,
18137207	603	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	604	},{ /* 3 */
	605	.name = "PDC20271",
	606	.init_setup = init_setup_pdcnew,
	607	.init_chipset = init_chipset_pdcnew,
	608	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	609	.autodma = AUTODMA,
1da177e4 LT	610	.bootable = OFF_BOARD,
4099d143	611	.pio_mask = ATA_PIO4,
18137207	612	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	613	},{ /* 4 */
	614	.name = "PDC20275",
	615	.init_setup = init_setup_pdcnew,
	616	.init_chipset = init_chipset_pdcnew,
	617	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	618	.autodma = AUTODMA,
1da177e4 LT	619	.bootable = OFF_BOARD,
4099d143	620	.pio_mask = ATA_PIO4,
18137207	621	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	622	},{ /* 5 */
	623	.name = "PDC20276",
	624	.init_setup = init_setup_pdc20276,
	625	.init_chipset = init_chipset_pdcnew,
	626	.init_hwif = init_hwif_pdc202new,
1da177e4	627	.autodma = AUTODMA,
1da177e4	628	.bootable = OFF_BOARD,
4099d143	629	.pio_mask = ATA_PIO4,
18137207	630	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	631	},{ /* 6 */
	632	.name = "PDC20277",
	633	.init_setup = init_setup_pdcnew,
	634	.init_chipset = init_chipset_pdcnew,
	635	.init_hwif = init_hwif_pdc202new,
1da177e4 LT	636	.autodma = AUTODMA,
1da177e4 LT	637	.bootable = OFF_BOARD,
4099d143	638	.pio_mask = ATA_PIO4,
18137207	639	.udma_mask = 0x7f, /* udma0-6*/
1da177e4 LT	640	}
	641	};
	642
	643	/**
	644	* pdc202new_init_one - called when a pdc202xx is found
	645	* @dev: the pdc202new device
	646	* @id: the matching pci id
	647	*
	648	* Called when the PCI registration layer (or the IDE initialization)
	649	* finds a device matching our IDE device tables.
	650	*/
	651
	652	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	653	{
	654	ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
	655
	656	return d->init_setup(dev, d);
	657	}
	658
	659	static struct pci_device_id pdc202new_pci_tbl[] = {
	660	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	661	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	662	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	663	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	664	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	665	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
	666	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
	667	{ 0, },
	668	};
	669	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	670
	671	static struct pci_driver driver = {
	672	.name = "Promise_IDE",
	673	.id_table = pdc202new_pci_tbl,
	674	.probe = pdc202new_init_one,
	675	};
	676
82ab1eec	677	static int __init pdc202new_ide_init(void)
1da177e4 LT	678	{
	679	return ide_pci_register_driver(&driver);
	680	}
	681
	682	module_init(pdc202new_ide_init);
	683
	684	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	685	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	686	MODULE_LICENSE("GPL");