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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003 | |
3 | * | |
4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
7 | * | |
8 | * May be copied or modified under the terms of the GNU General Public License | |
9 | * | |
10 | * PIO mode setting function for Intel chipsets. | |
11 | * For use instead of BIOS settings. | |
12 | * | |
13 | * 40-41 | |
14 | * 42-43 | |
15 | * | |
16 | * 41 | |
17 | * 43 | |
18 | * | |
19 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); | |
20 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); | |
21 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); | |
22 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); | |
23 | * | |
24 | * sitre = word40 & 0x4000; primary | |
25 | * sitre = word42 & 0x4000; secondary | |
26 | * | |
27 | * 44 8421|8421 hdd|hdb | |
28 | * | |
29 | * 48 8421 hdd|hdc|hdb|hda udma enabled | |
30 | * | |
31 | * 0001 hda | |
32 | * 0010 hdb | |
33 | * 0100 hdc | |
34 | * 1000 hdd | |
35 | * | |
36 | * 4a 84|21 hdb|hda | |
37 | * 4b 84|21 hdd|hdc | |
38 | * | |
39 | * ata-33/82371AB | |
40 | * ata-33/82371EB | |
41 | * ata-33/82801AB ata-66/82801AA | |
42 | * 00|00 udma 0 00|00 reserved | |
43 | * 01|01 udma 1 01|01 udma 3 | |
44 | * 10|10 udma 2 10|10 udma 4 | |
45 | * 11|11 reserved 11|11 reserved | |
46 | * | |
47 | * 54 8421|8421 ata66 drive|ata66 enable | |
48 | * | |
49 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); | |
50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); | |
51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); | |
52 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); | |
53 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); | |
54 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); | |
55 | * | |
56 | * Documentation | |
57 | * Publically available from Intel web site. Errata documentation | |
58 | * is also publically available. As an aide to anyone hacking on this | |
59 | * driver the list of errata that are relevant is below.going back to | |
60 | * PIIX4. Older device documentation is now a bit tricky to find. | |
61 | * | |
62 | * Errata of note: | |
63 | * | |
64 | * Unfixable | |
65 | * PIIX4 errata #9 - Only on ultra obscure hw | |
66 | * ICH3 errata #13 - Not observed to affect real hw | |
67 | * by Intel | |
68 | * | |
69 | * Things we must deal with | |
70 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
71 | * (must stop/start dma to recover) | |
72 | * 440MX errata #15 - As PIIX4 errata #10 | |
73 | * PIIX4 errata #15 - Must not read control registers | |
74 | * during a PIO transfer | |
75 | * 440MX errata #13 - As PIIX4 errata #15 | |
76 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
77 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
78 | * ICH2 spec c #9 - Extra operations needed to handle | |
79 | * drive hotswap [NOT YET SUPPORTED] | |
80 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
81 | * and must be dword aligned | |
82 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
83 | * | |
84 | * Should have been BIOS fixed: | |
85 | * 450NX: errata #19 - DMA hangs on old 450NX | |
86 | * 450NX: errata #20 - DMA hangs on old 450NX | |
87 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
88 | * ICH3 errata #15 - IDE deadlock under high load | |
89 | * (BIOS must set dev 31 fn 0 bit 23) | |
90 | * ICH3 errata #18 - Don't use native mode | |
91 | */ | |
92 | ||
1da177e4 LT |
93 | #include <linux/types.h> |
94 | #include <linux/module.h> | |
95 | #include <linux/kernel.h> | |
96 | #include <linux/ioport.h> | |
97 | #include <linux/pci.h> | |
98 | #include <linux/hdreg.h> | |
99 | #include <linux/ide.h> | |
100 | #include <linux/delay.h> | |
101 | #include <linux/init.h> | |
102 | ||
103 | #include <asm/io.h> | |
104 | ||
105 | static int no_piix_dma; | |
106 | ||
107 | /** | |
108 | * piix_ratemask - compute rate mask for PIIX IDE | |
109 | * @drive: IDE drive to compute for | |
110 | * | |
111 | * Returns the available modes for the PIIX IDE controller. | |
112 | */ | |
113 | ||
114 | static u8 piix_ratemask (ide_drive_t *drive) | |
115 | { | |
116 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
117 | u8 mode; | |
118 | ||
119 | switch(dev->device) { | |
120 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
121 | mode = 3; | |
122 | break; | |
123 | /* UDMA 100 capable */ | |
124 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
125 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
126 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
127 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
128 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
129 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
130 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
131 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
132 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
133 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
134 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
135 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 136 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 137 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
1da177e4 LT |
138 | mode = 3; |
139 | break; | |
140 | /* UDMA 66 capable */ | |
141 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
142 | case PCI_DEVICE_ID_INTEL_82372FB_1: | |
143 | mode = 2; | |
144 | break; | |
145 | /* UDMA 33 capable */ | |
146 | case PCI_DEVICE_ID_INTEL_82371AB: | |
147 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
148 | case PCI_DEVICE_ID_INTEL_82451NX: | |
149 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
150 | return 1; | |
151 | /* Non UDMA capable (MWDMA2) */ | |
152 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
153 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
154 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
155 | case PCI_DEVICE_ID_INTEL_82371MX: | |
156 | default: | |
157 | return 0; | |
158 | } | |
159 | ||
160 | /* | |
161 | * If we are UDMA66 capable fall back to UDMA33 | |
162 | * if the drive cannot see an 80pin cable. | |
163 | */ | |
164 | if (!eighty_ninty_three(drive)) | |
165 | mode = min(mode, (u8)1); | |
166 | return mode; | |
167 | } | |
168 | ||
169 | /** | |
170 | * piix_dma_2_pio - return the PIO mode matching DMA | |
171 | * @xfer_rate: transfer speed | |
172 | * | |
173 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
174 | * mode requested by the controller. | |
175 | */ | |
176 | ||
177 | static u8 piix_dma_2_pio (u8 xfer_rate) { | |
178 | switch(xfer_rate) { | |
179 | case XFER_UDMA_6: | |
180 | case XFER_UDMA_5: | |
181 | case XFER_UDMA_4: | |
182 | case XFER_UDMA_3: | |
183 | case XFER_UDMA_2: | |
184 | case XFER_UDMA_1: | |
185 | case XFER_UDMA_0: | |
186 | case XFER_MW_DMA_2: | |
187 | case XFER_PIO_4: | |
188 | return 4; | |
189 | case XFER_MW_DMA_1: | |
190 | case XFER_PIO_3: | |
191 | return 3; | |
192 | case XFER_SW_DMA_2: | |
193 | case XFER_PIO_2: | |
194 | return 2; | |
195 | case XFER_MW_DMA_0: | |
196 | case XFER_SW_DMA_1: | |
197 | case XFER_SW_DMA_0: | |
198 | case XFER_PIO_1: | |
199 | case XFER_PIO_0: | |
200 | case XFER_PIO_SLOW: | |
201 | default: | |
202 | return 0; | |
203 | } | |
204 | } | |
205 | ||
206 | /** | |
207 | * piix_tune_drive - tune a drive attached to a PIIX | |
208 | * @drive: drive to tune | |
209 | * @pio: desired PIO mode | |
210 | * | |
211 | * Set the interface PIO mode based upon the settings done by AMI BIOS | |
212 | * (might be useful if drive is not registered in CMOS for any reason). | |
213 | */ | |
214 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) | |
215 | { | |
216 | ide_hwif_t *hwif = HWIF(drive); | |
217 | struct pci_dev *dev = hwif->pci_dev; | |
218 | int is_slave = (&hwif->drives[1] == drive); | |
219 | int master_port = hwif->channel ? 0x42 : 0x40; | |
220 | int slave_port = 0x44; | |
221 | unsigned long flags; | |
222 | u16 master_data; | |
223 | u8 slave_data; | |
4fb0f76d | 224 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 225 | int control = 0; |
4fb0f76d | 226 | |
1da177e4 | 227 | /* ISP RTC */ |
5ac24697 AC |
228 | static const u8 timings[][2]= { |
229 | { 0, 0 }, | |
230 | { 0, 0 }, | |
231 | { 1, 0 }, | |
232 | { 2, 1 }, | |
233 | { 2, 3 }, }; | |
1da177e4 LT |
234 | |
235 | pio = ide_get_best_pio_mode(drive, pio, 5, NULL); | |
4fb0f76d AC |
236 | |
237 | /* | |
238 | * Master vs slave is synchronized above us but the slave register is | |
239 | * shared by the two hwifs so the corner case of two slave timeouts in | |
240 | * parallel must be locked. | |
241 | */ | |
242 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 243 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 AC |
244 | |
245 | if (pio >= 2) | |
246 | control |= 1; /* Programmable timing on */ | |
247 | if (drive->media == ide_disk) | |
248 | control |= 4; /* Prefetch, post write */ | |
249 | if (pio >= 3) | |
250 | control |= 2; /* IORDY */ | |
1da177e4 LT |
251 | if (is_slave) { |
252 | master_data = master_data | 0x4000; | |
5ac24697 | 253 | if (pio > 1) { |
1da177e4 | 254 | /* enable PPE, IE and TIME */ |
5ac24697 AC |
255 | master_data = master_data | (control << 4); |
256 | } else { | |
257 | master_data &= ~0x0070; | |
258 | } | |
1da177e4 LT |
259 | pci_read_config_byte(dev, slave_port, &slave_data); |
260 | slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); | |
261 | slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); | |
262 | } else { | |
263 | master_data = master_data & 0xccf8; | |
5ac24697 | 264 | if (pio > 1) { |
1da177e4 | 265 | /* enable PPE, IE and TIME */ |
5ac24697 AC |
266 | master_data = master_data | control; |
267 | } | |
1da177e4 LT |
268 | master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); |
269 | } | |
270 | pci_write_config_word(dev, master_port, master_data); | |
271 | if (is_slave) | |
272 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 273 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
274 | } |
275 | ||
276 | /** | |
277 | * piix_tune_chipset - tune a PIIX interface | |
278 | * @drive: IDE drive to tune | |
279 | * @xferspeed: speed to configure | |
280 | * | |
281 | * Set a PIIX interface channel to the desired speeds. This involves | |
282 | * requires the right timing data into the PIIX configuration space | |
283 | * then setting the drive parameters appropriately | |
284 | */ | |
285 | ||
286 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
287 | { | |
288 | ide_hwif_t *hwif = HWIF(drive); | |
289 | struct pci_dev *dev = hwif->pci_dev; | |
290 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
291 | u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); | |
292 | int a_speed = 3 << (drive->dn * 4); | |
293 | int u_flag = 1 << drive->dn; | |
294 | int v_flag = 0x01 << drive->dn; | |
295 | int w_flag = 0x10 << drive->dn; | |
296 | int u_speed = 0; | |
297 | int sitre; | |
298 | u16 reg4042, reg4a; | |
299 | u8 reg48, reg54, reg55; | |
300 | ||
301 | pci_read_config_word(dev, maslave, ®4042); | |
302 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
303 | pci_read_config_byte(dev, 0x48, ®48); | |
304 | pci_read_config_word(dev, 0x4a, ®4a); | |
305 | pci_read_config_byte(dev, 0x54, ®54); | |
306 | pci_read_config_byte(dev, 0x55, ®55); | |
307 | ||
308 | switch(speed) { | |
309 | case XFER_UDMA_4: | |
310 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
311 | case XFER_UDMA_5: | |
312 | case XFER_UDMA_3: | |
313 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
314 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
315 | case XFER_MW_DMA_2: | |
316 | case XFER_MW_DMA_1: | |
317 | case XFER_SW_DMA_2: break; | |
318 | case XFER_PIO_4: | |
319 | case XFER_PIO_3: | |
320 | case XFER_PIO_2: | |
321 | case XFER_PIO_0: break; | |
322 | default: return -1; | |
323 | } | |
324 | ||
325 | if (speed >= XFER_UDMA_0) { | |
326 | if (!(reg48 & u_flag)) | |
327 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
328 | if (speed == XFER_UDMA_5) { | |
329 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
330 | } else { | |
331 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
332 | } | |
333 | if ((reg4a & a_speed) != u_speed) | |
334 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
335 | if (speed > XFER_UDMA_2) { | |
336 | if (!(reg54 & v_flag)) | |
337 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
338 | } else | |
339 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
340 | } else { | |
341 | if (reg48 & u_flag) | |
342 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
343 | if (reg4a & a_speed) | |
344 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
345 | if (reg54 & v_flag) | |
346 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
347 | if (reg55 & w_flag) | |
348 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
349 | } | |
350 | ||
351 | piix_tune_drive(drive, piix_dma_2_pio(speed)); | |
352 | return (ide_config_drive_speed(drive, speed)); | |
353 | } | |
354 | ||
1da177e4 LT |
355 | /** |
356 | * piix_config_drive_for_dma - configure drive for DMA | |
357 | * @drive: IDE drive to configure | |
358 | * | |
359 | * Set up a PIIX interface channel for the best available speed. | |
360 | * We prefer UDMA if it is available and then MWDMA. If DMA is | |
361 | * not available we switch to PIO and return 0. | |
362 | */ | |
363 | ||
364 | static int piix_config_drive_for_dma (ide_drive_t *drive) | |
365 | { | |
366 | u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); | |
1da177e4 LT |
367 | |
368 | /* If no DMA speed was available or the chipset has DMA bugs | |
369 | then disable DMA and use PIO */ | |
370 | ||
371 | if (!speed || no_piix_dma) { | |
372 | u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL); | |
373 | speed = piix_dma_2_pio(XFER_PIO_0 + tspeed); | |
374 | } | |
375 | ||
376 | (void) piix_tune_chipset(drive, speed); | |
377 | return ide_dma_enable(drive); | |
378 | } | |
379 | ||
380 | /** | |
381 | * piix_config_drive_xfer_rate - set up an IDE device | |
382 | * @drive: IDE drive to configure | |
383 | * | |
384 | * Set up the PIIX interface for the best available speed on this | |
385 | * interface, preferring DMA to PIO. | |
386 | */ | |
387 | ||
388 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) | |
389 | { | |
390 | ide_hwif_t *hwif = HWIF(drive); | |
391 | struct hd_driveid *id = drive->id; | |
392 | ||
393 | drive->init_speed = 0; | |
394 | ||
395 | if ((id->capability & 1) && drive->autodma) { | |
396 | ||
397 | if (ide_use_dma(drive)) { | |
398 | if (piix_config_drive_for_dma(drive)) | |
399 | return hwif->ide_dma_on(drive); | |
400 | } | |
401 | ||
402 | goto fast_ata_pio; | |
403 | ||
404 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
405 | fast_ata_pio: | |
406 | /* Find best PIO mode. */ | |
407 | hwif->tuneproc(drive, 255); | |
408 | return hwif->ide_dma_off_quietly(drive); | |
409 | } | |
410 | /* IORDY not supported */ | |
411 | return 0; | |
412 | } | |
413 | ||
414 | /** | |
415 | * init_chipset_piix - set up the PIIX chipset | |
416 | * @dev: PCI device to set up | |
417 | * @name: Name of the device | |
418 | * | |
419 | * Initialize the PCI device as required. For the PIIX this turns | |
420 | * out to be nice and simple | |
421 | */ | |
422 | ||
423 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) | |
424 | { | |
425 | switch(dev->device) { | |
426 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
427 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
428 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
429 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
430 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
431 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
432 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
433 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
434 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
435 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
436 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
437 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
438 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
439 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
440 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 441 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 442 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
1da177e4 LT |
443 | { |
444 | unsigned int extra = 0; | |
445 | pci_read_config_dword(dev, 0x54, &extra); | |
446 | pci_write_config_dword(dev, 0x54, extra|0x400); | |
447 | } | |
448 | default: | |
449 | break; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | /** | |
456 | * init_hwif_piix - fill in the hwif for the PIIX | |
457 | * @hwif: IDE interface | |
458 | * | |
459 | * Set up the ide_hwif_t for the PIIX interface according to the | |
460 | * capabilities of the hardware. | |
461 | */ | |
462 | ||
463 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
464 | { | |
465 | u8 reg54h = 0, reg55h = 0, ata66 = 0; | |
466 | u8 mask = hwif->channel ? 0xc0 : 0x30; | |
467 | ||
468 | #ifndef CONFIG_IA64 | |
469 | if (!hwif->irq) | |
470 | hwif->irq = hwif->channel ? 15 : 14; | |
471 | #endif /* CONFIG_IA64 */ | |
472 | ||
473 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { | |
474 | /* This is a painful system best to let it self tune for now */ | |
475 | return; | |
476 | } | |
ee2f344b AC |
477 | /* ESB2 appears to generate spurious DMA interrupts in PIO mode |
478 | when in native mode */ | |
479 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_ESB2_18) | |
480 | hwif->atapi_irq_bogon = 1; | |
1da177e4 LT |
481 | |
482 | hwif->autodma = 0; | |
483 | hwif->tuneproc = &piix_tune_drive; | |
484 | hwif->speedproc = &piix_tune_chipset; | |
485 | hwif->drives[0].autotune = 1; | |
486 | hwif->drives[1].autotune = 1; | |
487 | ||
488 | if (!hwif->dma_base) | |
489 | return; | |
490 | ||
491 | hwif->atapi_dma = 1; | |
492 | hwif->ultra_mask = 0x3f; | |
493 | hwif->mwdma_mask = 0x06; | |
494 | hwif->swdma_mask = 0x04; | |
495 | ||
496 | switch(hwif->pci_dev->device) { | |
497 | case PCI_DEVICE_ID_INTEL_82371MX: | |
498 | hwif->mwdma_mask = 0x80; | |
499 | hwif->swdma_mask = 0x80; | |
500 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
501 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
502 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
503 | hwif->ultra_mask = 0x80; | |
504 | break; | |
505 | case PCI_DEVICE_ID_INTEL_82371AB: | |
506 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
507 | case PCI_DEVICE_ID_INTEL_82451NX: | |
508 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
509 | hwif->ultra_mask = 0x07; | |
510 | break; | |
511 | default: | |
512 | pci_read_config_byte(hwif->pci_dev, 0x54, ®54h); | |
513 | pci_read_config_byte(hwif->pci_dev, 0x55, ®55h); | |
514 | ata66 = (reg54h & mask) ? 1 : 0; | |
515 | break; | |
516 | } | |
517 | ||
518 | if (!(hwif->udma_four)) | |
519 | hwif->udma_four = ata66; | |
520 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; | |
521 | if (!noautodma) | |
522 | hwif->autodma = 1; | |
523 | ||
524 | hwif->drives[1].autodma = hwif->autodma; | |
525 | hwif->drives[0].autodma = hwif->autodma; | |
526 | } | |
527 | ||
528 | #define DECLARE_PIIX_DEV(name_str) \ | |
529 | { \ | |
530 | .name = name_str, \ | |
531 | .init_chipset = init_chipset_piix, \ | |
532 | .init_hwif = init_hwif_piix, \ | |
533 | .channels = 2, \ | |
534 | .autodma = AUTODMA, \ | |
535 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
536 | .bootable = ON_BOARD, \ | |
537 | } | |
538 | ||
539 | static ide_pci_device_t piix_pci_info[] __devinitdata = { | |
540 | /* 0 */ DECLARE_PIIX_DEV("PIIXa"), | |
541 | /* 1 */ DECLARE_PIIX_DEV("PIIXb"), | |
542 | ||
543 | { /* 2 */ | |
544 | .name = "MPIIX", | |
545 | .init_hwif = init_hwif_piix, | |
546 | .channels = 2, | |
547 | .autodma = NODMA, | |
548 | .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, | |
549 | .bootable = ON_BOARD, | |
550 | }, | |
551 | ||
552 | /* 3 */ DECLARE_PIIX_DEV("PIIX3"), | |
553 | /* 4 */ DECLARE_PIIX_DEV("PIIX4"), | |
554 | /* 5 */ DECLARE_PIIX_DEV("ICH0"), | |
555 | /* 6 */ DECLARE_PIIX_DEV("PIIX4"), | |
556 | /* 7 */ DECLARE_PIIX_DEV("ICH"), | |
557 | /* 8 */ DECLARE_PIIX_DEV("PIIX4"), | |
558 | /* 9 */ DECLARE_PIIX_DEV("PIIX4"), | |
559 | /* 10 */ DECLARE_PIIX_DEV("ICH2"), | |
560 | /* 11 */ DECLARE_PIIX_DEV("ICH2M"), | |
561 | /* 12 */ DECLARE_PIIX_DEV("ICH3M"), | |
562 | /* 13 */ DECLARE_PIIX_DEV("ICH3"), | |
563 | /* 14 */ DECLARE_PIIX_DEV("ICH4"), | |
564 | /* 15 */ DECLARE_PIIX_DEV("ICH5"), | |
565 | /* 16 */ DECLARE_PIIX_DEV("C-ICH"), | |
566 | /* 17 */ DECLARE_PIIX_DEV("ICH4"), | |
567 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), | |
568 | /* 19 */ DECLARE_PIIX_DEV("ICH5"), | |
569 | /* 20 */ DECLARE_PIIX_DEV("ICH6"), | |
570 | /* 21 */ DECLARE_PIIX_DEV("ICH7"), | |
571 | /* 22 */ DECLARE_PIIX_DEV("ICH4"), | |
d69332b8 | 572 | /* 23 */ DECLARE_PIIX_DEV("ESB2"), |
b7bed9ec | 573 | /* 24 */ DECLARE_PIIX_DEV("ICH8M"), |
1da177e4 LT |
574 | }; |
575 | ||
576 | /** | |
577 | * piix_init_one - called when a PIIX is found | |
578 | * @dev: the piix device | |
579 | * @id: the matching pci id | |
580 | * | |
581 | * Called when the PCI registration layer (or the IDE initialization) | |
582 | * finds a device matching our IDE device tables. | |
583 | */ | |
584 | ||
585 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
586 | { | |
587 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; | |
588 | ||
589 | return ide_setup_pci_device(dev, d); | |
590 | } | |
591 | ||
592 | /** | |
593 | * piix_check_450nx - Check for problem 450NX setup | |
594 | * | |
595 | * Check for the present of 450NX errata #19 and errata #25. If | |
596 | * they are found, disable use of DMA IDE | |
597 | */ | |
598 | ||
599 | static void __devinit piix_check_450nx(void) | |
600 | { | |
601 | struct pci_dev *pdev = NULL; | |
602 | u16 cfg; | |
603 | u8 rev; | |
1424e504 | 604 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
605 | { |
606 | /* Look for 450NX PXB. Check for problem configurations | |
607 | A PCI quirk checks bit 6 already */ | |
608 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
609 | pci_read_config_word(pdev, 0x41, &cfg); | |
610 | /* Only on the original revision: IDE DMA can hang */ | |
611 | if(rev == 0x00) | |
612 | no_piix_dma = 1; | |
613 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
614 | else if(cfg & (1<<14) && rev < 5) | |
615 | no_piix_dma = 2; | |
616 | } | |
617 | if(no_piix_dma) | |
618 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); | |
619 | if(no_piix_dma == 2) | |
620 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); | |
621 | } | |
622 | ||
623 | static struct pci_device_id piix_pci_tbl[] = { | |
624 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
625 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
626 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
627 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
628 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
629 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
630 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, | |
631 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, | |
632 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, | |
633 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, | |
634 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, | |
635 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, | |
636 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, | |
637 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, | |
638 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, | |
639 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, | |
640 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, | |
641 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, | |
642 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
643 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, | |
644 | #endif | |
645 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, | |
646 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, | |
647 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, | |
648 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, | |
d69332b8 | 649 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
b7bed9ec | 650 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
1da177e4 LT |
651 | { 0, }, |
652 | }; | |
653 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
654 | ||
655 | static struct pci_driver driver = { | |
656 | .name = "PIIX_IDE", | |
657 | .id_table = piix_pci_tbl, | |
658 | .probe = piix_init_one, | |
659 | }; | |
660 | ||
661 | static int __init piix_ide_init(void) | |
662 | { | |
663 | piix_check_450nx(); | |
664 | return ide_pci_register_driver(&driver); | |
665 | } | |
666 | ||
667 | module_init(piix_ide_init); | |
668 | ||
669 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
670 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
671 | MODULE_LICENSE("GPL"); |