[deliverable/linux.git] / drivers / ide / pci / piix.c

/*
 *  linux/drivers/ide/pci/piix.c	Version 0.54	Sep 5, 2007
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  PIO mode setting function for Intel chipsets.
 *  For use instead of BIOS settings.
 *
 * 40-41
 * 42-43
 * 
 *                 41
 *                 43
 *
 * | PIO 0       | c0 | 80 | 0 |
 * | PIO 2 | SW2 | d0 | 90 | 4 |
 * | PIO 3 | MW1 | e1 | a1 | 9 |
 * | PIO 4 | MW2 | e3 | a3 | b |
 *
 * sitre = word40 & 0x4000; primary
 * sitre = word42 & 0x4000; secondary
 *
 * 44 8421|8421    hdd|hdb
 *
 * 48 8421         hdd|hdc|hdb|hda udma enabled
 *
 *    0001         hda
 *    0010         hdb
 *    0100         hdc
 *    1000         hdd
 *
 * 4a 84|21        hdb|hda
 * 4b 84|21        hdd|hdc
 *
 *    ata-33/82371AB
 *    ata-33/82371EB
 *    ata-33/82801AB            ata-66/82801AA
 *    00|00 udma 0              00|00 reserved
 *    01|01 udma 1              01|01 udma 3
 *    10|10 udma 2              10|10 udma 4
 *    11|11 reserved            11|11 reserved
 *
 * 54 8421|8421    ata66 drive|ata66 enable
 *
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
 *
 * Documentation
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
 * driver the list of errata that are relevant is below.going back to
 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

static int no_piix_dma;

/**
 *	piix_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode based upon the settings done by AMI BIOS.
 */

static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	static DEFINE_SPINLOCK(tune_lock);
	int control = 0;

				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	/*
	 * Master vs slave is synchronized above us but the slave register is
	 * shared by the two hwifs so the corner case of two slave timeouts in
	 * parallel must be locked.
	 */
	spin_lock_irqsave(&tune_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&tune_lock, flags);
}

/**
 *	piix_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a PIIX host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int a_speed		= 3 << (drive->dn * 4);
	int u_flag		= 1 << drive->dn;
	int v_flag		= 0x01 << drive->dn;
	int w_flag		= 0x10 << drive->dn;
	int u_speed		= 0;
	int			sitre;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	if (speed >= XFER_UDMA_0) {
		u8 udma = speed - XFER_UDMA_0;

		u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);

		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed == XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}
		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };
		u8 pio;

		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);

		if (speed >= XFER_MW_DMA_0)
			pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
		else
			pio = 2; /* only SWDMA2 is allowed */

		piix_set_pio_mode(drive, pio);
	}
}

/**
 *	init_chipset_ich	-	set up the ICH chipset
 *	@dev: PCI device to set up
 *	@name: Name of the device
 *
 *	Initialize the PCI device as required.  For the ICH this turns
 *	out to be nice and simple.
 */

static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
{
	u32 extra = 0;

	pci_read_config_dword(dev, 0x54, &extra);
	pci_write_config_dword(dev, 0x54, extra | 0x400);

	return 0;
}

/**
 *	piix_dma_clear_irq	-	clear BMDMA status
 *	@drive: IDE drive to clear
 *
 *	Called from ide_intr() for PIO interrupts
 *	to clear BMDMA status as needed by ICHx
 */
static void piix_dma_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	u8 dma_stat;

	/* clear the INTR & ERROR bits */
	dma_stat = inb(hwif->dma_status);
	/* Should we force the bit as well ? */
	outb(dma_stat, hwif->dma_status);
}

struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on Acer Aspire 2023WLMi */
	/* end marker */
	{ 0, }
};

static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = hwif->pci_dev;
	const struct ich_laptop *lap = &ich_laptop[0];
	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;

	/* check for specials */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
		    lap->subdevice == pdev->subsystem_device) {
			return ATA_CBL_PATA40_SHORT;
		}
		lap++;
	}

	pci_read_config_byte(pdev, 0x54, &reg54h);

	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/**
 *	init_hwif_piix		-	fill in the hwif for the PIIX
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the PIIX interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_piix(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &piix_set_pio_mode;
	hwif->set_dma_mode = &piix_set_dma_mode;

	if (!hwif->dma_base)
		return;

	if (hwif->ultra_mask & 0x78) {
		if (hwif->cbl != ATA_CBL_PATA40_SHORT)
			hwif->cbl = piix_cable_detect(hwif);
	}

	if (no_piix_dma)
		hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
}

static void __devinit init_hwif_ich(ide_hwif_t *hwif)
{
	init_hwif_piix(hwif);

	/* ICHx need to clear the BMDMA status for all interrupts */
	if (hwif->dma_base)
		hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
}

#ifndef CONFIG_IA64
 #define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE)
#else
 #define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
#endif

#define DECLARE_PIIX_DEV(name_str, udma) \
	{						\
		.name		= name_str,		\
		.init_hwif	= init_hwif_piix,	\
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.host_flags	= IDE_HFLAGS_PIIX,	\
		.pio_mask	= ATA_PIO4,		\
		.swdma_mask	= ATA_SWDMA2_ONLY,	\
		.mwdma_mask	= ATA_MWDMA12_ONLY,	\
		.udma_mask	= udma,			\
	}

#define DECLARE_ICH_DEV(name_str, udma) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_ich, \
		.init_hwif	= init_hwif_ich, \
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.host_flags	= IDE_HFLAGS_PIIX, \
		.pio_mask	= ATA_PIO4, \
		.swdma_mask	= ATA_SWDMA2_ONLY, \
		.mwdma_mask	= ATA_MWDMA12_ONLY, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info piix_pci_info[] __devinitdata = {
	/*  0 */ DECLARE_PIIX_DEV("PIIXa",	0x00),	/* no udma */
	/*  1 */ DECLARE_PIIX_DEV("PIIXb",	0x00),	/* no udma */

	/*  2 */
	{	/*
		 * MPIIX actually has only a single IDE channel mapped to
		 * the primary or secondary ports depending on the value
		 * of the bit 14 of the IDETIM register at offset 0x6c
		 */
		.name		= "MPIIX",
		.enablebits	= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
		.host_flags	= IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
				  IDE_HFLAGS_PIIX,
		.pio_mask	= ATA_PIO4,
		/* This is a painful system best to let it self tune for now */
	},

	/*  3 */ DECLARE_PIIX_DEV("PIIX3",	0x00),	/* no udma */
	/*  4 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  5 */ DECLARE_ICH_DEV("ICH0",	ATA_UDMA2),
	/*  6 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  7 */ DECLARE_ICH_DEV("ICH",		ATA_UDMA4),
	/*  8 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA4),
	/*  9 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/* 10 */ DECLARE_ICH_DEV("ICH2",	ATA_UDMA5),
	/* 11 */ DECLARE_ICH_DEV("ICH2M",	ATA_UDMA5),
	/* 12 */ DECLARE_ICH_DEV("ICH3M",	ATA_UDMA5),
	/* 13 */ DECLARE_ICH_DEV("ICH3",	ATA_UDMA5),
	/* 14 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 15 */ DECLARE_ICH_DEV("ICH5",	ATA_UDMA5),
	/* 16 */ DECLARE_ICH_DEV("C-ICH",	ATA_UDMA5),
	/* 17 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 18 */ DECLARE_ICH_DEV("ICH5-SATA",	ATA_UDMA5),
	/* 19 */ DECLARE_ICH_DEV("ICH5",	ATA_UDMA5),
	/* 20 */ DECLARE_ICH_DEV("ICH6",	ATA_UDMA5),
	/* 21 */ DECLARE_ICH_DEV("ICH7",	ATA_UDMA5),
	/* 22 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 23 */ DECLARE_ICH_DEV("ESB2",	ATA_UDMA5),
	/* 24 */ DECLARE_ICH_DEV("ICH8M",	ATA_UDMA5),
};

/**
 *	piix_init_one	-	called when a PIIX is found
 *	@dev: the piix device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
}

/**
 *	piix_check_450nx	-	Check for problem 450NX setup
 *	
 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found, disable use of DMA IDE
 */

static void __devinit piix_check_450nx(void)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
	{
		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
		if (pdev->revision == 0x00)
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
		else if (cfg & (1<<14) && pdev->revision < 5)
			no_piix_dma = 2;
	}
	if(no_piix_dma)
		printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	if(no_piix_dma == 2)
		printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
}		

static const struct pci_device_id piix_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
#endif
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);

static struct pci_driver driver = {
	.name		= "PIIX_IDE",
	.id_table	= piix_pci_tbl,
	.probe		= piix_init_one,
};

static int __init piix_ide_init(void)
{
	piix_check_450nx();
	return ide_pci_register_driver(&driver);
}

module_init(piix_ide_init);

MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
31e8a465	2	* linux/drivers/ide/pci/piix.c Version 0.54 Sep 5, 2007
1da177e4 LT	3	*
	4	* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
	5	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	6	* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
07af4276	7	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	8	*
	9	* May be copied or modified under the terms of the GNU General Public License
	10	*
44854add	11	* PIO mode setting function for Intel chipsets.
1da177e4 LT	12	* For use instead of BIOS settings.
	13	*
	14	* 40-41
	15	* 42-43
	16	*
	17	* 41
	18	* 43
	19	*
26bcb879 BZ	20	* \| PIO 0 \| c0 \| 80 \| 0 \|
	21	* \| PIO 2 \| SW2 \| d0 \| 90 \| 4 \|
	22	* \| PIO 3 \| MW1 \| e1 \| a1 \| 9 \|
	23	* \| PIO 4 \| MW2 \| e3 \| a3 \| b \|
	24	*
1da177e4 LT	25	* sitre = word40 & 0x4000; primary
	26	* sitre = word42 & 0x4000; secondary
	27	*
	28	* 44 8421\|8421 hdd\|hdb
44854add	29	*
1da177e4 LT	30	* 48 8421 hdd\|hdc\|hdb\|hda udma enabled
	31	*
	32	* 0001 hda
	33	* 0010 hdb
	34	* 0100 hdc
	35	* 1000 hdd
	36	*
	37	* 4a 84\|21 hdb\|hda
	38	* 4b 84\|21 hdd\|hdc
	39	*
	40	* ata-33/82371AB
	41	* ata-33/82371EB
	42	* ata-33/82801AB ata-66/82801AA
	43	* 00\|00 udma 0 00\|00 reserved
	44	* 01\|01 udma 1 01\|01 udma 3
	45	* 10\|10 udma 2 10\|10 udma 4
	46	* 11\|11 reserved 11\|11 reserved
	47	*
	48	* 54 8421\|8421 ata66 drive\|ata66 enable
	49	*
	50	* pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
	51	* pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
	52	* pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
	53	* pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
	54	* pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
	55	* pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
	56	*
	57	* Documentation
	58	* Publically available from Intel web site. Errata documentation
	59	* is also publically available. As an aide to anyone hacking on this
	60	* driver the list of errata that are relevant is below.going back to
	61	* PIIX4. Older device documentation is now a bit tricky to find.
	62	*
	63	* Errata of note:
	64	*
	65	* Unfixable
	66	* PIIX4 errata #9 - Only on ultra obscure hw
	67	* ICH3 errata #13 - Not observed to affect real hw
	68	* by Intel
	69	*
	70	* Things we must deal with
	71	* PIIX4 errata #10 - BM IDE hang with non UDMA
	72	* (must stop/start dma to recover)
	73	* 440MX errata #15 - As PIIX4 errata #10
	74	* PIIX4 errata #15 - Must not read control registers
	75	* during a PIO transfer
	76	* 440MX errata #13 - As PIIX4 errata #15
	77	* ICH2 errata #21 - DMA mode 0 doesn't work right
	78	* ICH0/1 errata #55 - As ICH2 errata #21
	79	* ICH2 spec c #9 - Extra operations needed to handle
	80	* drive hotswap [NOT YET SUPPORTED]
	81	* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
	82	* and must be dword aligned
	83	* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
	84	*
	85	* Should have been BIOS fixed:
	86	* 450NX: errata #19 - DMA hangs on old 450NX
	87	* 450NX: errata #20 - DMA hangs on old 450NX
	88	* 450NX: errata #25 - Corruption with DMA on old 450NX
	89	* ICH3 errata #15 - IDE deadlock under high load
	90	* (BIOS must set dev 31 fn 0 bit 23)
	91	* ICH3 errata #18 - Don't use native mode
	92	*/
	93
1da177e4 LT	94	#include <linux/types.h>
	95	#include <linux/module.h>
	96	#include <linux/kernel.h>
	97	#include <linux/ioport.h>
	98	#include <linux/pci.h>
	99	#include <linux/hdreg.h>
	100	#include <linux/ide.h>
	101	#include <linux/delay.h>
	102	#include <linux/init.h>
	103
	104	#include <asm/io.h>
	105
	106	static int no_piix_dma;
	107
1da177e4	108	/**
88b2b32b BZ	109	* piix_set_pio_mode - set host controller for PIO mode
	110	* @drive: drive
	111	* @pio: PIO mode number
1da177e4	112	*
07af4276	113	* Set the interface PIO mode based upon the settings done by AMI BIOS.
1da177e4	114	*/
88b2b32b BZ	115
88b2b32b BZ	116	static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	117	{
	118	ide_hwif_t *hwif = HWIF(drive);
	119	struct pci_dev *dev = hwif->pci_dev;
30dfd12f	120	int is_slave = drive->dn & 1;
1da177e4 LT	121	int master_port = hwif->channel ? 0x42 : 0x40;
	122	int slave_port = 0x44;
	123	unsigned long flags;
	124	u16 master_data;
	125	u8 slave_data;
4fb0f76d	126	static DEFINE_SPINLOCK(tune_lock);
5ac24697	127	int control = 0;
4fb0f76d	128
30dfd12f	129	/* ISP RTC */
5ac24697 AC	130	static const u8 timings[][2]= {
	131	{ 0, 0 },
	132	{ 0, 0 },
	133	{ 1, 0 },
	134	{ 2, 1 },
	135	{ 2, 3 }, };
1da177e4	136
4fb0f76d AC	137	/*
	138	* Master vs slave is synchronized above us but the slave register is
	139	* shared by the two hwifs so the corner case of two slave timeouts in
	140	* parallel must be locked.
	141	*/
	142	spin_lock_irqsave(&tune_lock, flags);
1da177e4	143	pci_read_config_word(dev, master_port, &master_data);
5ac24697	144
30dfd12f	145	if (pio > 1)
5ac24697 AC	146	control \|= 1; /* Programmable timing on */
	147	if (drive->media == ide_disk)
	148	control \|= 4; /* Prefetch, post write */
30dfd12f	149	if (pio > 2)
5ac24697	150	control \|= 2; /* IORDY */
1da177e4	151	if (is_slave) {
30dfd12f SS	152	master_data \|= 0x4000;
30dfd12f SS	153	master_data &= ~0x0070;
5ac24697	154	if (pio > 1) {
07af4276 SS	155	/* Set PPE, IE and TIME */
07af4276 SS	156	master_data \|= control << 4;
5ac24697	157	}
1da177e4	158	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	159	slave_data &= hwif->channel ? 0x0f : 0xf0;
	160	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	161	(hwif->channel ? 4 : 0);
1da177e4	162	} else {
30dfd12f	163	master_data &= ~0x3307;
5ac24697	164	if (pio > 1) {
1da177e4	165	/* enable PPE, IE and TIME */
07af4276	166	master_data \|= control;
5ac24697	167	}
07af4276	168	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	169	}
	170	pci_write_config_word(dev, master_port, master_data);
	171	if (is_slave)
	172	pci_write_config_byte(dev, slave_port, slave_data);
4fb0f76d	173	spin_unlock_irqrestore(&tune_lock, flags);
1da177e4 LT	174	}
1da177e4 LT	175
07af4276	176	/**
88b2b32b BZ	177	* piix_set_dma_mode - set host controller for DMA mode
	178	* @drive: drive
	179	* @speed: DMA mode
1da177e4	180	*
88b2b32b BZ	181	* Set a PIIX host controller to the desired DMA mode. This involves
88b2b32b BZ	182	* programming the right timing data into the PCI configuration space.
1da177e4	183	*/
f212ff28	184
88b2b32b	185	static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	186	{
	187	ide_hwif_t *hwif = HWIF(drive);
	188	struct pci_dev *dev = hwif->pci_dev;
	189	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	190	int a_speed = 3 << (drive->dn * 4);
	191	int u_flag = 1 << drive->dn;
	192	int v_flag = 0x01 << drive->dn;
	193	int w_flag = 0x10 << drive->dn;
	194	int u_speed = 0;
	195	int sitre;
	196	u16 reg4042, reg4a;
1c54a93d	197	u8 reg48, reg54, reg55;
1da177e4 LT	198
	199	pci_read_config_word(dev, maslave, &reg4042);
	200	sitre = (reg4042 & 0x4000) ? 1 : 0;
	201	pci_read_config_byte(dev, 0x48, &reg48);
	202	pci_read_config_word(dev, 0x4a, &reg4a);
	203	pci_read_config_byte(dev, 0x54, &reg54);
	204	pci_read_config_byte(dev, 0x55, &reg55);
	205
1da177e4	206	if (speed >= XFER_UDMA_0) {
4db90a14 BZ	207	u8 udma = speed - XFER_UDMA_0;
	208
	209	u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
	210
1da177e4 LT	211	if (!(reg48 & u_flag))
	212	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
	213	if (speed == XFER_UDMA_5) {
	214	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
	215	} else {
	216	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	217	}
	218	if ((reg4a & a_speed) != u_speed)
	219	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
	220	if (speed > XFER_UDMA_2) {
	221	if (!(reg54 & v_flag))
	222	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
	223	} else
	224	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	225	} else {
8c91abf8	226	const u8 mwdma_to_pio[] = { 0, 3, 4 };
1c54a93d	227	u8 pio;
8c91abf8	228
1da177e4 LT	229	if (reg48 & u_flag)
	230	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
	231	if (reg4a & a_speed)
	232	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	233	if (reg54 & v_flag)
	234	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	235	if (reg55 & w_flag)
	236	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
8c91abf8 BZ	237
	238	if (speed >= XFER_MW_DMA_0)
	239	pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
	240	else
	241	pio = 2; /* only SWDMA2 is allowed */
1da177e4	242
1c54a93d BZ	243	piix_set_pio_mode(drive, pio);
1c54a93d BZ	244	}
1da177e4 LT	245	}
1da177e4 LT	246
1da177e4	247	/**
40d2dd7e	248	* init_chipset_ich - set up the ICH chipset
f0dd8712 AL	249	* @dev: PCI device to set up
	250	* @name: Name of the device
	251	*
40d2dd7e BZ	252	* Initialize the PCI device as required. For the ICH this turns
40d2dd7e BZ	253	* out to be nice and simple.
f0dd8712 AL	254	*/
f0dd8712 AL	255
40d2dd7e	256	static unsigned int __devinit init_chipset_ich(struct pci_dev dev, const char name)
f0dd8712	257	{
40d2dd7e BZ	258	u32 extra = 0;
	259
	260	pci_read_config_dword(dev, 0x54, &extra);
	261	pci_write_config_dword(dev, 0x54, extra \| 0x400);
f0dd8712 AL	262
	263	return 0;
	264	}
	265
	266	/**
	267	* piix_dma_clear_irq - clear BMDMA status
	268	* @drive: IDE drive to clear
	269	*
	270	* Called from ide_intr() for PIO interrupts
	271	* to clear BMDMA status as needed by ICHx
	272	*/
	273	static void piix_dma_clear_irq(ide_drive_t *drive)
	274	{
	275	ide_hwif_t *hwif = HWIF(drive);
	276	u8 dma_stat;
	277
	278	/* clear the INTR & ERROR bits */
31e8a465	279	dma_stat = inb(hwif->dma_status);
f0dd8712	280	/* Should we force the bit as well ? */
31e8a465	281	outb(dma_stat, hwif->dma_status);
f0dd8712 AL	282	}
f0dd8712 AL	283
7207626f BZ	284	struct ich_laptop {
	285	u16 device;
	286	u16 subvendor;
	287	u16 subdevice;
	288	};
	289
	290	/*
	291	* List of laptops that use short cables rather than 80 wire
	292	*/
	293
	294	static const struct ich_laptop ich_laptop[] = {
	295	/* devid, subvendor, subdev */
afda5e4d	296	{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
7207626f BZ	297	{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
	298	{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
	299	{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
dd0fd40d	300	{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
7207626f BZ	301	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
	302	/* end marker */
	303	{ 0, }
	304	};
	305
49521f97	306	static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
74594fd1	307	{
7207626f BZ	308	struct pci_dev *pdev = hwif->pci_dev;
7207626f BZ	309	const struct ich_laptop *lap = &ich_laptop[0];
74594fd1 BZ	310	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
74594fd1 BZ	311
7207626f BZ	312	/* check for specials */
	313	while (lap->device) {
	314	if (lap->device == pdev->device &&
	315	lap->subvendor == pdev->subsystem_vendor &&
	316	lap->subdevice == pdev->subsystem_device) {
	317	return ATA_CBL_PATA40_SHORT;
	318	}
	319	lap++;
	320	}
	321
	322	pci_read_config_byte(pdev, 0x54, &reg54h);
74594fd1	323
49521f97	324	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
74594fd1 BZ	325	}
74594fd1 BZ	326
1da177e4 LT	327	/**
	328	* init_hwif_piix - fill in the hwif for the PIIX
	329	* @hwif: IDE interface
	330	*
	331	* Set up the ide_hwif_t for the PIIX interface according to the
	332	* capabilities of the hardware.
	333	*/
	334
	335	static void __devinit init_hwif_piix(ide_hwif_t *hwif)
	336	{
26bcb879	337	hwif->set_pio_mode = &piix_set_pio_mode;
88b2b32b BZ	338	hwif->set_dma_mode = &piix_set_dma_mode;
88b2b32b BZ	339
1da177e4 LT	340	if (!hwif->dma_base)
	341	return;
	342
18137207	343	if (hwif->ultra_mask & 0x78) {
49521f97 BZ	344	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	345	hwif->cbl = piix_cable_detect(hwif);
1da177e4 LT	346	}
1da177e4 LT	347
74594fd1 BZ	348	if (no_piix_dma)
74594fd1 BZ	349	hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
1da177e4 LT	350	}
1da177e4 LT	351
40d2dd7e BZ	352	static void __devinit init_hwif_ich(ide_hwif_t *hwif)
	353	{
	354	init_hwif_piix(hwif);
	355
	356	/* ICHx need to clear the BMDMA status for all interrupts */
	357	if (hwif->dma_base)
	358	hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
	359	}
	360
3985ee3b BZ	361	#ifndef CONFIG_IA64
	362	#define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS \| IDE_HFLAG_BOOTABLE)
	363	#else
	364	#define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
	365	#endif
	366
18137207	367	#define DECLARE_PIIX_DEV(name_str, udma) \
1da177e4 LT	368	{ \
1da177e4 LT	369	.name = name_str, \
1da177e4	370	.init_hwif = init_hwif_piix, \
1da177e4	371	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
3985ee3b	372	.host_flags = IDE_HFLAGS_PIIX, \
4099d143	373	.pio_mask = ATA_PIO4, \
5f8b6c34 BZ	374	.swdma_mask = ATA_SWDMA2_ONLY, \
5f8b6c34 BZ	375	.mwdma_mask = ATA_MWDMA12_ONLY, \
18137207	376	.udma_mask = udma, \
1da177e4 LT	377	}
1da177e4 LT	378
40d2dd7e BZ	379	#define DECLARE_ICH_DEV(name_str, udma) \
	380	{ \
	381	.name = name_str, \
	382	.init_chipset = init_chipset_ich, \
	383	.init_hwif = init_hwif_ich, \
	384	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
3985ee3b	385	.host_flags = IDE_HFLAGS_PIIX, \
40d2dd7e BZ	386	.pio_mask = ATA_PIO4, \
	387	.swdma_mask = ATA_SWDMA2_ONLY, \
	388	.mwdma_mask = ATA_MWDMA12_ONLY, \
	389	.udma_mask = udma, \
	390	}
	391
85620436	392	static const struct ide_port_info piix_pci_info[] __devinitdata = {
5f8b6c34 BZ	393	/* 0 / DECLARE_PIIX_DEV("PIIXa", 0x00), / no udma */
5f8b6c34 BZ	394	/* 1 / DECLARE_PIIX_DEV("PIIXb", 0x00), / no udma */
1da177e4	395
d2872239 SS	396	/* 2 */
	397	{ /*
	398	* MPIIX actually has only a single IDE channel mapped to
	399	* the primary or secondary ports depending on the value
	400	* of the bit 14 of the IDETIM register at offset 0x6c
	401	*/
1da177e4	402	.name = "MPIIX",
d2872239	403	.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
47b68788	404	.host_flags = IDE_HFLAG_ISA_PORTS \| IDE_HFLAG_NO_DMA \|
3985ee3b	405	IDE_HFLAGS_PIIX,
4099d143	406	.pio_mask = ATA_PIO4,
3985ee3b	407	/* This is a painful system best to let it self tune for now */
1da177e4 LT	408	},
1da177e4 LT	409
5f8b6c34 BZ	410	/* 3 / DECLARE_PIIX_DEV("PIIX3", 0x00), / no udma */
5f8b6c34 BZ	411	/* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e	412	/* 5 */ DECLARE_ICH_DEV("ICH0", ATA_UDMA2),
5f8b6c34	413	/* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e	414	/* 7 */ DECLARE_ICH_DEV("ICH", ATA_UDMA4),
5f8b6c34 BZ	415	/* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
5f8b6c34 BZ	416	/* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e BZ	417	/* 10 */ DECLARE_ICH_DEV("ICH2", ATA_UDMA5),
	418	/* 11 */ DECLARE_ICH_DEV("ICH2M", ATA_UDMA5),
	419	/* 12 */ DECLARE_ICH_DEV("ICH3M", ATA_UDMA5),
	420	/* 13 */ DECLARE_ICH_DEV("ICH3", ATA_UDMA5),
	421	/* 14 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	422	/* 15 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
	423	/* 16 */ DECLARE_ICH_DEV("C-ICH", ATA_UDMA5),
	424	/* 17 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	425	/* 18 */ DECLARE_ICH_DEV("ICH5-SATA", ATA_UDMA5),
	426	/* 19 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
	427	/* 20 */ DECLARE_ICH_DEV("ICH6", ATA_UDMA5),
	428	/* 21 */ DECLARE_ICH_DEV("ICH7", ATA_UDMA5),
	429	/* 22 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	430	/* 23 */ DECLARE_ICH_DEV("ESB2", ATA_UDMA5),
	431	/* 24 */ DECLARE_ICH_DEV("ICH8M", ATA_UDMA5),
1da177e4 LT	432	};
	433
	434	/**
	435	* piix_init_one - called when a PIIX is found
	436	* @dev: the piix device
	437	* @id: the matching pci id
	438	*
	439	* Called when the PCI registration layer (or the IDE initialization)
	440	* finds a device matching our IDE device tables.
	441	*/
	442
	443	static int __devinit piix_init_one(struct pci_dev dev, const struct pci_device_id id)
	444	{
039788e1	445	return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
1da177e4 LT	446	}
	447
	448	/**
	449	* piix_check_450nx - Check for problem 450NX setup
	450	*
	451	* Check for the present of 450NX errata #19 and errata #25. If
	452	* they are found, disable use of DMA IDE
	453	*/
	454
	455	static void __devinit piix_check_450nx(void)
	456	{
	457	struct pci_dev *pdev = NULL;
	458	u16 cfg;
1424e504	459	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
1da177e4 LT	460	{
	461	/* Look for 450NX PXB. Check for problem configurations
	462	A PCI quirk checks bit 6 already */
1da177e4 LT	463	pci_read_config_word(pdev, 0x41, &cfg);
1da177e4 LT	464	/* Only on the original revision: IDE DMA can hang */
44c10138	465	if (pdev->revision == 0x00)
1da177e4 LT	466	no_piix_dma = 1;
1da177e4 LT	467	/* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138	468	else if (cfg & (1<<14) && pdev->revision < 5)
1da177e4 LT	469	no_piix_dma = 2;
	470	}
	471	if(no_piix_dma)
	472	printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	473	if(no_piix_dma == 2)
	474	printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
	475	}
	476
9cbcc5e3 BZ	477	static const struct pci_device_id piix_pci_tbl[] = {
	478	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 0 },
	479	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
	480	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 2 },
	481	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 3 },
	482	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 4 },
	483	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 5 },
	484	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 6 },
	485	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 7 },
	486	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 8 },
	487	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 9 },
	488	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 10 },
	489	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 11 },
	490	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	491	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	492	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	493	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	494	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 16 },
	495	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
1da177e4	496	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	497	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 18 },
1da177e4	498	#endif
9cbcc5e3 BZ	499	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 19 },
	500	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 20 },
	501	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 21 },
	502	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 22 },
	503	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 23 },
	504	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 24 },
1da177e4 LT	505	{ 0, },
	506	};
	507	MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
	508
	509	static struct pci_driver driver = {
	510	.name = "PIIX_IDE",
	511	.id_table = piix_pci_tbl,
	512	.probe = piix_init_one,
	513	};
	514
	515	static int __init piix_ide_init(void)
	516	{
	517	piix_check_450nx();
	518	return ide_pci_register_driver(&driver);
	519	}
	520
	521	module_init(piix_ide_init);
	522
	523	MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
	524	MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
	525	MODULE_LICENSE("GPL");