[deliverable/linux.git] / drivers / ide / pci / piix.c

/*
 *  linux/drivers/ide/pci/piix.c	Version 0.54	Sep 5, 2007
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  PIO mode setting function for Intel chipsets.
 *  For use instead of BIOS settings.
 *
 * 40-41
 * 42-43
 * 
 *                 41
 *                 43
 *
 * | PIO 0       | c0 | 80 | 0 |
 * | PIO 2 | SW2 | d0 | 90 | 4 |
 * | PIO 3 | MW1 | e1 | a1 | 9 |
 * | PIO 4 | MW2 | e3 | a3 | b |
 *
 * sitre = word40 & 0x4000; primary
 * sitre = word42 & 0x4000; secondary
 *
 * 44 8421|8421    hdd|hdb
 *
 * 48 8421         hdd|hdc|hdb|hda udma enabled
 *
 *    0001         hda
 *    0010         hdb
 *    0100         hdc
 *    1000         hdd
 *
 * 4a 84|21        hdb|hda
 * 4b 84|21        hdd|hdc
 *
 *    ata-33/82371AB
 *    ata-33/82371EB
 *    ata-33/82801AB            ata-66/82801AA
 *    00|00 udma 0              00|00 reserved
 *    01|01 udma 1              01|01 udma 3
 *    10|10 udma 2              10|10 udma 4
 *    11|11 reserved            11|11 reserved
 *
 * 54 8421|8421    ata66 drive|ata66 enable
 *
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
 *
 * Documentation
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
 * driver the list of errata that are relevant is below.going back to
 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

static int no_piix_dma;

/**
 *	piix_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode based upon the settings done by AMI BIOS.
 */

static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	static DEFINE_SPINLOCK(tune_lock);
	int control = 0;

				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	/*
	 * Master vs slave is synchronized above us but the slave register is
	 * shared by the two hwifs so the corner case of two slave timeouts in
	 * parallel must be locked.
	 */
	spin_lock_irqsave(&tune_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&tune_lock, flags);
}

/**
 *	piix_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a PIIX host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int a_speed		= 3 << (drive->dn * 4);
	int u_flag		= 1 << drive->dn;
	int v_flag		= 0x01 << drive->dn;
	int w_flag		= 0x10 << drive->dn;
	int u_speed		= 0;
	int			sitre;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	switch(speed) {
		case XFER_UDMA_4:
		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
		case XFER_UDMA_5:
		case XFER_UDMA_3:
		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_SW_DMA_2:	break;
		default:		return;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed == XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}
		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };
		u8 pio;

		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);

		if (speed >= XFER_MW_DMA_0)
			pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
		else
			pio = 2; /* only SWDMA2 is allowed */

		piix_set_pio_mode(drive, pio);
	}
}

/**
 *	piix_is_ichx	-	check if ICHx
 *	@dev: PCI device to check
 *
 *	returns 1 if ICHx, 0 otherwise.
 */
static int piix_is_ichx(struct pci_dev *dev)
{
        switch (dev->device) {
		case PCI_DEVICE_ID_INTEL_82801EB_1:
		case PCI_DEVICE_ID_INTEL_82801AA_1:
		case PCI_DEVICE_ID_INTEL_82801AB_1:
		case PCI_DEVICE_ID_INTEL_82801BA_8:
		case PCI_DEVICE_ID_INTEL_82801BA_9:
		case PCI_DEVICE_ID_INTEL_82801CA_10:
		case PCI_DEVICE_ID_INTEL_82801CA_11:
		case PCI_DEVICE_ID_INTEL_82801DB_1:
		case PCI_DEVICE_ID_INTEL_82801DB_10:
		case PCI_DEVICE_ID_INTEL_82801DB_11:
		case PCI_DEVICE_ID_INTEL_82801EB_11:
		case PCI_DEVICE_ID_INTEL_82801E_11:
		case PCI_DEVICE_ID_INTEL_ESB_2:
		case PCI_DEVICE_ID_INTEL_ICH6_19:
		case PCI_DEVICE_ID_INTEL_ICH7_21:
		case PCI_DEVICE_ID_INTEL_ESB2_18:
		case PCI_DEVICE_ID_INTEL_ICH8_6:
			return 1;
	}

	return 0;
}

/**
 *	init_chipset_piix	-	set up the PIIX chipset
 *	@dev: PCI device to set up
 *	@name: Name of the device
 *
 *	Initialize the PCI device as required. For the PIIX this turns
 *	out to be nice and simple
 */

static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
{
	if (piix_is_ichx(dev)) {
		unsigned int extra = 0;
		pci_read_config_dword(dev, 0x54, &extra);
		pci_write_config_dword(dev, 0x54, extra|0x400);
	}

	return 0;
}

/**
 *	piix_dma_clear_irq	-	clear BMDMA status
 *	@drive: IDE drive to clear
 *
 *	Called from ide_intr() for PIO interrupts
 *	to clear BMDMA status as needed by ICHx
 */
static void piix_dma_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	u8 dma_stat;

	/* clear the INTR & ERROR bits */
	dma_stat = inb(hwif->dma_status);
	/* Should we force the bit as well ? */
	outb(dma_stat, hwif->dma_status);
}

struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on Acer Aspire 2023WLMi */
	/* end marker */
	{ 0, }
};

static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = hwif->pci_dev;
	const struct ich_laptop *lap = &ich_laptop[0];
	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;

	/* check for specials */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
		    lap->subdevice == pdev->subsystem_device) {
			return ATA_CBL_PATA40_SHORT;
		}
		lap++;
	}

	pci_read_config_byte(pdev, 0x54, &reg54h);

	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/**
 *	init_hwif_piix		-	fill in the hwif for the PIIX
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the PIIX interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_piix(ide_hwif_t *hwif)
{
#ifndef CONFIG_IA64
	if (!hwif->irq)
		hwif->irq = hwif->channel ? 15 : 14;
#endif /* CONFIG_IA64 */

	if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
		/* This is a painful system best to let it self tune for now */
		return;
	}

	hwif->set_pio_mode = &piix_set_pio_mode;
	hwif->set_dma_mode = &piix_set_dma_mode;

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	/* ICHx need to clear the bmdma status for all interrupts */
	if (piix_is_ichx(hwif->pci_dev))
		hwif->ide_dma_clear_irq = &piix_dma_clear_irq;

	if (hwif->ultra_mask & 0x78) {
		if (hwif->cbl != ATA_CBL_PATA40_SHORT)
			hwif->cbl = piix_cable_detect(hwif);
	}

	if (no_piix_dma)
		hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
}

#define DECLARE_PIIX_DEV(name_str, udma) \
	{						\
		.name		= name_str,		\
		.init_chipset	= init_chipset_piix,	\
		.init_hwif	= init_hwif_piix,	\
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.host_flags	= IDE_HFLAG_BOOTABLE,	\
		.pio_mask	= ATA_PIO4,		\
		.swdma_mask	= ATA_SWDMA2_ONLY,	\
		.mwdma_mask	= ATA_MWDMA12_ONLY,	\
		.udma_mask	= udma,			\
	}

static ide_pci_device_t piix_pci_info[] __devinitdata = {
	/*  0 */ DECLARE_PIIX_DEV("PIIXa",	0x00),	/* no udma */
	/*  1 */ DECLARE_PIIX_DEV("PIIXb",	0x00),	/* no udma */

	/*  2 */
	{	/*
		 * MPIIX actually has only a single IDE channel mapped to
		 * the primary or secondary ports depending on the value
		 * of the bit 14 of the IDETIM register at offset 0x6c
		 */
		.name		= "MPIIX",
		.init_hwif	= init_hwif_piix,
		.enablebits	= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
		.host_flags	= IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
				  IDE_HFLAG_BOOTABLE,
		.pio_mask	= ATA_PIO4,
	},

	/*  3 */ DECLARE_PIIX_DEV("PIIX3",	0x00),	/* no udma */
	/*  4 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  5 */ DECLARE_PIIX_DEV("ICH0",	ATA_UDMA2),
	/*  6 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  7 */ DECLARE_PIIX_DEV("ICH",	ATA_UDMA4),
	/*  8 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA4),
	/*  9 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/* 10 */ DECLARE_PIIX_DEV("ICH2",	ATA_UDMA5),
	/* 11 */ DECLARE_PIIX_DEV("ICH2M",	ATA_UDMA5),
	/* 12 */ DECLARE_PIIX_DEV("ICH3M",	ATA_UDMA5),
	/* 13 */ DECLARE_PIIX_DEV("ICH3",	ATA_UDMA5),
	/* 14 */ DECLARE_PIIX_DEV("ICH4",	ATA_UDMA5),
	/* 15 */ DECLARE_PIIX_DEV("ICH5",	ATA_UDMA5),
	/* 16 */ DECLARE_PIIX_DEV("C-ICH",	ATA_UDMA5),
	/* 17 */ DECLARE_PIIX_DEV("ICH4",	ATA_UDMA5),
	/* 18 */ DECLARE_PIIX_DEV("ICH5-SATA",	ATA_UDMA5),
	/* 19 */ DECLARE_PIIX_DEV("ICH5",	ATA_UDMA5),
	/* 20 */ DECLARE_PIIX_DEV("ICH6",	ATA_UDMA5),
	/* 21 */ DECLARE_PIIX_DEV("ICH7",	ATA_UDMA5),
	/* 22 */ DECLARE_PIIX_DEV("ICH4",	ATA_UDMA5),
	/* 23 */ DECLARE_PIIX_DEV("ESB2",	ATA_UDMA5),
	/* 24 */ DECLARE_PIIX_DEV("ICH8M",	ATA_UDMA5),
};

/**
 *	piix_init_one	-	called when a PIIX is found
 *	@dev: the piix device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &piix_pci_info[id->driver_data];

	return ide_setup_pci_device(dev, d);
}

/**
 *	piix_check_450nx	-	Check for problem 450NX setup
 *	
 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found, disable use of DMA IDE
 */

static void __devinit piix_check_450nx(void)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
	{
		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
		if (pdev->revision == 0x00)
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
		else if (cfg & (1<<14) && pdev->revision < 5)
			no_piix_dma = 2;
	}
	if(no_piix_dma)
		printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	if(no_piix_dma == 2)
		printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
}		

static const struct pci_device_id piix_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
#endif
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);

static struct pci_driver driver = {
	.name		= "PIIX_IDE",
	.id_table	= piix_pci_tbl,
	.probe		= piix_init_one,
};

static int __init piix_ide_init(void)
{
	piix_check_450nx();
	return ide_pci_register_driver(&driver);
}

module_init(piix_ide_init);

MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
31e8a465	2	* linux/drivers/ide/pci/piix.c Version 0.54 Sep 5, 2007
1da177e4 LT	3	*
	4	* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
	5	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	6	* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
07af4276	7	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	8	*
	9	* May be copied or modified under the terms of the GNU General Public License
	10	*
44854add	11	* PIO mode setting function for Intel chipsets.
1da177e4 LT	12	* For use instead of BIOS settings.
	13	*
	14	* 40-41
	15	* 42-43
	16	*
	17	* 41
	18	* 43
	19	*
26bcb879 BZ	20	* \| PIO 0 \| c0 \| 80 \| 0 \|
	21	* \| PIO 2 \| SW2 \| d0 \| 90 \| 4 \|
	22	* \| PIO 3 \| MW1 \| e1 \| a1 \| 9 \|
	23	* \| PIO 4 \| MW2 \| e3 \| a3 \| b \|
	24	*
1da177e4 LT	25	* sitre = word40 & 0x4000; primary
	26	* sitre = word42 & 0x4000; secondary
	27	*
	28	* 44 8421\|8421 hdd\|hdb
44854add	29	*
1da177e4 LT	30	* 48 8421 hdd\|hdc\|hdb\|hda udma enabled
	31	*
	32	* 0001 hda
	33	* 0010 hdb
	34	* 0100 hdc
	35	* 1000 hdd
	36	*
	37	* 4a 84\|21 hdb\|hda
	38	* 4b 84\|21 hdd\|hdc
	39	*
	40	* ata-33/82371AB
	41	* ata-33/82371EB
	42	* ata-33/82801AB ata-66/82801AA
	43	* 00\|00 udma 0 00\|00 reserved
	44	* 01\|01 udma 1 01\|01 udma 3
	45	* 10\|10 udma 2 10\|10 udma 4
	46	* 11\|11 reserved 11\|11 reserved
	47	*
	48	* 54 8421\|8421 ata66 drive\|ata66 enable
	49	*
	50	* pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
	51	* pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
	52	* pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
	53	* pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
	54	* pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
	55	* pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
	56	*
	57	* Documentation
	58	* Publically available from Intel web site. Errata documentation
	59	* is also publically available. As an aide to anyone hacking on this
	60	* driver the list of errata that are relevant is below.going back to
	61	* PIIX4. Older device documentation is now a bit tricky to find.
	62	*
	63	* Errata of note:
	64	*
	65	* Unfixable
	66	* PIIX4 errata #9 - Only on ultra obscure hw
	67	* ICH3 errata #13 - Not observed to affect real hw
	68	* by Intel
	69	*
	70	* Things we must deal with
	71	* PIIX4 errata #10 - BM IDE hang with non UDMA
	72	* (must stop/start dma to recover)
	73	* 440MX errata #15 - As PIIX4 errata #10
	74	* PIIX4 errata #15 - Must not read control registers
	75	* during a PIO transfer
	76	* 440MX errata #13 - As PIIX4 errata #15
	77	* ICH2 errata #21 - DMA mode 0 doesn't work right
	78	* ICH0/1 errata #55 - As ICH2 errata #21
	79	* ICH2 spec c #9 - Extra operations needed to handle
	80	* drive hotswap [NOT YET SUPPORTED]
	81	* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
	82	* and must be dword aligned
	83	* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
	84	*
	85	* Should have been BIOS fixed:
	86	* 450NX: errata #19 - DMA hangs on old 450NX
	87	* 450NX: errata #20 - DMA hangs on old 450NX
	88	* 450NX: errata #25 - Corruption with DMA on old 450NX
	89	* ICH3 errata #15 - IDE deadlock under high load
	90	* (BIOS must set dev 31 fn 0 bit 23)
	91	* ICH3 errata #18 - Don't use native mode
	92	*/
	93
1da177e4 LT	94	#include <linux/types.h>
	95	#include <linux/module.h>
	96	#include <linux/kernel.h>
	97	#include <linux/ioport.h>
	98	#include <linux/pci.h>
	99	#include <linux/hdreg.h>
	100	#include <linux/ide.h>
	101	#include <linux/delay.h>
	102	#include <linux/init.h>
	103
	104	#include <asm/io.h>
	105
	106	static int no_piix_dma;
	107
1da177e4	108	/**
88b2b32b BZ	109	* piix_set_pio_mode - set host controller for PIO mode
	110	* @drive: drive
	111	* @pio: PIO mode number
1da177e4	112	*
07af4276	113	* Set the interface PIO mode based upon the settings done by AMI BIOS.
1da177e4	114	*/
88b2b32b BZ	115
88b2b32b BZ	116	static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	117	{
	118	ide_hwif_t *hwif = HWIF(drive);
	119	struct pci_dev *dev = hwif->pci_dev;
30dfd12f	120	int is_slave = drive->dn & 1;
1da177e4 LT	121	int master_port = hwif->channel ? 0x42 : 0x40;
	122	int slave_port = 0x44;
	123	unsigned long flags;
	124	u16 master_data;
	125	u8 slave_data;
4fb0f76d	126	static DEFINE_SPINLOCK(tune_lock);
5ac24697	127	int control = 0;
4fb0f76d	128
30dfd12f	129	/* ISP RTC */
5ac24697 AC	130	static const u8 timings[][2]= {
	131	{ 0, 0 },
	132	{ 0, 0 },
	133	{ 1, 0 },
	134	{ 2, 1 },
	135	{ 2, 3 }, };
1da177e4	136
4fb0f76d AC	137	/*
	138	* Master vs slave is synchronized above us but the slave register is
	139	* shared by the two hwifs so the corner case of two slave timeouts in
	140	* parallel must be locked.
	141	*/
	142	spin_lock_irqsave(&tune_lock, flags);
1da177e4	143	pci_read_config_word(dev, master_port, &master_data);
5ac24697	144
30dfd12f	145	if (pio > 1)
5ac24697 AC	146	control \|= 1; /* Programmable timing on */
	147	if (drive->media == ide_disk)
	148	control \|= 4; /* Prefetch, post write */
30dfd12f	149	if (pio > 2)
5ac24697	150	control \|= 2; /* IORDY */
1da177e4	151	if (is_slave) {
30dfd12f SS	152	master_data \|= 0x4000;
30dfd12f SS	153	master_data &= ~0x0070;
5ac24697	154	if (pio > 1) {
07af4276 SS	155	/* Set PPE, IE and TIME */
07af4276 SS	156	master_data \|= control << 4;
5ac24697	157	}
1da177e4	158	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	159	slave_data &= hwif->channel ? 0x0f : 0xf0;
	160	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	161	(hwif->channel ? 4 : 0);
1da177e4	162	} else {
30dfd12f	163	master_data &= ~0x3307;
5ac24697	164	if (pio > 1) {
1da177e4	165	/* enable PPE, IE and TIME */
07af4276	166	master_data \|= control;
5ac24697	167	}
07af4276	168	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	169	}
	170	pci_write_config_word(dev, master_port, master_data);
	171	if (is_slave)
	172	pci_write_config_byte(dev, slave_port, slave_data);
4fb0f76d	173	spin_unlock_irqrestore(&tune_lock, flags);
1da177e4 LT	174	}
1da177e4 LT	175
07af4276	176	/**
88b2b32b BZ	177	* piix_set_dma_mode - set host controller for DMA mode
	178	* @drive: drive
	179	* @speed: DMA mode
1da177e4	180	*
88b2b32b BZ	181	* Set a PIIX host controller to the desired DMA mode. This involves
88b2b32b BZ	182	* programming the right timing data into the PCI configuration space.
1da177e4	183	*/
f212ff28	184
88b2b32b	185	static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	186	{
	187	ide_hwif_t *hwif = HWIF(drive);
	188	struct pci_dev *dev = hwif->pci_dev;
	189	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	190	int a_speed = 3 << (drive->dn * 4);
	191	int u_flag = 1 << drive->dn;
	192	int v_flag = 0x01 << drive->dn;
	193	int w_flag = 0x10 << drive->dn;
	194	int u_speed = 0;
	195	int sitre;
	196	u16 reg4042, reg4a;
1c54a93d	197	u8 reg48, reg54, reg55;
1da177e4 LT	198
	199	pci_read_config_word(dev, maslave, &reg4042);
	200	sitre = (reg4042 & 0x4000) ? 1 : 0;
	201	pci_read_config_byte(dev, 0x48, &reg48);
	202	pci_read_config_word(dev, 0x4a, &reg4a);
	203	pci_read_config_byte(dev, 0x54, &reg54);
	204	pci_read_config_byte(dev, 0x55, &reg55);
	205
	206	switch(speed) {
	207	case XFER_UDMA_4:
	208	case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
	209	case XFER_UDMA_5:
	210	case XFER_UDMA_3:
	211	case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
	212	case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
	213	case XFER_MW_DMA_2:
	214	case XFER_MW_DMA_1:
	215	case XFER_SW_DMA_2: break;
88b2b32b	216	default: return;
1da177e4 LT	217	}
	218
	219	if (speed >= XFER_UDMA_0) {
	220	if (!(reg48 & u_flag))
	221	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
	222	if (speed == XFER_UDMA_5) {
	223	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
	224	} else {
	225	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	226	}
	227	if ((reg4a & a_speed) != u_speed)
	228	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
	229	if (speed > XFER_UDMA_2) {
	230	if (!(reg54 & v_flag))
	231	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
	232	} else
	233	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	234	} else {
8c91abf8	235	const u8 mwdma_to_pio[] = { 0, 3, 4 };
1c54a93d	236	u8 pio;
8c91abf8	237
1da177e4 LT	238	if (reg48 & u_flag)
	239	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
	240	if (reg4a & a_speed)
	241	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	242	if (reg54 & v_flag)
	243	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	244	if (reg55 & w_flag)
	245	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
8c91abf8 BZ	246
	247	if (speed >= XFER_MW_DMA_0)
	248	pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
	249	else
	250	pio = 2; /* only SWDMA2 is allowed */
1da177e4	251
1c54a93d BZ	252	piix_set_pio_mode(drive, pio);
1c54a93d BZ	253	}
1da177e4 LT	254	}
1da177e4 LT	255
1da177e4	256	/**
f0dd8712 AL	257	* piix_is_ichx - check if ICHx
f0dd8712 AL	258	* @dev: PCI device to check
1da177e4	259	*
f0dd8712	260	* returns 1 if ICHx, 0 otherwise.
1da177e4	261	*/
f0dd8712	262	static int piix_is_ichx(struct pci_dev *dev)
1da177e4	263	{
f0dd8712	264	switch (dev->device) {
1da177e4 LT	265	case PCI_DEVICE_ID_INTEL_82801EB_1:
	266	case PCI_DEVICE_ID_INTEL_82801AA_1:
	267	case PCI_DEVICE_ID_INTEL_82801AB_1:
	268	case PCI_DEVICE_ID_INTEL_82801BA_8:
	269	case PCI_DEVICE_ID_INTEL_82801BA_9:
	270	case PCI_DEVICE_ID_INTEL_82801CA_10:
	271	case PCI_DEVICE_ID_INTEL_82801CA_11:
	272	case PCI_DEVICE_ID_INTEL_82801DB_1:
	273	case PCI_DEVICE_ID_INTEL_82801DB_10:
	274	case PCI_DEVICE_ID_INTEL_82801DB_11:
	275	case PCI_DEVICE_ID_INTEL_82801EB_11:
	276	case PCI_DEVICE_ID_INTEL_82801E_11:
	277	case PCI_DEVICE_ID_INTEL_ESB_2:
	278	case PCI_DEVICE_ID_INTEL_ICH6_19:
	279	case PCI_DEVICE_ID_INTEL_ICH7_21:
d69332b8	280	case PCI_DEVICE_ID_INTEL_ESB2_18:
b7bed9ec	281	case PCI_DEVICE_ID_INTEL_ICH8_6:
f0dd8712	282	return 1;
1da177e4 LT	283	}
	284
	285	return 0;
	286	}
	287
f0dd8712 AL	288	/**
	289	* init_chipset_piix - set up the PIIX chipset
	290	* @dev: PCI device to set up
	291	* @name: Name of the device
	292	*
	293	* Initialize the PCI device as required. For the PIIX this turns
	294	* out to be nice and simple
	295	*/
	296
	297	static unsigned int __devinit init_chipset_piix (struct pci_dev dev, const char name)
	298	{
	299	if (piix_is_ichx(dev)) {
	300	unsigned int extra = 0;
	301	pci_read_config_dword(dev, 0x54, &extra);
	302	pci_write_config_dword(dev, 0x54, extra\|0x400);
	303	}
	304
	305	return 0;
	306	}
	307
	308	/**
	309	* piix_dma_clear_irq - clear BMDMA status
	310	* @drive: IDE drive to clear
	311	*
	312	* Called from ide_intr() for PIO interrupts
	313	* to clear BMDMA status as needed by ICHx
	314	*/
	315	static void piix_dma_clear_irq(ide_drive_t *drive)
	316	{
	317	ide_hwif_t *hwif = HWIF(drive);
	318	u8 dma_stat;
	319
	320	/* clear the INTR & ERROR bits */
31e8a465	321	dma_stat = inb(hwif->dma_status);
f0dd8712	322	/* Should we force the bit as well ? */
31e8a465	323	outb(dma_stat, hwif->dma_status);
f0dd8712 AL	324	}
f0dd8712 AL	325
7207626f BZ	326	struct ich_laptop {
	327	u16 device;
	328	u16 subvendor;
	329	u16 subdevice;
	330	};
	331
	332	/*
	333	* List of laptops that use short cables rather than 80 wire
	334	*/
	335
	336	static const struct ich_laptop ich_laptop[] = {
	337	/* devid, subvendor, subdev */
	338	{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
	339	{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
	340	{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
	341	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
	342	/* end marker */
	343	{ 0, }
	344	};
	345
49521f97	346	static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
74594fd1	347	{
7207626f BZ	348	struct pci_dev *pdev = hwif->pci_dev;
7207626f BZ	349	const struct ich_laptop *lap = &ich_laptop[0];
74594fd1 BZ	350	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
74594fd1 BZ	351
7207626f BZ	352	/* check for specials */
	353	while (lap->device) {
	354	if (lap->device == pdev->device &&
	355	lap->subvendor == pdev->subsystem_vendor &&
	356	lap->subdevice == pdev->subsystem_device) {
	357	return ATA_CBL_PATA40_SHORT;
	358	}
	359	lap++;
	360	}
	361
	362	pci_read_config_byte(pdev, 0x54, &reg54h);
74594fd1	363
49521f97	364	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
74594fd1 BZ	365	}
74594fd1 BZ	366
1da177e4 LT	367	/**
	368	* init_hwif_piix - fill in the hwif for the PIIX
	369	* @hwif: IDE interface
	370	*
	371	* Set up the ide_hwif_t for the PIIX interface according to the
	372	* capabilities of the hardware.
	373	*/
	374
	375	static void __devinit init_hwif_piix(ide_hwif_t *hwif)
	376	{
1da177e4 LT	377	#ifndef CONFIG_IA64
	378	if (!hwif->irq)
	379	hwif->irq = hwif->channel ? 15 : 14;
	380	#endif /* CONFIG_IA64 */
	381
	382	if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
	383	/* This is a painful system best to let it self tune for now */
	384	return;
	385	}
	386
26bcb879	387	hwif->set_pio_mode = &piix_set_pio_mode;
88b2b32b BZ	388	hwif->set_dma_mode = &piix_set_dma_mode;
88b2b32b BZ	389
1da177e4 LT	390	hwif->drives[0].autotune = 1;
	391	hwif->drives[1].autotune = 1;
	392
	393	if (!hwif->dma_base)
	394	return;
	395
f0dd8712 AL	396	/* ICHx need to clear the bmdma status for all interrupts */
	397	if (piix_is_ichx(hwif->pci_dev))
	398	hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
	399
18137207	400	if (hwif->ultra_mask & 0x78) {
49521f97 BZ	401	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	402	hwif->cbl = piix_cable_detect(hwif);
1da177e4 LT	403	}
1da177e4 LT	404
74594fd1 BZ	405	if (no_piix_dma)
74594fd1 BZ	406	hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
1da177e4 LT	407	}
1da177e4 LT	408
18137207	409	#define DECLARE_PIIX_DEV(name_str, udma) \
1da177e4 LT	410	{ \
	411	.name = name_str, \
	412	.init_chipset = init_chipset_piix, \
	413	.init_hwif = init_hwif_piix, \
1da177e4	414	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
7cab14a7	415	.host_flags = IDE_HFLAG_BOOTABLE, \
4099d143	416	.pio_mask = ATA_PIO4, \
5f8b6c34 BZ	417	.swdma_mask = ATA_SWDMA2_ONLY, \
5f8b6c34 BZ	418	.mwdma_mask = ATA_MWDMA12_ONLY, \
18137207	419	.udma_mask = udma, \
1da177e4 LT	420	}
	421
	422	static ide_pci_device_t piix_pci_info[] __devinitdata = {
5f8b6c34 BZ	423	/* 0 / DECLARE_PIIX_DEV("PIIXa", 0x00), / no udma */
5f8b6c34 BZ	424	/* 1 / DECLARE_PIIX_DEV("PIIXb", 0x00), / no udma */
1da177e4	425
d2872239 SS	426	/* 2 */
	427	{ /*
	428	* MPIIX actually has only a single IDE channel mapped to
	429	* the primary or secondary ports depending on the value
	430	* of the bit 14 of the IDETIM register at offset 0x6c
	431	*/
1da177e4 LT	432	.name = "MPIIX",
1da177e4 LT	433	.init_hwif = init_hwif_piix,
d2872239	434	.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
47b68788 BZ	435	.host_flags = IDE_HFLAG_ISA_PORTS \| IDE_HFLAG_NO_DMA \|
47b68788 BZ	436	IDE_HFLAG_BOOTABLE,
4099d143	437	.pio_mask = ATA_PIO4,
1da177e4 LT	438	},
1da177e4 LT	439
5f8b6c34 BZ	440	/* 3 / DECLARE_PIIX_DEV("PIIX3", 0x00), / no udma */
	441	/* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
	442	/* 5 */ DECLARE_PIIX_DEV("ICH0", ATA_UDMA2),
	443	/* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
	444	/* 7 */ DECLARE_PIIX_DEV("ICH", ATA_UDMA4),
	445	/* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
	446	/* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
	447	/* 10 */ DECLARE_PIIX_DEV("ICH2", ATA_UDMA5),
	448	/* 11 */ DECLARE_PIIX_DEV("ICH2M", ATA_UDMA5),
	449	/* 12 */ DECLARE_PIIX_DEV("ICH3M", ATA_UDMA5),
	450	/* 13 */ DECLARE_PIIX_DEV("ICH3", ATA_UDMA5),
	451	/* 14 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
	452	/* 15 */ DECLARE_PIIX_DEV("ICH5", ATA_UDMA5),
	453	/* 16 */ DECLARE_PIIX_DEV("C-ICH", ATA_UDMA5),
	454	/* 17 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
	455	/* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", ATA_UDMA5),
	456	/* 19 */ DECLARE_PIIX_DEV("ICH5", ATA_UDMA5),
	457	/* 20 */ DECLARE_PIIX_DEV("ICH6", ATA_UDMA5),
	458	/* 21 */ DECLARE_PIIX_DEV("ICH7", ATA_UDMA5),
	459	/* 22 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
	460	/* 23 */ DECLARE_PIIX_DEV("ESB2", ATA_UDMA5),
	461	/* 24 */ DECLARE_PIIX_DEV("ICH8M", ATA_UDMA5),
1da177e4 LT	462	};
	463
	464	/**
	465	* piix_init_one - called when a PIIX is found
	466	* @dev: the piix device
	467	* @id: the matching pci id
	468	*
	469	* Called when the PCI registration layer (or the IDE initialization)
	470	* finds a device matching our IDE device tables.
	471	*/
	472
	473	static int __devinit piix_init_one(struct pci_dev dev, const struct pci_device_id id)
	474	{
	475	ide_pci_device_t *d = &piix_pci_info[id->driver_data];
	476
	477	return ide_setup_pci_device(dev, d);
	478	}
	479
	480	/**
	481	* piix_check_450nx - Check for problem 450NX setup
	482	*
	483	* Check for the present of 450NX errata #19 and errata #25. If
	484	* they are found, disable use of DMA IDE
	485	*/
	486
	487	static void __devinit piix_check_450nx(void)
	488	{
	489	struct pci_dev *pdev = NULL;
	490	u16 cfg;
1424e504	491	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
1da177e4 LT	492	{
	493	/* Look for 450NX PXB. Check for problem configurations
	494	A PCI quirk checks bit 6 already */
1da177e4 LT	495	pci_read_config_word(pdev, 0x41, &cfg);
1da177e4 LT	496	/* Only on the original revision: IDE DMA can hang */
44c10138	497	if (pdev->revision == 0x00)
1da177e4 LT	498	no_piix_dma = 1;
1da177e4 LT	499	/* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138	500	else if (cfg & (1<<14) && pdev->revision < 5)
1da177e4 LT	501	no_piix_dma = 2;
	502	}
	503	if(no_piix_dma)
	504	printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	505	if(no_piix_dma == 2)
	506	printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
	507	}
	508
9cbcc5e3 BZ	509	static const struct pci_device_id piix_pci_tbl[] = {
	510	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 0 },
	511	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
	512	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 2 },
	513	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 3 },
	514	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 4 },
	515	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 5 },
	516	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 6 },
	517	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 7 },
	518	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 8 },
	519	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 9 },
	520	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 10 },
	521	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 11 },
	522	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	523	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	524	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	525	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	526	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 16 },
	527	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
1da177e4	528	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	529	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 18 },
1da177e4	530	#endif
9cbcc5e3 BZ	531	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 19 },
	532	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 20 },
	533	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 21 },
	534	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 22 },
	535	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 23 },
	536	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 24 },
1da177e4 LT	537	{ 0, },
	538	};
	539	MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
	540
	541	static struct pci_driver driver = {
	542	.name = "PIIX_IDE",
	543	.id_table = piix_pci_tbl,
	544	.probe = piix_init_one,
	545	};
	546
	547	static int __init piix_ide_init(void)
	548	{
	549	piix_check_450nx();
	550	return ide_pci_register_driver(&driver);
	551	}
	552
	553	module_init(piix_ide_init);
	554
	555	MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
	556	MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
	557	MODULE_LICENSE("GPL");