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ide: Kconfig face-lift
[deliverable/linux.git] / drivers / ide / pci / piix.c
CommitLineData
1da177e4 1/*
0c8de52d 2 * linux/drivers/ide/pci/piix.c Version 0.51 Jul 6, 2007
1da177e4
LT		 3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
07af4276 7 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 8 *
9 * May be copied or modified under the terms of the GNU General Public License
10 *
44854add 11 * PIO mode setting function for Intel chipsets.
1da177e4
LT		 12 * For use instead of BIOS settings.
13 *
14 * 40-41
15 * 42-43
16 *
17 * 41
18 * 43
19 *
20 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
21 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
22 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
23 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
24 *
25 * sitre = word40 & 0x4000; primary
26 * sitre = word42 & 0x4000; secondary
27 *
28 * 44 8421|8421 hdd|hdb
44854add 29 *
1da177e4
LT		 30 * 48 8421 hdd|hdc|hdb|hda udma enabled
31 *
32 * 0001 hda
33 * 0010 hdb
34 * 0100 hdc
35 * 1000 hdd
36 *
37 * 4a 84|21 hdb|hda
38 * 4b 84|21 hdd|hdc
39 *
40 * ata-33/82371AB
41 * ata-33/82371EB
42 * ata-33/82801AB ata-66/82801AA
43 * 00|00 udma 0 00|00 reserved
44 * 01|01 udma 1 01|01 udma 3
45 * 10|10 udma 2 10|10 udma 4
46 * 11|11 reserved 11|11 reserved
47 *
48 * 54 8421|8421 ata66 drive|ata66 enable
49 *
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
56 *
57 * Documentation
58 * Publically available from Intel web site. Errata documentation
59 * is also publically available. As an aide to anyone hacking on this
60 * driver the list of errata that are relevant is below.going back to
61 * PIIX4. Older device documentation is now a bit tricky to find.
62 *
63 * Errata of note:
64 *
65 * Unfixable
66 * PIIX4 errata #9 - Only on ultra obscure hw
67 * ICH3 errata #13 - Not observed to affect real hw
68 * by Intel
69 *
70 * Things we must deal with
71 * PIIX4 errata #10 - BM IDE hang with non UDMA
72 * (must stop/start dma to recover)
73 * 440MX errata #15 - As PIIX4 errata #10
74 * PIIX4 errata #15 - Must not read control registers
75 * during a PIO transfer
76 * 440MX errata #13 - As PIIX4 errata #15
77 * ICH2 errata #21 - DMA mode 0 doesn't work right
78 * ICH0/1 errata #55 - As ICH2 errata #21
79 * ICH2 spec c #9 - Extra operations needed to handle
80 * drive hotswap [NOT YET SUPPORTED]
81 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
82 * and must be dword aligned
83 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
84 *
85 * Should have been BIOS fixed:
86 * 450NX: errata #19 - DMA hangs on old 450NX
87 * 450NX: errata #20 - DMA hangs on old 450NX
88 * 450NX: errata #25 - Corruption with DMA on old 450NX
89 * ICH3 errata #15 - IDE deadlock under high load
90 * (BIOS must set dev 31 fn 0 bit 23)
91 * ICH3 errata #18 - Don't use native mode
92 */
93
1da177e4
LT		 94#include <linux/types.h>
95#include <linux/module.h>
96#include <linux/kernel.h>
97#include <linux/ioport.h>
98#include <linux/pci.h>
99#include <linux/hdreg.h>
100#include <linux/ide.h>
101#include <linux/delay.h>
102#include <linux/init.h>
103
104#include <asm/io.h>
105
106static int no_piix_dma;
107
1da177e4
LT		 108/**
109 * piix_dma_2_pio - return the PIO mode matching DMA
110 * @xfer_rate: transfer speed
111 *
0c8de52d 112 * Returns the nearest equivalent PIO timing for the DMA
1da177e4
LT		 113 * mode requested by the controller.
114 */
115
116static u8 piix_dma_2_pio (u8 xfer_rate) {
117 switch(xfer_rate) {
118 case XFER_UDMA_6:
119 case XFER_UDMA_5:
120 case XFER_UDMA_4:
121 case XFER_UDMA_3:
122 case XFER_UDMA_2:
123 case XFER_UDMA_1:
124 case XFER_UDMA_0:
125 case XFER_MW_DMA_2:
1da177e4
LT		 126 return 4;
127 case XFER_MW_DMA_1:
1da177e4
LT		 128 return 3;
129 case XFER_SW_DMA_2:
1da177e4
LT		 130 return 2;
131 case XFER_MW_DMA_0:
132 case XFER_SW_DMA_1:
133 case XFER_SW_DMA_0:
1da177e4
LT		 134 default:
135 return 0;
136 }
137}
138
139/**
07af4276 140 * piix_tune_pio - tune PIIX for PIO mode
1da177e4
LT		 141 * @drive: drive to tune
142 * @pio: desired PIO mode
143 *
07af4276 144 * Set the interface PIO mode based upon the settings done by AMI BIOS.
1da177e4 145 */
07af4276 146static void piix_tune_pio (ide_drive_t *drive, u8 pio)
1da177e4
LT		 147{
148 ide_hwif_t *hwif = HWIF(drive);
149 struct pci_dev *dev = hwif->pci_dev;
30dfd12f 150 int is_slave = drive->dn & 1;
1da177e4
LT		 151 int master_port = hwif->channel ? 0x42 : 0x40;
152 int slave_port = 0x44;
153 unsigned long flags;
154 u16 master_data;
155 u8 slave_data;
4fb0f76d 156 static DEFINE_SPINLOCK(tune_lock);
5ac24697 157 int control = 0;
4fb0f76d 158
30dfd12f 159 /* ISP RTC */
5ac24697
AC		 160 static const u8 timings[][2]= {
161 { 0, 0 },
162 { 0, 0 },
163 { 1, 0 },
164 { 2, 1 },
165 { 2, 3 }, };
1da177e4 166
4fb0f76d
AC		 167 /*
168 * Master vs slave is synchronized above us but the slave register is
169 * shared by the two hwifs so the corner case of two slave timeouts in
170 * parallel must be locked.
171 */
172 spin_lock_irqsave(&tune_lock, flags);
1da177e4 173 pci_read_config_word(dev, master_port, &master_data);
5ac24697 174
30dfd12f 175 if (pio > 1)
5ac24697
AC		 176 control |= 1; /* Programmable timing on */
177 if (drive->media == ide_disk)
178 control |= 4; /* Prefetch, post write */
30dfd12f 179 if (pio > 2)
5ac24697 180 control |= 2; /* IORDY */
1da177e4 181 if (is_slave) {
30dfd12f
SS		 182 master_data |= 0x4000;
183 master_data &= ~0x0070;
5ac24697 184 if (pio > 1) {
07af4276
SS		 185 /* Set PPE, IE and TIME */
186 master_data |= control << 4;
5ac24697 187 }
1da177e4 188 pci_read_config_byte(dev, slave_port, &slave_data);
07af4276
SS		 189 slave_data &= hwif->channel ? 0x0f : 0xf0;
190 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
191 (hwif->channel ? 4 : 0);
1da177e4 192 } else {
30dfd12f 193 master_data &= ~0x3307;
5ac24697 194 if (pio > 1) {
1da177e4 195 /* enable PPE, IE and TIME */
07af4276 196 master_data |= control;
5ac24697 197 }
07af4276 198 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
1da177e4
LT		 199 }
200 pci_write_config_word(dev, master_port, master_data);
201 if (is_slave)
202 pci_write_config_byte(dev, slave_port, slave_data);
4fb0f76d 203 spin_unlock_irqrestore(&tune_lock, flags);
1da177e4
LT		 204}
205
07af4276
SS		 206/**
207 * piix_tune_drive - tune a drive attached to PIIX
208 * @drive: drive to tune
209 * @pio: desired PIO mode
210 *
211 * Set the drive's PIO mode (might be useful if drive is not registered
212 * in CMOS for any reason).
213 */
214static void piix_tune_drive (ide_drive_t *drive, u8 pio)
215{
2134758d 216 pio = ide_get_best_pio_mode(drive, pio, 4);
07af4276
SS		 217 piix_tune_pio(drive, pio);
218 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
219}
220
1da177e4
LT		 221/**
222 * piix_tune_chipset - tune a PIIX interface
223 * @drive: IDE drive to tune
f212ff28 224 * @speed: speed to configure
1da177e4
LT		 225 *
226 * Set a PIIX interface channel to the desired speeds. This involves
227 * requires the right timing data into the PIIX configuration space
228 * then setting the drive parameters appropriately
229 */
f212ff28
BZ		 230
231static int piix_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 232{
233 ide_hwif_t *hwif = HWIF(drive);
234 struct pci_dev *dev = hwif->pci_dev;
235 u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4
LT		 236 int a_speed = 3 << (drive->dn * 4);
237 int u_flag = 1 << drive->dn;
238 int v_flag = 0x01 << drive->dn;
239 int w_flag = 0x10 << drive->dn;
240 int u_speed = 0;
241 int sitre;
242 u16 reg4042, reg4a;
243 u8 reg48, reg54, reg55;
244
245 pci_read_config_word(dev, maslave, &reg4042);
246 sitre = (reg4042 & 0x4000) ? 1 : 0;
247 pci_read_config_byte(dev, 0x48, &reg48);
248 pci_read_config_word(dev, 0x4a, &reg4a);
249 pci_read_config_byte(dev, 0x54, &reg54);
250 pci_read_config_byte(dev, 0x55, &reg55);
251
252 switch(speed) {
253 case XFER_UDMA_4:
254 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
255 case XFER_UDMA_5:
256 case XFER_UDMA_3:
257 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
258 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
259 case XFER_MW_DMA_2:
260 case XFER_MW_DMA_1:
261 case XFER_SW_DMA_2: break;
262 case XFER_PIO_4:
263 case XFER_PIO_3:
264 case XFER_PIO_2:
0c8de52d 265 case XFER_PIO_1:
1da177e4
LT		 266 case XFER_PIO_0: break;
267 default: return -1;
268 }
269
270 if (speed >= XFER_UDMA_0) {
271 if (!(reg48 & u_flag))
272 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
273 if (speed == XFER_UDMA_5) {
274 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
275 } else {
276 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
277 }
278 if ((reg4a & a_speed) != u_speed)
279 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
280 if (speed > XFER_UDMA_2) {
281 if (!(reg54 & v_flag))
282 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
283 } else
284 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
285 } else {
286 if (reg48 & u_flag)
287 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
288 if (reg4a & a_speed)
289 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
290 if (reg54 & v_flag)
291 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
292 if (reg55 & w_flag)
293 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
294 }
295
0c8de52d
BZ		 296 if (speed > XFER_PIO_4)
297 piix_tune_pio(drive, piix_dma_2_pio(speed));
298 else
299 piix_tune_pio(drive, speed - XFER_PIO_0);
300
07af4276 301 return ide_config_drive_speed(drive, speed);
1da177e4
LT		 302}
303
1da177e4
LT		 304/**
305 * piix_config_drive_xfer_rate - set up an IDE device
306 * @drive: IDE drive to configure
307 *
308 * Set up the PIIX interface for the best available speed on this
309 * interface, preferring DMA to PIO.
310 */
311
312static int piix_config_drive_xfer_rate (ide_drive_t *drive)
313{
1da177e4
LT		 314 drive->init_speed = 0;
315
29e744d0 316 if (ide_tune_dma(drive))
3608b5d7 317 return 0;
1da177e4 318
d8f4469d 319 if (ide_use_fast_pio(drive))
07af4276 320 piix_tune_drive(drive, 255);
d8f4469d 321
3608b5d7 322 return -1;
1da177e4
LT		 323}
324
325/**
f0dd8712
AL		 326 * piix_is_ichx - check if ICHx
327 * @dev: PCI device to check
1da177e4 328 *
f0dd8712 329 * returns 1 if ICHx, 0 otherwise.
1da177e4 330 */
f0dd8712 331static int piix_is_ichx(struct pci_dev *dev)
1da177e4 332{
f0dd8712 333 switch (dev->device) {
1da177e4
LT		 334 case PCI_DEVICE_ID_INTEL_82801EB_1:
335 case PCI_DEVICE_ID_INTEL_82801AA_1:
336 case PCI_DEVICE_ID_INTEL_82801AB_1:
337 case PCI_DEVICE_ID_INTEL_82801BA_8:
338 case PCI_DEVICE_ID_INTEL_82801BA_9:
339 case PCI_DEVICE_ID_INTEL_82801CA_10:
340 case PCI_DEVICE_ID_INTEL_82801CA_11:
341 case PCI_DEVICE_ID_INTEL_82801DB_1:
342 case PCI_DEVICE_ID_INTEL_82801DB_10:
343 case PCI_DEVICE_ID_INTEL_82801DB_11:
344 case PCI_DEVICE_ID_INTEL_82801EB_11:
345 case PCI_DEVICE_ID_INTEL_82801E_11:
346 case PCI_DEVICE_ID_INTEL_ESB_2:
347 case PCI_DEVICE_ID_INTEL_ICH6_19:
348 case PCI_DEVICE_ID_INTEL_ICH7_21:
d69332b8 349 case PCI_DEVICE_ID_INTEL_ESB2_18:
b7bed9ec 350 case PCI_DEVICE_ID_INTEL_ICH8_6:
f0dd8712 351 return 1;
1da177e4
LT		 352 }
353
354 return 0;
355}
356
f0dd8712
AL		 357/**
358 * init_chipset_piix - set up the PIIX chipset
359 * @dev: PCI device to set up
360 * @name: Name of the device
361 *
362 * Initialize the PCI device as required. For the PIIX this turns
363 * out to be nice and simple
364 */
365
366static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
367{
368 if (piix_is_ichx(dev)) {
369 unsigned int extra = 0;
370 pci_read_config_dword(dev, 0x54, &extra);
371 pci_write_config_dword(dev, 0x54, extra|0x400);
372 }
373
374 return 0;
375}
376
377/**
378 * piix_dma_clear_irq - clear BMDMA status
379 * @drive: IDE drive to clear
380 *
381 * Called from ide_intr() for PIO interrupts
382 * to clear BMDMA status as needed by ICHx
383 */
384static void piix_dma_clear_irq(ide_drive_t *drive)
385{
386 ide_hwif_t *hwif = HWIF(drive);
387 u8 dma_stat;
388
389 /* clear the INTR & ERROR bits */
390 dma_stat = hwif->INB(hwif->dma_status);
391 /* Should we force the bit as well ? */
392 hwif->OUTB(dma_stat, hwif->dma_status);
393}
394
7207626f
BZ		 395struct ich_laptop {
396 u16 device;
397 u16 subvendor;
398 u16 subdevice;
399};
400
401/*
402 * List of laptops that use short cables rather than 80 wire
403 */
404
405static const struct ich_laptop ich_laptop[] = {
406 /* devid, subvendor, subdev */
407 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
408 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
409 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
410 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
411 /* end marker */
412 { 0, }
413};
414
49521f97 415static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
74594fd1 416{
7207626f
BZ		 417 struct pci_dev *pdev = hwif->pci_dev;
418 const struct ich_laptop *lap = &ich_laptop[0];
74594fd1
BZ		 419 u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
420
7207626f
BZ		 421 /* check for specials */
422 while (lap->device) {
423 if (lap->device == pdev->device &&
424 lap->subvendor == pdev->subsystem_vendor &&
425 lap->subdevice == pdev->subsystem_device) {
426 return ATA_CBL_PATA40_SHORT;
427 }
428 lap++;
429 }
430
431 pci_read_config_byte(pdev, 0x54, &reg54h);
74594fd1 432
49521f97 433 return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
74594fd1
BZ		 434}
435
1da177e4
LT		 436/**
437 * init_hwif_piix - fill in the hwif for the PIIX
438 * @hwif: IDE interface
439 *
440 * Set up the ide_hwif_t for the PIIX interface according to the
441 * capabilities of the hardware.
442 */
443
444static void __devinit init_hwif_piix(ide_hwif_t *hwif)
445{
1da177e4
LT		 446#ifndef CONFIG_IA64
447 if (!hwif->irq)
448 hwif->irq = hwif->channel ? 15 : 14;
449#endif /* CONFIG_IA64 */
450
451 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
452 /* This is a painful system best to let it self tune for now */
453 return;
454 }
455
456 hwif->autodma = 0;
457 hwif->tuneproc = &piix_tune_drive;
458 hwif->speedproc = &piix_tune_chipset;
459 hwif->drives[0].autotune = 1;
460 hwif->drives[1].autotune = 1;
461
462 if (!hwif->dma_base)
463 return;
464
f0dd8712
AL		 465 /* ICHx need to clear the bmdma status for all interrupts */
466 if (piix_is_ichx(hwif->pci_dev))
467 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
468
1da177e4 469 hwif->atapi_dma = 1;
18137207
BZ		 470
471 hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4
LT		 472 hwif->mwdma_mask = 0x06;
473 hwif->swdma_mask = 0x04;
474
18137207 475 if (hwif->ultra_mask & 0x78) {
49521f97
BZ		 476 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
477 hwif->cbl = piix_cable_detect(hwif);
1da177e4
LT		 478 }
479
74594fd1
BZ		 480 if (no_piix_dma)
481 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
482
1da177e4
LT		 483 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
484 if (!noautodma)
485 hwif->autodma = 1;
486
487 hwif->drives[1].autodma = hwif->autodma;
488 hwif->drives[0].autodma = hwif->autodma;
489}
490
18137207 491#define DECLARE_PIIX_DEV(name_str, udma) \
1da177e4
LT		 492 { \
493 .name = name_str, \
494 .init_chipset = init_chipset_piix, \
495 .init_hwif = init_hwif_piix, \
1da177e4
LT		 496 .autodma = AUTODMA, \
497 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
498 .bootable = ON_BOARD, \
4099d143 499 .pio_mask = ATA_PIO4, \
18137207 500 .udma_mask = udma, \
1da177e4
LT		 501 }
502
503static ide_pci_device_t piix_pci_info[] __devinitdata = {
18137207
BZ		 504 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
505 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
1da177e4 506
d2872239
SS		 507 /* 2 */
508 { /*
509 * MPIIX actually has only a single IDE channel mapped to
510 * the primary or secondary ports depending on the value
511 * of the bit 14 of the IDETIM register at offset 0x6c
512 */
1da177e4
LT		 513 .name = "MPIIX",
514 .init_hwif = init_hwif_piix,
1da177e4 515 .autodma = NODMA,
d2872239 516 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
1da177e4 517 .bootable = ON_BOARD,
a5d8c5c8 518 .host_flags = IDE_HFLAG_ISA_PORTS,
4099d143 519 .pio_mask = ATA_PIO4,
1da177e4
LT		 520 },
521
18137207
BZ		 522 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
523 /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
524 /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
525 /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
526 /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
527 /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
528 /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
529 /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
530 /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
531 /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
532 /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
533 /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
534 /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
535 /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
536 /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
537 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
538 /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
539 /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
540 /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
541 /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
542 /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
543 /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
1da177e4
LT		 544};
545
546/**
547 * piix_init_one - called when a PIIX is found
548 * @dev: the piix device
549 * @id: the matching pci id
550 *
551 * Called when the PCI registration layer (or the IDE initialization)
552 * finds a device matching our IDE device tables.
553 */
554
555static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
556{
557 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
558
559 return ide_setup_pci_device(dev, d);
560}
561
562/**
563 * piix_check_450nx - Check for problem 450NX setup
564 *
565 * Check for the present of 450NX errata #19 and errata #25. If
566 * they are found, disable use of DMA IDE
567 */
568
569static void __devinit piix_check_450nx(void)
570{
571 struct pci_dev *pdev = NULL;
572 u16 cfg;
1424e504 573 while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
1da177e4
LT		 574 {
575 /* Look for 450NX PXB. Check for problem configurations
576 A PCI quirk checks bit 6 already */
1da177e4
LT		 577 pci_read_config_word(pdev, 0x41, &cfg);
578 /* Only on the original revision: IDE DMA can hang */
44c10138 579 if (pdev->revision == 0x00)
1da177e4
LT		 580 no_piix_dma = 1;
581 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 582 else if (cfg & (1<<14) && pdev->revision < 5)
1da177e4
LT		 583 no_piix_dma = 2;
584 }
585 if(no_piix_dma)
586 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
587 if(no_piix_dma == 2)
588 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
589}
590
591static struct pci_device_id piix_pci_tbl[] = {
592 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
593 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
594 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
595 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
597 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
598 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
599 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
600 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
601 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
602 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
603 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
604 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
605 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
606 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
607 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
608 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
609 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
610#ifdef CONFIG_BLK_DEV_IDE_SATA
611 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
612#endif
613 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
614 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
615 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
616 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
d69332b8 617 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
b7bed9ec 618 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
1da177e4
LT		 619 { 0, },
620};
621MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
622
623static struct pci_driver driver = {
624 .name = "PIIX_IDE",
625 .id_table = piix_pci_tbl,
626 .probe = piix_init_one,
627};
628
629static int __init piix_ide_init(void)
630{
631 piix_check_450nx();
632 return ide_pci_register_driver(&driver);
633}
634
635module_init(piix_ide_init);
636
637MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
638MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
639MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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