Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
3 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
4 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
07af4276 | 5 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
2be564b0 | 9 | * Documentation: |
1da177e4 | 10 | * |
1da177e4 LT |
11 | * Publically available from Intel web site. Errata documentation |
12 | * is also publically available. As an aide to anyone hacking on this | |
13 | * driver the list of errata that are relevant is below.going back to | |
14 | * PIIX4. Older device documentation is now a bit tricky to find. | |
15 | * | |
16 | * Errata of note: | |
17 | * | |
18 | * Unfixable | |
19 | * PIIX4 errata #9 - Only on ultra obscure hw | |
20 | * ICH3 errata #13 - Not observed to affect real hw | |
21 | * by Intel | |
22 | * | |
23 | * Things we must deal with | |
24 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
25 | * (must stop/start dma to recover) | |
26 | * 440MX errata #15 - As PIIX4 errata #10 | |
27 | * PIIX4 errata #15 - Must not read control registers | |
28 | * during a PIO transfer | |
29 | * 440MX errata #13 - As PIIX4 errata #15 | |
30 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
31 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
32 | * ICH2 spec c #9 - Extra operations needed to handle | |
33 | * drive hotswap [NOT YET SUPPORTED] | |
34 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
35 | * and must be dword aligned | |
36 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
37 | * | |
38 | * Should have been BIOS fixed: | |
39 | * 450NX: errata #19 - DMA hangs on old 450NX | |
40 | * 450NX: errata #20 - DMA hangs on old 450NX | |
41 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
42 | * ICH3 errata #15 - IDE deadlock under high load | |
43 | * (BIOS must set dev 31 fn 0 bit 23) | |
44 | * ICH3 errata #18 - Don't use native mode | |
45 | */ | |
46 | ||
1da177e4 LT |
47 | #include <linux/types.h> |
48 | #include <linux/module.h> | |
49 | #include <linux/kernel.h> | |
1da177e4 LT |
50 | #include <linux/pci.h> |
51 | #include <linux/hdreg.h> | |
52 | #include <linux/ide.h> | |
1da177e4 LT |
53 | #include <linux/init.h> |
54 | ||
55 | #include <asm/io.h> | |
56 | ||
ced3ec8a BZ |
57 | #define DRV_NAME "piix" |
58 | ||
1da177e4 LT |
59 | static int no_piix_dma; |
60 | ||
1da177e4 | 61 | /** |
88b2b32b BZ |
62 | * piix_set_pio_mode - set host controller for PIO mode |
63 | * @drive: drive | |
64 | * @pio: PIO mode number | |
1da177e4 | 65 | * |
07af4276 | 66 | * Set the interface PIO mode based upon the settings done by AMI BIOS. |
1da177e4 | 67 | */ |
88b2b32b BZ |
68 | |
69 | static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
70 | { |
71 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 72 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
30dfd12f | 73 | int is_slave = drive->dn & 1; |
1da177e4 LT |
74 | int master_port = hwif->channel ? 0x42 : 0x40; |
75 | int slave_port = 0x44; | |
76 | unsigned long flags; | |
77 | u16 master_data; | |
78 | u8 slave_data; | |
4fb0f76d | 79 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 80 | int control = 0; |
4fb0f76d | 81 | |
30dfd12f | 82 | /* ISP RTC */ |
5ac24697 AC |
83 | static const u8 timings[][2]= { |
84 | { 0, 0 }, | |
85 | { 0, 0 }, | |
86 | { 1, 0 }, | |
87 | { 2, 1 }, | |
88 | { 2, 3 }, }; | |
1da177e4 | 89 | |
4fb0f76d AC |
90 | /* |
91 | * Master vs slave is synchronized above us but the slave register is | |
92 | * shared by the two hwifs so the corner case of two slave timeouts in | |
93 | * parallel must be locked. | |
94 | */ | |
95 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 96 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 | 97 | |
30dfd12f | 98 | if (pio > 1) |
5ac24697 AC |
99 | control |= 1; /* Programmable timing on */ |
100 | if (drive->media == ide_disk) | |
101 | control |= 4; /* Prefetch, post write */ | |
30dfd12f | 102 | if (pio > 2) |
5ac24697 | 103 | control |= 2; /* IORDY */ |
1da177e4 | 104 | if (is_slave) { |
30dfd12f SS |
105 | master_data |= 0x4000; |
106 | master_data &= ~0x0070; | |
5ac24697 | 107 | if (pio > 1) { |
07af4276 SS |
108 | /* Set PPE, IE and TIME */ |
109 | master_data |= control << 4; | |
5ac24697 | 110 | } |
1da177e4 | 111 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
112 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
113 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
114 | (hwif->channel ? 4 : 0); | |
1da177e4 | 115 | } else { |
30dfd12f | 116 | master_data &= ~0x3307; |
5ac24697 | 117 | if (pio > 1) { |
1da177e4 | 118 | /* enable PPE, IE and TIME */ |
07af4276 | 119 | master_data |= control; |
5ac24697 | 120 | } |
07af4276 | 121 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
122 | } |
123 | pci_write_config_word(dev, master_port, master_data); | |
124 | if (is_slave) | |
125 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 126 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
127 | } |
128 | ||
07af4276 | 129 | /** |
88b2b32b BZ |
130 | * piix_set_dma_mode - set host controller for DMA mode |
131 | * @drive: drive | |
132 | * @speed: DMA mode | |
1da177e4 | 133 | * |
88b2b32b BZ |
134 | * Set a PIIX host controller to the desired DMA mode. This involves |
135 | * programming the right timing data into the PCI configuration space. | |
1da177e4 | 136 | */ |
f212ff28 | 137 | |
88b2b32b | 138 | static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
139 | { |
140 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 141 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 142 | u8 maslave = hwif->channel ? 0x42 : 0x40; |
1da177e4 LT |
143 | int a_speed = 3 << (drive->dn * 4); |
144 | int u_flag = 1 << drive->dn; | |
145 | int v_flag = 0x01 << drive->dn; | |
146 | int w_flag = 0x10 << drive->dn; | |
147 | int u_speed = 0; | |
148 | int sitre; | |
149 | u16 reg4042, reg4a; | |
1c54a93d | 150 | u8 reg48, reg54, reg55; |
1da177e4 LT |
151 | |
152 | pci_read_config_word(dev, maslave, ®4042); | |
153 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
154 | pci_read_config_byte(dev, 0x48, ®48); | |
155 | pci_read_config_word(dev, 0x4a, ®4a); | |
156 | pci_read_config_byte(dev, 0x54, ®54); | |
157 | pci_read_config_byte(dev, 0x55, ®55); | |
158 | ||
1da177e4 | 159 | if (speed >= XFER_UDMA_0) { |
4db90a14 BZ |
160 | u8 udma = speed - XFER_UDMA_0; |
161 | ||
162 | u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4); | |
163 | ||
1da177e4 LT |
164 | if (!(reg48 & u_flag)) |
165 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
166 | if (speed == XFER_UDMA_5) { | |
167 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
168 | } else { | |
169 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
170 | } | |
171 | if ((reg4a & a_speed) != u_speed) | |
172 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
173 | if (speed > XFER_UDMA_2) { | |
174 | if (!(reg54 & v_flag)) | |
175 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
176 | } else | |
177 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
178 | } else { | |
8c91abf8 | 179 | const u8 mwdma_to_pio[] = { 0, 3, 4 }; |
1c54a93d | 180 | u8 pio; |
8c91abf8 | 181 | |
1da177e4 LT |
182 | if (reg48 & u_flag) |
183 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
184 | if (reg4a & a_speed) | |
185 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
186 | if (reg54 & v_flag) | |
187 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
188 | if (reg55 & w_flag) | |
189 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
8c91abf8 BZ |
190 | |
191 | if (speed >= XFER_MW_DMA_0) | |
192 | pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; | |
193 | else | |
194 | pio = 2; /* only SWDMA2 is allowed */ | |
1da177e4 | 195 | |
1c54a93d BZ |
196 | piix_set_pio_mode(drive, pio); |
197 | } | |
1da177e4 LT |
198 | } |
199 | ||
1da177e4 | 200 | /** |
40d2dd7e | 201 | * init_chipset_ich - set up the ICH chipset |
f0dd8712 AL |
202 | * @dev: PCI device to set up |
203 | * @name: Name of the device | |
204 | * | |
40d2dd7e BZ |
205 | * Initialize the PCI device as required. For the ICH this turns |
206 | * out to be nice and simple. | |
f0dd8712 AL |
207 | */ |
208 | ||
40d2dd7e | 209 | static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name) |
f0dd8712 | 210 | { |
40d2dd7e BZ |
211 | u32 extra = 0; |
212 | ||
213 | pci_read_config_dword(dev, 0x54, &extra); | |
214 | pci_write_config_dword(dev, 0x54, extra | 0x400); | |
f0dd8712 AL |
215 | |
216 | return 0; | |
217 | } | |
218 | ||
219 | /** | |
220 | * piix_dma_clear_irq - clear BMDMA status | |
221 | * @drive: IDE drive to clear | |
222 | * | |
223 | * Called from ide_intr() for PIO interrupts | |
224 | * to clear BMDMA status as needed by ICHx | |
225 | */ | |
226 | static void piix_dma_clear_irq(ide_drive_t *drive) | |
227 | { | |
228 | ide_hwif_t *hwif = HWIF(drive); | |
229 | u8 dma_stat; | |
230 | ||
231 | /* clear the INTR & ERROR bits */ | |
cab7f8ed | 232 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
f0dd8712 | 233 | /* Should we force the bit as well ? */ |
cab7f8ed | 234 | outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); |
f0dd8712 AL |
235 | } |
236 | ||
7207626f BZ |
237 | struct ich_laptop { |
238 | u16 device; | |
239 | u16 subvendor; | |
240 | u16 subdevice; | |
241 | }; | |
242 | ||
243 | /* | |
244 | * List of laptops that use short cables rather than 80 wire | |
245 | */ | |
246 | ||
247 | static const struct ich_laptop ich_laptop[] = { | |
248 | /* devid, subvendor, subdev */ | |
afda5e4d | 249 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
7207626f BZ |
250 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
251 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ | |
252 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ | |
dd0fd40d | 253 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
7207626f | 254 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */ |
1fa5a40f | 255 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
7207626f BZ |
256 | /* end marker */ |
257 | { 0, } | |
258 | }; | |
259 | ||
49521f97 | 260 | static u8 __devinit piix_cable_detect(ide_hwif_t *hwif) |
74594fd1 | 261 | { |
36501650 | 262 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
7207626f | 263 | const struct ich_laptop *lap = &ich_laptop[0]; |
74594fd1 BZ |
264 | u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; |
265 | ||
7207626f BZ |
266 | /* check for specials */ |
267 | while (lap->device) { | |
268 | if (lap->device == pdev->device && | |
269 | lap->subvendor == pdev->subsystem_vendor && | |
270 | lap->subdevice == pdev->subsystem_device) { | |
271 | return ATA_CBL_PATA40_SHORT; | |
272 | } | |
273 | lap++; | |
274 | } | |
275 | ||
276 | pci_read_config_byte(pdev, 0x54, ®54h); | |
74594fd1 | 277 | |
49521f97 | 278 | return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
74594fd1 BZ |
279 | } |
280 | ||
1da177e4 LT |
281 | /** |
282 | * init_hwif_piix - fill in the hwif for the PIIX | |
283 | * @hwif: IDE interface | |
284 | * | |
285 | * Set up the ide_hwif_t for the PIIX interface according to the | |
286 | * capabilities of the hardware. | |
287 | */ | |
288 | ||
289 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
290 | { | |
1da177e4 LT |
291 | if (!hwif->dma_base) |
292 | return; | |
293 | ||
74594fd1 BZ |
294 | if (no_piix_dma) |
295 | hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; | |
1da177e4 LT |
296 | } |
297 | ||
40d2dd7e BZ |
298 | static void __devinit init_hwif_ich(ide_hwif_t *hwif) |
299 | { | |
300 | init_hwif_piix(hwif); | |
301 | ||
302 | /* ICHx need to clear the BMDMA status for all interrupts */ | |
303 | if (hwif->dma_base) | |
304 | hwif->ide_dma_clear_irq = &piix_dma_clear_irq; | |
305 | } | |
306 | ||
ac95beed BZ |
307 | static const struct ide_port_ops piix_port_ops = { |
308 | .set_pio_mode = piix_set_pio_mode, | |
309 | .set_dma_mode = piix_set_dma_mode, | |
310 | .cable_detect = piix_cable_detect, | |
311 | }; | |
312 | ||
3985ee3b | 313 | #ifndef CONFIG_IA64 |
5e71d9c5 | 314 | #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS |
3985ee3b | 315 | #else |
5e71d9c5 | 316 | #define IDE_HFLAGS_PIIX 0 |
3985ee3b BZ |
317 | #endif |
318 | ||
ced3ec8a | 319 | #define DECLARE_PIIX_DEV(udma) \ |
1da177e4 | 320 | { \ |
ced3ec8a | 321 | .name = DRV_NAME, \ |
1da177e4 | 322 | .init_hwif = init_hwif_piix, \ |
1da177e4 | 323 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ |
ac95beed | 324 | .port_ops = &piix_port_ops, \ |
3985ee3b | 325 | .host_flags = IDE_HFLAGS_PIIX, \ |
4099d143 | 326 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
327 | .swdma_mask = ATA_SWDMA2_ONLY, \ |
328 | .mwdma_mask = ATA_MWDMA12_ONLY, \ | |
18137207 | 329 | .udma_mask = udma, \ |
1da177e4 LT |
330 | } |
331 | ||
ced3ec8a | 332 | #define DECLARE_ICH_DEV(udma) \ |
40d2dd7e | 333 | { \ |
ced3ec8a | 334 | .name = DRV_NAME, \ |
40d2dd7e BZ |
335 | .init_chipset = init_chipset_ich, \ |
336 | .init_hwif = init_hwif_ich, \ | |
337 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
ac95beed | 338 | .port_ops = &piix_port_ops, \ |
3985ee3b | 339 | .host_flags = IDE_HFLAGS_PIIX, \ |
40d2dd7e BZ |
340 | .pio_mask = ATA_PIO4, \ |
341 | .swdma_mask = ATA_SWDMA2_ONLY, \ | |
342 | .mwdma_mask = ATA_MWDMA12_ONLY, \ | |
343 | .udma_mask = udma, \ | |
344 | } | |
345 | ||
85620436 | 346 | static const struct ide_port_info piix_pci_info[] __devinitdata = { |
ced3ec8a | 347 | /* 0: MPIIX */ |
d2872239 SS |
348 | { /* |
349 | * MPIIX actually has only a single IDE channel mapped to | |
350 | * the primary or secondary ports depending on the value | |
351 | * of the bit 14 of the IDETIM register at offset 0x6c | |
352 | */ | |
ced3ec8a | 353 | .name = DRV_NAME, |
d2872239 | 354 | .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, |
47b68788 | 355 | .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA | |
3985ee3b | 356 | IDE_HFLAGS_PIIX, |
4099d143 | 357 | .pio_mask = ATA_PIO4, |
3985ee3b | 358 | /* This is a painful system best to let it self tune for now */ |
1da177e4 | 359 | }, |
ced3ec8a BZ |
360 | /* 1: PIIXa/PIIXb/PIIX3 */ |
361 | DECLARE_PIIX_DEV(0x00), /* no udma */ | |
362 | /* 2: PIIX4 */ | |
363 | DECLARE_PIIX_DEV(ATA_UDMA2), | |
364 | /* 3: ICH0 */ | |
365 | DECLARE_ICH_DEV(ATA_UDMA2), | |
366 | /* 4: ICH */ | |
367 | DECLARE_ICH_DEV(ATA_UDMA4), | |
368 | /* 5: PIIX4 */ | |
369 | DECLARE_PIIX_DEV(ATA_UDMA4), | |
370 | /* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */ | |
371 | DECLARE_ICH_DEV(ATA_UDMA5), | |
1da177e4 LT |
372 | }; |
373 | ||
374 | /** | |
375 | * piix_init_one - called when a PIIX is found | |
376 | * @dev: the piix device | |
377 | * @id: the matching pci id | |
378 | * | |
379 | * Called when the PCI registration layer (or the IDE initialization) | |
380 | * finds a device matching our IDE device tables. | |
381 | */ | |
382 | ||
383 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
384 | { | |
6cdf6eb3 | 385 | return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL); |
1da177e4 LT |
386 | } |
387 | ||
388 | /** | |
389 | * piix_check_450nx - Check for problem 450NX setup | |
390 | * | |
391 | * Check for the present of 450NX errata #19 and errata #25. If | |
392 | * they are found, disable use of DMA IDE | |
393 | */ | |
394 | ||
395 | static void __devinit piix_check_450nx(void) | |
396 | { | |
397 | struct pci_dev *pdev = NULL; | |
398 | u16 cfg; | |
1424e504 | 399 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
400 | { |
401 | /* Look for 450NX PXB. Check for problem configurations | |
402 | A PCI quirk checks bit 6 already */ | |
1da177e4 LT |
403 | pci_read_config_word(pdev, 0x41, &cfg); |
404 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 405 | if (pdev->revision == 0x00) |
1da177e4 LT |
406 | no_piix_dma = 1; |
407 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 408 | else if (cfg & (1<<14) && pdev->revision < 5) |
1da177e4 LT |
409 | no_piix_dma = 2; |
410 | } | |
411 | if(no_piix_dma) | |
ced3ec8a | 412 | printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n"); |
1da177e4 | 413 | if(no_piix_dma == 2) |
ced3ec8a | 414 | printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n"); |
1da177e4 LT |
415 | } |
416 | ||
9cbcc5e3 | 417 | static const struct pci_device_id piix_pci_tbl[] = { |
ced3ec8a BZ |
418 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 }, |
419 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 }, | |
420 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 }, | |
421 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 }, | |
422 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 }, | |
423 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 }, | |
424 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 }, | |
425 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 }, | |
426 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 }, | |
427 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 }, | |
428 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 }, | |
429 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 }, | |
430 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 }, | |
431 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 }, | |
432 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 }, | |
433 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 }, | |
434 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 }, | |
435 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 }, | |
1da177e4 | 436 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
ced3ec8a | 437 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 }, |
1da177e4 | 438 | #endif |
ced3ec8a BZ |
439 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 }, |
440 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 }, | |
441 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 }, | |
442 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 }, | |
443 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 }, | |
444 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 }, | |
1da177e4 LT |
445 | { 0, }, |
446 | }; | |
447 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
448 | ||
449 | static struct pci_driver driver = { | |
450 | .name = "PIIX_IDE", | |
451 | .id_table = piix_pci_tbl, | |
452 | .probe = piix_init_one, | |
da8c3e0d | 453 | .remove = ide_pci_remove, |
1da177e4 LT |
454 | }; |
455 | ||
456 | static int __init piix_ide_init(void) | |
457 | { | |
458 | piix_check_450nx(); | |
459 | return ide_pci_register_driver(&driver); | |
460 | } | |
461 | ||
da8c3e0d BZ |
462 | static void __exit piix_ide_exit(void) |
463 | { | |
464 | pci_unregister_driver(&driver); | |
465 | } | |
466 | ||
1da177e4 | 467 | module_init(piix_ide_init); |
da8c3e0d | 468 | module_exit(piix_ide_exit); |
1da177e4 LT |
469 | |
470 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
471 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
472 | MODULE_LICENSE("GPL"); |