[deliverable/linux.git] / drivers / ide / pci / sc1200.c

/*
 * Copyright (C) 2000-2002		Mark Lord <mlord@pobox.com>
 * Copyright (C)      2007		Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	Available from National Semiconductor
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/pm.h>

#include <asm/io.h>

#define SC1200_REV_A	0x00
#define SC1200_REV_B1	0x01
#define SC1200_REV_B3	0x02
#define SC1200_REV_C1	0x03
#define SC1200_REV_D1	0x04

#define PCI_CLK_33	0x00
#define PCI_CLK_48	0x01
#define PCI_CLK_66	0x02
#define PCI_CLK_33A	0x03

static unsigned short sc1200_get_pci_clock (void)
{
	unsigned char chip_id, silicon_revision;
	unsigned int pci_clock;
	/*
	 * Check the silicon revision, as not all versions of the chip
	 * have the register with the fast PCI bus timings.
	 */
	chip_id = inb (0x903c);
	silicon_revision = inb (0x903d);

	// Read the fast pci clock frequency
	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
		pci_clock = PCI_CLK_33;
	} else {
		// check clock generator configuration (cfcc)
		// the clock is in bits 8 and 9 of this word

		pci_clock = inw (0x901e);
		pci_clock >>= 8;
		pci_clock &= 0x03;
		if (pci_clock == PCI_CLK_33A)
			pci_clock = PCI_CLK_33;
	}
	return pci_clock;
}

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static const unsigned int sc1200_pio_timings[4][5] =
	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},	// format0  33Mhz
	 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},	// format1, 33Mhz
	 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},	// format1, 48Mhz
	 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}};	// format1, 66Mhz

/*
 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
 */
//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)

static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;

	pci_read_config_dword(pdev, basereg + 4, &format);
	format = (format >> 31) & 1;
	if (format)
		format += sc1200_get_pci_clock();
	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
			       sc1200_pio_timings[format][pio]);
}

/*
 *	The SC1200 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 */
static u8 sc1200_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	struct hd_driveid *mateid = mate->id;
	u8 mask = hwif->ultra_mask;

	if (mate->present == 0)
		goto out;

	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
			goto out;
		if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
			mask = 0;
	}
out:
	return mask;
}

static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t		*hwif = HWIF(drive);
	struct pci_dev		*dev = to_pci_dev(hwif->dev);
	int			unit = drive->select.b.unit;
	unsigned int		reg, timings;
	unsigned short		pci_clock;
	unsigned int		basereg = hwif->channel ? 0x50 : 0x40;

	static const u32 udma_timing[3][3] = {
		{ 0x00921250, 0x00911140, 0x00911030 },
		{ 0x00932470, 0x00922260, 0x00922140 },
		{ 0x009436a1, 0x00933481, 0x00923261 },
	};

	static const u32 mwdma_timing[3][3] = {
		{ 0x00077771, 0x00012121, 0x00002020 },
		{ 0x000bbbb2, 0x00024241, 0x00013131 },
		{ 0x000ffff3, 0x00035352, 0x00015151 },
	};

	pci_clock = sc1200_get_pci_clock();

	/*
	 * Note that each DMA mode has several timings associated with it.
	 * The correct timing depends on the fast PCI clock freq.
	 */

	if (mode >= XFER_UDMA_0)
		timings =  udma_timing[pci_clock][mode - XFER_UDMA_0];
	else
		timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];

	if (unit == 0) {			/* are we configuring drive0? */
		pci_read_config_dword(dev, basereg + 4, &reg);
		timings |= reg & 0x80000000;	/* preserve PIO format bit */
		pci_write_config_dword(dev, basereg + 4, timings);
	} else
		pci_write_config_dword(dev, basereg + 12, timings);
}

/*  Replacement for the standard ide_dma_end action in
 *  dma_proc.
 *
 *  returns 1 on error, 0 otherwise
 */
static int sc1200_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	unsigned long dma_base = hwif->dma_base;
	byte dma_stat;

	dma_stat = inb(dma_base+2);		/* get DMA status */

	if (!(dma_stat & 4))
		printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
		  dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));

	outb(dma_stat|0x1b, dma_base+2);	/* clear the INTR & ERROR bits */
	outb(inb(dma_base)&~1, dma_base);	/* !! DO THIS HERE !! stop DMA */

	drive->waiting_for_dma = 0;
	ide_destroy_dmatable(drive);		/* purge DMA mappings */

	return (dma_stat & 7) != 4;		/* verify good DMA status */
}

/*
 * sc1200_set_pio_mode() handles setting of PIO modes
 * for both the chipset and drive.
 *
 * All existing BIOSs for this chipset guarantee that all drives
 * will have valid default PIO timings set up before we get here.
 */

static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t	*hwif = HWIF(drive);
	int		mode = -1;

	/*
	 * bad abuse of ->set_pio_mode interface
	 */
	switch (pio) {
		case 200: mode = XFER_UDMA_0;	break;
		case 201: mode = XFER_UDMA_1;	break;
		case 202: mode = XFER_UDMA_2;	break;
		case 100: mode = XFER_MW_DMA_0;	break;
		case 101: mode = XFER_MW_DMA_1;	break;
		case 102: mode = XFER_MW_DMA_2;	break;
	}
	if (mode != -1) {
		printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
		ide_dma_off_quietly(drive);
		if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
			hwif->dma_ops->dma_host_set(drive, 1);
		return;
	}

	sc1200_tunepio(drive, pio);
}

#ifdef CONFIG_PM
struct sc1200_saved_state {
	u32 regs[8];
};

static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
{
	printk("SC1200: suspend(%u)\n", state.event);

	/*
	 * we only save state when going from full power to less
	 */
	if (state.event == PM_EVENT_ON) {
		struct ide_host *host = pci_get_drvdata(dev);
		struct sc1200_saved_state *ss = host->host_priv;
		unsigned int r;

		/*
		 * save timing registers
		 * (this may be unnecessary if BIOS also does it)
		 */
		for (r = 0; r < 8; r++)
			pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	}

	pci_disable_device(dev);
	pci_set_power_state(dev, pci_choose_state(dev, state));
	return 0;
}

static int sc1200_resume (struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct sc1200_saved_state *ss = host->host_priv;
	unsigned int r;
	int i;

	i = pci_enable_device(dev);
	if (i)
		return i;

	/*
	 * restore timing registers
	 * (this may be unnecessary if BIOS also does it)
	 */
	for (r = 0; r < 8; r++)
		pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);

	return 0;
}
#endif

static const struct ide_port_ops sc1200_port_ops = {
	.set_pio_mode		= sc1200_set_pio_mode,
	.set_dma_mode		= sc1200_set_dma_mode,
	.udma_filter		= sc1200_udma_filter,
};

static const struct ide_dma_ops sc1200_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= sc1200_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timeout		= ide_dma_timeout,
};

static const struct ide_port_info sc1200_chipset __devinitdata = {
	.name		= "SC1200",
	.port_ops	= &sc1200_port_ops,
	.dma_ops	= &sc1200_dma_ops,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_ABUSE_DMA_MODES,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct sc1200_saved_state *ss = NULL;
	int rc;

#ifdef CONFIG_PM
	ss = kmalloc(sizeof(*ss), GFP_KERNEL);
	if (ss == NULL)
		return -ENOMEM;
#endif
	rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
	if (rc)
		kfree(ss);

	return rc;
}

static const struct pci_device_id sc1200_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);

static struct pci_driver driver = {
	.name		= "SC1200_IDE",
	.id_table	= sc1200_pci_tbl,
	.probe		= sc1200_init_one,
	.remove		= ide_pci_remove,
#ifdef CONFIG_PM
	.suspend	= sc1200_suspend,
	.resume		= sc1200_resume,
#endif
};

static int __init sc1200_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

static void __exit sc1200_ide_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(sc1200_ide_init);
module_exit(sc1200_ide_exit);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5fd216bb BZ	3	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	4	*
1da177e4 LT	5	* May be copied or modified under the terms of the GNU General Public License
	6	*
	7	* Development of this chipset driver was funded
	8	* by the nice folks at National Semiconductor.
	9	*
	10	* Documentation:
	11	* Available from National Semiconductor
	12	*/
	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
1da177e4	17	#include <linux/hdreg.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/ide.h>
	21	#include <linux/pm.h>
78829dd9	22
1da177e4	23	#include <asm/io.h>
1da177e4 LT	24
	25	#define SC1200_REV_A 0x00
	26	#define SC1200_REV_B1 0x01
	27	#define SC1200_REV_B3 0x02
	28	#define SC1200_REV_C1 0x03
	29	#define SC1200_REV_D1 0x04
	30
	31	#define PCI_CLK_33 0x00
	32	#define PCI_CLK_48 0x01
	33	#define PCI_CLK_66 0x02
	34	#define PCI_CLK_33A 0x03
	35
	36	static unsigned short sc1200_get_pci_clock (void)
	37	{
	38	unsigned char chip_id, silicon_revision;
	39	unsigned int pci_clock;
	40	/*
	41	* Check the silicon revision, as not all versions of the chip
	42	* have the register with the fast PCI bus timings.
	43	*/
	44	chip_id = inb (0x903c);
	45	silicon_revision = inb (0x903d);
	46
	47	// Read the fast pci clock frequency
	48	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
	49	pci_clock = PCI_CLK_33;
	50	} else {
	51	// check clock generator configuration (cfcc)
	52	// the clock is in bits 8 and 9 of this word
	53
	54	pci_clock = inw (0x901e);
	55	pci_clock >>= 8;
	56	pci_clock &= 0x03;
	57	if (pci_clock == PCI_CLK_33A)
	58	pci_clock = PCI_CLK_33;
	59	}
	60	return pci_clock;
	61	}
	62
1da177e4 LT	63	/*
	64	* Here are the standard PIO mode 0-4 timings for each "format".
	65	* Format-0 uses fast data reg timings, with slower command reg timings.
	66	* Format-1 uses fast timings for all registers, but won't work with all drives.
	67	*/
	68	static const unsigned int sc1200_pio_timings[4][5] =
	69	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
	70	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
	71	{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
	72	{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
	73
	74	/*
	75	* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
	76	*/
	77	//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
	78
3c3f5d2c BZ	79	static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
	80	{
	81	ide_hwif_t *hwif = drive->hwif;
36501650	82	struct pci_dev *pdev = to_pci_dev(hwif->dev);
3c3f5d2c BZ	83	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
	84
	85	pci_read_config_dword(pdev, basereg + 4, &format);
	86	format = (format >> 31) & 1;
	87	if (format)
	88	format += sc1200_get_pci_clock();
	89	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
	90	sc1200_pio_timings[format][pio]);
	91	}
	92
5fd216bb BZ	93	/*
	94	* The SC1200 specifies that two drives sharing a cable cannot mix
	95	* UDMA/MDMA. It has to be one or the other, for the pair, though
	96	* different timings can still be chosen for each drive. We could
	97	* set the appropriate timing bits on the fly, but that might be
	98	* a bit confusing. So, for now we statically handle this requirement
	99	* by looking at our mate drive to see what it is capable of, before
	100	* choosing a mode for our own drive.
	101	*/
	102	static u8 sc1200_udma_filter(ide_drive_t *drive)
1da177e4	103	{
5fd216bb BZ	104	ide_hwif_t *hwif = drive->hwif;
	105	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	106	struct hd_driveid *mateid = mate->id;
	107	u8 mask = hwif->ultra_mask;
	108
	109	if (mate->present == 0)
	110	goto out;
	111
	112	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
	113	if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
	114	goto out;
	115	if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
	116	mask = 0;
1da177e4	117	}
5fd216bb BZ	118	out:
5fd216bb BZ	119	return mask;
1da177e4 LT	120	}
1da177e4 LT	121
88b2b32b	122	static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4 LT	123	{
1da177e4 LT	124	ide_hwif_t *hwif = HWIF(drive);
36501650	125	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	126	int unit = drive->select.b.unit;
	127	unsigned int reg, timings;
	128	unsigned short pci_clock;
	129	unsigned int basereg = hwif->channel ? 0x50 : 0x40;
	130
4eed504d BZ	131	static const u32 udma_timing[3][3] = {
	132	{ 0x00921250, 0x00911140, 0x00911030 },
	133	{ 0x00932470, 0x00922260, 0x00922140 },
	134	{ 0x009436a1, 0x00933481, 0x00923261 },
	135	};
	136
	137	static const u32 mwdma_timing[3][3] = {
	138	{ 0x00077771, 0x00012121, 0x00002020 },
	139	{ 0x000bbbb2, 0x00024241, 0x00013131 },
	140	{ 0x000ffff3, 0x00035352, 0x00015151 },
	141	};
	142
1da177e4 LT	143	pci_clock = sc1200_get_pci_clock();
	144
	145	/*
1da177e4 LT	146	* Note that each DMA mode has several timings associated with it.
	147	* The correct timing depends on the fast PCI clock freq.
	148	*/
4eed504d BZ	149
	150	if (mode >= XFER_UDMA_0)
	151	timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
	152	else
	153	timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
1da177e4 LT	154
1da177e4 LT	155	if (unit == 0) { /* are we configuring drive0? */
36501650	156	pci_read_config_dword(dev, basereg + 4, &reg);
1da177e4	157	timings \|= reg & 0x80000000; /* preserve PIO format bit */
36501650 BZ	158	pci_write_config_dword(dev, basereg + 4, timings);
	159	} else
	160	pci_write_config_dword(dev, basereg + 12, timings);
1da177e4 LT	161	}
1da177e4 LT	162
1da177e4 LT	163	/* Replacement for the standard ide_dma_end action in
	164	* dma_proc.
	165	*
	166	* returns 1 on error, 0 otherwise
	167	*/
5e37bdc0	168	static int sc1200_dma_end(ide_drive_t *drive)
1da177e4 LT	169	{
	170	ide_hwif_t *hwif = HWIF(drive);
	171	unsigned long dma_base = hwif->dma_base;
	172	byte dma_stat;
	173
	174	dma_stat = inb(dma_base+2); /* get DMA status */
	175
	176	if (!(dma_stat & 4))
	177	printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
	178	dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
	179
	180	outb(dma_stat\|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
	181	outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
	182
	183	drive->waiting_for_dma = 0;
	184	ide_destroy_dmatable(drive); /* purge DMA mappings */
	185
	186	return (dma_stat & 7) != 4; /* verify good DMA status */
	187	}
	188
	189	/*
26bcb879	190	* sc1200_set_pio_mode() handles setting of PIO modes
1da177e4 LT	191	* for both the chipset and drive.
	192	*
	193	* All existing BIOSs for this chipset guarantee that all drives
	194	* will have valid default PIO timings set up before we get here.
	195	*/
26bcb879 BZ	196
26bcb879 BZ	197	static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	198	{
1da177e4 LT	199	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	200	int mode = -1;
1da177e4 LT	201
a01ba401	202	/*
26bcb879	203	* bad abuse of ->set_pio_mode interface
a01ba401	204	*/
1da177e4 LT	205	switch (pio) {
	206	case 200: mode = XFER_UDMA_0; break;
	207	case 201: mode = XFER_UDMA_1; break;
	208	case 202: mode = XFER_UDMA_2; break;
	209	case 100: mode = XFER_MW_DMA_0; break;
	210	case 101: mode = XFER_MW_DMA_1; break;
	211	case 102: mode = XFER_MW_DMA_2; break;
	212	}
	213	if (mode != -1) {
	214	printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
4a546e04	215	ide_dma_off_quietly(drive);
f37aaf9e	216	if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
5e37bdc0	217	hwif->dma_ops->dma_host_set(drive, 1);
1da177e4 LT	218	return;
	219	}
	220
88b2b32b	221	sc1200_tunepio(drive, pio);
1da177e4 LT	222	}
1da177e4 LT	223
b86cc29d	224	#ifdef CONFIG_PM
7c0e2666 BZ	225	struct sc1200_saved_state {
	226	u32 regs[8];
	227	};
1da177e4	228
3bfffd97	229	static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
1da177e4	230	{
ca078bae	231	printk("SC1200: suspend(%u)\n", state.event);
1da177e4	232
7c0e2666 BZ	233	/*
	234	* we only save state when going from full power to less
	235	*/
ca078bae	236	if (state.event == PM_EVENT_ON) {
96776f3b BZ	237	struct ide_host *host = pci_get_drvdata(dev);
96776f3b BZ	238	struct sc1200_saved_state *ss = host->host_priv;
7c0e2666 BZ	239	unsigned int r;
7c0e2666 BZ	240
7c0e2666 BZ	241	/*
	242	* save timing registers
	243	* (this may be unnecessary if BIOS also does it)
	244	*/
	245	for (r = 0; r < 8; r++)
	246	pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	247	}
1da177e4 LT	248
1da177e4 LT	249	pci_disable_device(dev);
ca078bae	250	pci_set_power_state(dev, pci_choose_state(dev, state));
1da177e4 LT	251	return 0;
	252	}
	253
	254	static int sc1200_resume (struct pci_dev *dev)
	255	{
96776f3b BZ	256	struct ide_host *host = pci_get_drvdata(dev);
96776f3b BZ	257	struct sc1200_saved_state *ss = host->host_priv;
7c0e2666 BZ	258	unsigned int r;
7c0e2666 BZ	259	int i;
9d434813 JG	260
	261	i = pci_enable_device(dev);
	262	if (i)
	263	return i;
1da177e4	264
7c0e2666 BZ	265	/*
	266	* restore timing registers
	267	* (this may be unnecessary if BIOS also does it)
	268	*/
96776f3b BZ	269	for (r = 0; r < 8; r++)
96776f3b BZ	270	pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
7c0e2666	271
1da177e4 LT	272	return 0;
1da177e4 LT	273	}
b86cc29d	274	#endif
1da177e4	275
ac95beed BZ	276	static const struct ide_port_ops sc1200_port_ops = {
	277	.set_pio_mode = sc1200_set_pio_mode,
	278	.set_dma_mode = sc1200_set_dma_mode,
	279	.udma_filter = sc1200_udma_filter,
	280	};
	281
f37afdac BZ	282	static const struct ide_dma_ops sc1200_dma_ops = {
	283	.dma_host_set = ide_dma_host_set,
	284	.dma_setup = ide_dma_setup,
	285	.dma_exec_cmd = ide_dma_exec_cmd,
	286	.dma_start = ide_dma_start,
5e37bdc0	287	.dma_end = sc1200_dma_end,
f37afdac BZ	288	.dma_test_irq = ide_dma_test_irq,
	289	.dma_lost_irq = ide_dma_lost_irq,
	290	.dma_timeout = ide_dma_timeout,
5e37bdc0 BZ	291	};
5e37bdc0 BZ	292
85620436	293	static const struct ide_port_info sc1200_chipset __devinitdata = {
1da177e4	294	.name = "SC1200",
ac95beed	295	.port_ops = &sc1200_port_ops,
5e37bdc0	296	.dma_ops = &sc1200_dma_ops,
1c51361a BZ	297	.host_flags = IDE_HFLAG_SERIALIZE \|
1c51361a BZ	298	IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	299	IDE_HFLAG_ABUSE_DMA_MODES,
4099d143	300	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	301	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	302	.udma_mask = ATA_UDMA2,
1da177e4 LT	303	};
	304
	305	static int __devinit sc1200_init_one(struct pci_dev dev, const struct pci_device_id id)
	306	{
96776f3b BZ	307	struct sc1200_saved_state *ss = NULL;
	308	int rc;
	309
	310	#ifdef CONFIG_PM
	311	ss = kmalloc(sizeof(*ss), GFP_KERNEL);
	312	if (ss == NULL)
	313	return -ENOMEM;
	314	#endif
	315	rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
	316	if (rc)
	317	kfree(ss);
	318
	319	return rc;
1da177e4 LT	320	}
1da177e4 LT	321
9cbcc5e3 BZ	322	static const struct pci_device_id sc1200_pci_tbl[] = {
9cbcc5e3 BZ	323	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
1da177e4 LT	324	{ 0, },
	325	};
	326	MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
	327
	328	static struct pci_driver driver = {
	329	.name = "SC1200_IDE",
	330	.id_table = sc1200_pci_tbl,
	331	.probe = sc1200_init_one,
991f5e69	332	.remove = ide_pci_remove,
b86cc29d	333	#ifdef CONFIG_PM
1da177e4 LT	334	.suspend = sc1200_suspend,
1da177e4 LT	335	.resume = sc1200_resume,
b86cc29d	336	#endif
1da177e4 LT	337	};
1da177e4 LT	338
82ab1eec	339	static int __init sc1200_ide_init(void)
1da177e4 LT	340	{
	341	return ide_pci_register_driver(&driver);
	342	}
	343
991f5e69 BZ	344	static void __exit sc1200_ide_exit(void)
	345	{
	346	pci_unregister_driver(&driver);
	347	}
	348
1da177e4	349	module_init(sc1200_ide_init);
991f5e69	350	module_exit(sc1200_ide_exit);
1da177e4 LT	351
	352	MODULE_AUTHOR("Mark Lord");
	353	MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
	354	MODULE_LICENSE("GPL");