Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> |
5fd216bb BZ |
3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
4 | * | |
1da177e4 LT |
5 | * May be copied or modified under the terms of the GNU General Public License |
6 | * | |
7 | * Development of this chipset driver was funded | |
8 | * by the nice folks at National Semiconductor. | |
9 | * | |
10 | * Documentation: | |
11 | * Available from National Semiconductor | |
12 | */ | |
13 | ||
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
1da177e4 | 17 | #include <linux/hdreg.h> |
1da177e4 LT |
18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/ide.h> | |
21 | #include <linux/pm.h> | |
78829dd9 | 22 | |
1da177e4 | 23 | #include <asm/io.h> |
1da177e4 | 24 | |
ced3ec8a BZ |
25 | #define DRV_NAME "sc1200" |
26 | ||
1da177e4 LT |
27 | #define SC1200_REV_A 0x00 |
28 | #define SC1200_REV_B1 0x01 | |
29 | #define SC1200_REV_B3 0x02 | |
30 | #define SC1200_REV_C1 0x03 | |
31 | #define SC1200_REV_D1 0x04 | |
32 | ||
33 | #define PCI_CLK_33 0x00 | |
34 | #define PCI_CLK_48 0x01 | |
35 | #define PCI_CLK_66 0x02 | |
36 | #define PCI_CLK_33A 0x03 | |
37 | ||
38 | static unsigned short sc1200_get_pci_clock (void) | |
39 | { | |
40 | unsigned char chip_id, silicon_revision; | |
41 | unsigned int pci_clock; | |
42 | /* | |
43 | * Check the silicon revision, as not all versions of the chip | |
44 | * have the register with the fast PCI bus timings. | |
45 | */ | |
46 | chip_id = inb (0x903c); | |
47 | silicon_revision = inb (0x903d); | |
48 | ||
49 | // Read the fast pci clock frequency | |
50 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { | |
51 | pci_clock = PCI_CLK_33; | |
52 | } else { | |
53 | // check clock generator configuration (cfcc) | |
54 | // the clock is in bits 8 and 9 of this word | |
55 | ||
56 | pci_clock = inw (0x901e); | |
57 | pci_clock >>= 8; | |
58 | pci_clock &= 0x03; | |
59 | if (pci_clock == PCI_CLK_33A) | |
60 | pci_clock = PCI_CLK_33; | |
61 | } | |
62 | return pci_clock; | |
63 | } | |
64 | ||
1da177e4 LT |
65 | /* |
66 | * Here are the standard PIO mode 0-4 timings for each "format". | |
67 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
68 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
69 | */ | |
70 | static const unsigned int sc1200_pio_timings[4][5] = | |
71 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz | |
72 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz | |
73 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz | |
74 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz | |
75 | ||
76 | /* | |
77 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. | |
78 | */ | |
79 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) | |
80 | ||
3c3f5d2c BZ |
81 | static void sc1200_tunepio(ide_drive_t *drive, u8 pio) |
82 | { | |
83 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 84 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
3c3f5d2c BZ |
85 | unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; |
86 | ||
87 | pci_read_config_dword(pdev, basereg + 4, &format); | |
88 | format = (format >> 31) & 1; | |
89 | if (format) | |
90 | format += sc1200_get_pci_clock(); | |
91 | pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), | |
92 | sc1200_pio_timings[format][pio]); | |
93 | } | |
94 | ||
5fd216bb BZ |
95 | /* |
96 | * The SC1200 specifies that two drives sharing a cable cannot mix | |
97 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
98 | * different timings can still be chosen for each drive. We could | |
99 | * set the appropriate timing bits on the fly, but that might be | |
100 | * a bit confusing. So, for now we statically handle this requirement | |
101 | * by looking at our mate drive to see what it is capable of, before | |
102 | * choosing a mode for our own drive. | |
103 | */ | |
104 | static u8 sc1200_udma_filter(ide_drive_t *drive) | |
1da177e4 | 105 | { |
5fd216bb BZ |
106 | ide_hwif_t *hwif = drive->hwif; |
107 | ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; | |
108 | struct hd_driveid *mateid = mate->id; | |
109 | u8 mask = hwif->ultra_mask; | |
110 | ||
111 | if (mate->present == 0) | |
112 | goto out; | |
113 | ||
114 | if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { | |
115 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) | |
116 | goto out; | |
117 | if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) | |
118 | mask = 0; | |
1da177e4 | 119 | } |
5fd216bb BZ |
120 | out: |
121 | return mask; | |
1da177e4 LT |
122 | } |
123 | ||
88b2b32b | 124 | static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode) |
1da177e4 LT |
125 | { |
126 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 127 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
128 | int unit = drive->select.b.unit; |
129 | unsigned int reg, timings; | |
130 | unsigned short pci_clock; | |
131 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
132 | ||
4eed504d BZ |
133 | static const u32 udma_timing[3][3] = { |
134 | { 0x00921250, 0x00911140, 0x00911030 }, | |
135 | { 0x00932470, 0x00922260, 0x00922140 }, | |
136 | { 0x009436a1, 0x00933481, 0x00923261 }, | |
137 | }; | |
138 | ||
139 | static const u32 mwdma_timing[3][3] = { | |
140 | { 0x00077771, 0x00012121, 0x00002020 }, | |
141 | { 0x000bbbb2, 0x00024241, 0x00013131 }, | |
142 | { 0x000ffff3, 0x00035352, 0x00015151 }, | |
143 | }; | |
144 | ||
1da177e4 LT |
145 | pci_clock = sc1200_get_pci_clock(); |
146 | ||
147 | /* | |
1da177e4 LT |
148 | * Note that each DMA mode has several timings associated with it. |
149 | * The correct timing depends on the fast PCI clock freq. | |
150 | */ | |
4eed504d BZ |
151 | |
152 | if (mode >= XFER_UDMA_0) | |
153 | timings = udma_timing[pci_clock][mode - XFER_UDMA_0]; | |
154 | else | |
155 | timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0]; | |
1da177e4 LT |
156 | |
157 | if (unit == 0) { /* are we configuring drive0? */ | |
36501650 | 158 | pci_read_config_dword(dev, basereg + 4, ®); |
1da177e4 | 159 | timings |= reg & 0x80000000; /* preserve PIO format bit */ |
36501650 BZ |
160 | pci_write_config_dword(dev, basereg + 4, timings); |
161 | } else | |
162 | pci_write_config_dword(dev, basereg + 12, timings); | |
1da177e4 LT |
163 | } |
164 | ||
1da177e4 LT |
165 | /* Replacement for the standard ide_dma_end action in |
166 | * dma_proc. | |
167 | * | |
168 | * returns 1 on error, 0 otherwise | |
169 | */ | |
5e37bdc0 | 170 | static int sc1200_dma_end(ide_drive_t *drive) |
1da177e4 LT |
171 | { |
172 | ide_hwif_t *hwif = HWIF(drive); | |
173 | unsigned long dma_base = hwif->dma_base; | |
174 | byte dma_stat; | |
175 | ||
176 | dma_stat = inb(dma_base+2); /* get DMA status */ | |
177 | ||
178 | if (!(dma_stat & 4)) | |
179 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", | |
180 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); | |
181 | ||
182 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ | |
183 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ | |
184 | ||
185 | drive->waiting_for_dma = 0; | |
186 | ide_destroy_dmatable(drive); /* purge DMA mappings */ | |
187 | ||
188 | return (dma_stat & 7) != 4; /* verify good DMA status */ | |
189 | } | |
190 | ||
191 | /* | |
26bcb879 | 192 | * sc1200_set_pio_mode() handles setting of PIO modes |
1da177e4 LT |
193 | * for both the chipset and drive. |
194 | * | |
195 | * All existing BIOSs for this chipset guarantee that all drives | |
196 | * will have valid default PIO timings set up before we get here. | |
197 | */ | |
26bcb879 BZ |
198 | |
199 | static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
200 | { |
201 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
202 | int mode = -1; |
203 | ||
a01ba401 | 204 | /* |
26bcb879 | 205 | * bad abuse of ->set_pio_mode interface |
a01ba401 | 206 | */ |
1da177e4 LT |
207 | switch (pio) { |
208 | case 200: mode = XFER_UDMA_0; break; | |
209 | case 201: mode = XFER_UDMA_1; break; | |
210 | case 202: mode = XFER_UDMA_2; break; | |
211 | case 100: mode = XFER_MW_DMA_0; break; | |
212 | case 101: mode = XFER_MW_DMA_1; break; | |
213 | case 102: mode = XFER_MW_DMA_2; break; | |
214 | } | |
215 | if (mode != -1) { | |
216 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); | |
4a546e04 | 217 | ide_dma_off_quietly(drive); |
f37aaf9e | 218 | if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma) |
5e37bdc0 | 219 | hwif->dma_ops->dma_host_set(drive, 1); |
1da177e4 LT |
220 | return; |
221 | } | |
222 | ||
88b2b32b | 223 | sc1200_tunepio(drive, pio); |
1da177e4 LT |
224 | } |
225 | ||
b86cc29d | 226 | #ifdef CONFIG_PM |
7c0e2666 BZ |
227 | struct sc1200_saved_state { |
228 | u32 regs[8]; | |
229 | }; | |
1da177e4 | 230 | |
3bfffd97 | 231 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
1da177e4 | 232 | { |
ca078bae | 233 | printk("SC1200: suspend(%u)\n", state.event); |
1da177e4 | 234 | |
7c0e2666 BZ |
235 | /* |
236 | * we only save state when going from full power to less | |
237 | */ | |
ca078bae | 238 | if (state.event == PM_EVENT_ON) { |
96776f3b BZ |
239 | struct ide_host *host = pci_get_drvdata(dev); |
240 | struct sc1200_saved_state *ss = host->host_priv; | |
7c0e2666 BZ |
241 | unsigned int r; |
242 | ||
7c0e2666 BZ |
243 | /* |
244 | * save timing registers | |
245 | * (this may be unnecessary if BIOS also does it) | |
246 | */ | |
247 | for (r = 0; r < 8; r++) | |
248 | pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]); | |
249 | } | |
1da177e4 LT |
250 | |
251 | pci_disable_device(dev); | |
ca078bae | 252 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
1da177e4 LT |
253 | return 0; |
254 | } | |
255 | ||
256 | static int sc1200_resume (struct pci_dev *dev) | |
257 | { | |
96776f3b BZ |
258 | struct ide_host *host = pci_get_drvdata(dev); |
259 | struct sc1200_saved_state *ss = host->host_priv; | |
7c0e2666 BZ |
260 | unsigned int r; |
261 | int i; | |
9d434813 JG |
262 | |
263 | i = pci_enable_device(dev); | |
264 | if (i) | |
265 | return i; | |
1da177e4 | 266 | |
7c0e2666 BZ |
267 | /* |
268 | * restore timing registers | |
269 | * (this may be unnecessary if BIOS also does it) | |
270 | */ | |
96776f3b BZ |
271 | for (r = 0; r < 8; r++) |
272 | pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]); | |
7c0e2666 | 273 | |
1da177e4 LT |
274 | return 0; |
275 | } | |
b86cc29d | 276 | #endif |
1da177e4 | 277 | |
ac95beed BZ |
278 | static const struct ide_port_ops sc1200_port_ops = { |
279 | .set_pio_mode = sc1200_set_pio_mode, | |
280 | .set_dma_mode = sc1200_set_dma_mode, | |
281 | .udma_filter = sc1200_udma_filter, | |
282 | }; | |
283 | ||
f37afdac BZ |
284 | static const struct ide_dma_ops sc1200_dma_ops = { |
285 | .dma_host_set = ide_dma_host_set, | |
286 | .dma_setup = ide_dma_setup, | |
287 | .dma_exec_cmd = ide_dma_exec_cmd, | |
288 | .dma_start = ide_dma_start, | |
5e37bdc0 | 289 | .dma_end = sc1200_dma_end, |
f37afdac BZ |
290 | .dma_test_irq = ide_dma_test_irq, |
291 | .dma_lost_irq = ide_dma_lost_irq, | |
292 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
293 | }; |
294 | ||
85620436 | 295 | static const struct ide_port_info sc1200_chipset __devinitdata = { |
ced3ec8a | 296 | .name = DRV_NAME, |
ac95beed | 297 | .port_ops = &sc1200_port_ops, |
5e37bdc0 | 298 | .dma_ops = &sc1200_dma_ops, |
1c51361a BZ |
299 | .host_flags = IDE_HFLAG_SERIALIZE | |
300 | IDE_HFLAG_POST_SET_MODE | | |
5e71d9c5 | 301 | IDE_HFLAG_ABUSE_DMA_MODES, |
4099d143 | 302 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
303 | .mwdma_mask = ATA_MWDMA2, |
304 | .udma_mask = ATA_UDMA2, | |
1da177e4 LT |
305 | }; |
306 | ||
307 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
308 | { | |
96776f3b BZ |
309 | struct sc1200_saved_state *ss = NULL; |
310 | int rc; | |
311 | ||
312 | #ifdef CONFIG_PM | |
313 | ss = kmalloc(sizeof(*ss), GFP_KERNEL); | |
314 | if (ss == NULL) | |
315 | return -ENOMEM; | |
316 | #endif | |
317 | rc = ide_pci_init_one(dev, &sc1200_chipset, ss); | |
318 | if (rc) | |
319 | kfree(ss); | |
320 | ||
321 | return rc; | |
1da177e4 LT |
322 | } |
323 | ||
9cbcc5e3 BZ |
324 | static const struct pci_device_id sc1200_pci_tbl[] = { |
325 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, | |
1da177e4 LT |
326 | { 0, }, |
327 | }; | |
328 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); | |
329 | ||
330 | static struct pci_driver driver = { | |
331 | .name = "SC1200_IDE", | |
332 | .id_table = sc1200_pci_tbl, | |
333 | .probe = sc1200_init_one, | |
991f5e69 | 334 | .remove = ide_pci_remove, |
b86cc29d | 335 | #ifdef CONFIG_PM |
1da177e4 LT |
336 | .suspend = sc1200_suspend, |
337 | .resume = sc1200_resume, | |
b86cc29d | 338 | #endif |
1da177e4 LT |
339 | }; |
340 | ||
82ab1eec | 341 | static int __init sc1200_ide_init(void) |
1da177e4 LT |
342 | { |
343 | return ide_pci_register_driver(&driver); | |
344 | } | |
345 | ||
991f5e69 BZ |
346 | static void __exit sc1200_ide_exit(void) |
347 | { | |
348 | pci_unregister_driver(&driver); | |
349 | } | |
350 | ||
1da177e4 | 351 | module_init(sc1200_ide_init); |
991f5e69 | 352 | module_exit(sc1200_ide_exit); |
1da177e4 LT |
353 | |
354 | MODULE_AUTHOR("Mark Lord"); | |
355 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); | |
356 | MODULE_LICENSE("GPL"); |