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ide: add ->read_altstatus method
[deliverable/linux.git] / drivers / ide / pci / scc_pata.c
CommitLineData
bde18a2e
KI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35#define SCC_PATA_NAME "scc IDE"
36
37#define TDVHSEL_MASTER 0x00000001
38#define TDVHSEL_SLAVE 0x00000004
39
40#define MODE_JCUSFEN 0x00000080
41
42#define CCKCTRL_ATARESET 0x00040000
43#define CCKCTRL_BUFCNT 0x00020000
44#define CCKCTRL_CRST 0x00010000
45#define CCKCTRL_OCLKEN 0x00000100
46#define CCKCTRL_ATACLKOEN 0x00000002
47#define CCKCTRL_LCLKEN 0x00000001
48
49#define QCHCD_IOS_SS 0x00000001
50
51#define QCHSD_STPDIAG 0x00020000
52
53#define INTMASK_MSK 0xD1000012
54#define INTSTS_SERROR 0x80000000
55#define INTSTS_PRERR 0x40000000
56#define INTSTS_RERR 0x10000000
57#define INTSTS_ICERR 0x01000000
58#define INTSTS_BMSINT 0x00000010
59#define INTSTS_BMHE 0x00000008
60#define INTSTS_IOIRQS 0x00000004
61#define INTSTS_INTRQ 0x00000002
62#define INTSTS_ACTEINT 0x00000001
63
64#define ECMODE_VALUE 0x01
65
66static struct scc_ports {
67 unsigned long ctl, dma;
589b0626 68 ide_hwif_t *hwif; /* for removing port from system */
bde18a2e
KI		 69} scc_ports[MAX_HWIFS];
70
71/* PIO transfer mode table */
72/* JCHST */
73static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76};
77
78/* JCHHT */
79static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82};
83
84/* JCHCT */
85static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88};
89
90
91/* DMA transfer mode table */
92/* JCHDCTM/JCHDCTS */
93static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96};
97
98/* JCSTWTM/JCSTWTS */
99static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102};
103
104/* JCTSS */
105static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108};
109
110/* JCENVT */
111static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114};
115
116/* JCACTSELS/JCACTSELM */
117static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120};
121
122
123static u8 scc_ide_inb(unsigned long port)
124{
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127}
128
c6dfa867
BZ		 129static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
130{
131 out_be32((void *)hwif->io_ports.command_addr, cmd);
132 eieio();
133 in_be32((void *)(hwif->dma_base + 0x01c));
134 eieio();
135}
136
b73c7ee2
BZ		 137static u8 scc_read_status(ide_hwif_t *hwif)
138{
139 return (u8)in_be32((void *)hwif->io_ports.status_addr);
140}
141
1f6d8a0f
BZ		 142static u8 scc_read_altstatus(ide_hwif_t *hwif)
143{
144 return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
145}
146
b2f951aa
BZ		 147static u8 scc_read_sff_dma_status(ide_hwif_t *hwif)
148{
cab7f8ed 149 return (u8)in_be32((void *)(hwif->dma_base + 4));
b2f951aa
BZ		 150}
151
bde18a2e
KI		 152static void scc_ide_insw(unsigned long port, void *addr, u32 count)
153{
154 u16 *ptr = (u16 *)addr;
155 while (count--) {
156 *ptr++ = le16_to_cpu(in_be32((void*)port));
157 }
158}
159
160static void scc_ide_insl(unsigned long port, void *addr, u32 count)
161{
162 u16 *ptr = (u16 *)addr;
163 while (count--) {
164 *ptr++ = le16_to_cpu(in_be32((void*)port));
165 *ptr++ = le16_to_cpu(in_be32((void*)port));
166 }
167}
168
169static void scc_ide_outb(u8 addr, unsigned long port)
170{
171 out_be32((void*)port, addr);
172}
173
f8c4bd0a 174static void scc_ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port)
bde18a2e 175{
bde18a2e 176 out_be32((void*)port, addr);
f644d47a 177 eieio();
bde18a2e 178 in_be32((void*)(hwif->dma_base + 0x01c));
f644d47a 179 eieio();
bde18a2e
KI		 180}
181
182static void
183scc_ide_outsw(unsigned long port, void *addr, u32 count)
184{
185 u16 *ptr = (u16 *)addr;
186 while (count--) {
187 out_be32((void*)port, cpu_to_le16(*ptr++));
188 }
189}
190
191static void
192scc_ide_outsl(unsigned long port, void *addr, u32 count)
193{
194 u16 *ptr = (u16 *)addr;
195 while (count--) {
196 out_be32((void*)port, cpu_to_le16(*ptr++));
197 out_be32((void*)port, cpu_to_le16(*ptr++));
198 }
199}
200
bde18a2e 201/**
88b2b32b
BZ		 202 * scc_set_pio_mode - set host controller for PIO mode
203 * @drive: drive
204 * @pio: PIO mode number
bde18a2e
KI		 205 *
206 * Load the timing settings for this device mode into the
207 * controller.
208 */
209
88b2b32b 210static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
bde18a2e
KI		 211{
212 ide_hwif_t *hwif = HWIF(drive);
213 struct scc_ports *ports = ide_get_hwifdata(hwif);
214 unsigned long ctl_base = ports->ctl;
215 unsigned long cckctrl_port = ctl_base + 0xff0;
216 unsigned long piosht_port = ctl_base + 0x000;
217 unsigned long pioct_port = ctl_base + 0x004;
218 unsigned long reg;
bde18a2e
KI		 219 int offset;
220
0ecdca26 221 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 222 if (reg & CCKCTRL_ATACLKOEN) {
223 offset = 1; /* 133MHz */
224 } else {
225 offset = 0; /* 100MHz */
226 }
3fcece66 227 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
0ecdca26 228 out_be32((void __iomem *)piosht_port, reg);
3fcece66 229 reg = JCHCTtbl[offset][pio];
0ecdca26 230 out_be32((void __iomem *)pioct_port, reg);
3fcece66 231}
bde18a2e 232
bde18a2e 233/**
88b2b32b
BZ		 234 * scc_set_dma_mode - set host controller for DMA mode
235 * @drive: drive
236 * @speed: DMA mode
bde18a2e
KI		 237 *
238 * Load the timing settings for this device mode into the
239 * controller.
240 */
241
88b2b32b 242static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
bde18a2e
KI		 243{
244 ide_hwif_t *hwif = HWIF(drive);
bde18a2e
KI		 245 struct scc_ports *ports = ide_get_hwifdata(hwif);
246 unsigned long ctl_base = ports->ctl;
247 unsigned long cckctrl_port = ctl_base + 0xff0;
248 unsigned long mdmact_port = ctl_base + 0x008;
249 unsigned long mcrcst_port = ctl_base + 0x00c;
250 unsigned long sdmact_port = ctl_base + 0x010;
251 unsigned long scrcst_port = ctl_base + 0x014;
252 unsigned long udenvt_port = ctl_base + 0x018;
253 unsigned long tdvhsel_port = ctl_base + 0x020;
254 int is_slave = (&hwif->drives[1] == drive);
255 int offset, idx;
256 unsigned long reg;
257 unsigned long jcactsel;
258
0ecdca26 259 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 260 if (reg & CCKCTRL_ATACLKOEN) {
261 offset = 1; /* 133MHz */
262 } else {
263 offset = 0; /* 100MHz */
264 }
265
4db90a14 266 idx = speed - XFER_UDMA_0;
bde18a2e
KI		 267
268 jcactsel = JCACTSELtbl[offset][idx];
269 if (is_slave) {
0ecdca26
BZ		 270 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
271 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
272 jcactsel = jcactsel << 2;
273 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
bde18a2e 274 } else {
0ecdca26
BZ		 275 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
276 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
277 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
bde18a2e
KI		 278 }
279 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
0ecdca26 280 out_be32((void __iomem *)udenvt_port, reg);
bde18a2e
KI		 281}
282
669185e9
BZ		 283static void scc_dma_host_set(ide_drive_t *drive, int on)
284{
285 ide_hwif_t *hwif = drive->hwif;
286 u8 unit = (drive->select.b.unit & 0x01);
cab7f8ed 287 u8 dma_stat = scc_ide_inb(hwif->dma_base + 4);
669185e9
BZ		 288
289 if (on)
290 dma_stat |= (1 << (5 + unit));
291 else
292 dma_stat &= ~(1 << (5 + unit));
293
cab7f8ed 294 scc_ide_outb(dma_stat, hwif->dma_base + 4);
669185e9
BZ		 295}
296
0ecdca26
BZ		 297/**
298 * scc_ide_dma_setup - begin a DMA phase
299 * @drive: target device
300 *
301 * Build an IDE DMA PRD (IDE speak for scatter gather table)
302 * and then set up the DMA transfer registers.
303 *
304 * Returns 0 on success. If a PIO fallback is required then 1
305 * is returned.
306 */
307
308static int scc_dma_setup(ide_drive_t *drive)
309{
310 ide_hwif_t *hwif = drive->hwif;
311 struct request *rq = HWGROUP(drive)->rq;
312 unsigned int reading;
313 u8 dma_stat;
314
315 if (rq_data_dir(rq))
316 reading = 0;
317 else
318 reading = 1 << 3;
319
320 /* fall back to pio! */
321 if (!ide_build_dmatable(drive, rq)) {
322 ide_map_sg(drive, rq);
323 return 1;
324 }
325
326 /* PRD table */
55224bc8 327 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
0ecdca26
BZ		 328
329 /* specify r/w */
cab7f8ed 330 out_be32((void __iomem *)hwif->dma_base, reading);
0ecdca26 331
cab7f8ed
BZ		 332 /* read DMA status for INTR & ERROR flags */
333 dma_stat = in_be32((void __iomem *)(hwif->dma_base + 4));
0ecdca26
BZ		 334
335 /* clear INTR & ERROR flags */
cab7f8ed 336 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
0ecdca26
BZ		 337 drive->waiting_for_dma = 1;
338 return 0;
339}
340
669185e9
BZ		 341static void scc_dma_start(ide_drive_t *drive)
342{
343 ide_hwif_t *hwif = drive->hwif;
cab7f8ed 344 u8 dma_cmd = scc_ide_inb(hwif->dma_base);
669185e9
BZ		 345
346 /* start DMA */
cab7f8ed 347 scc_ide_outb(dma_cmd | 1, hwif->dma_base);
669185e9
BZ		 348 hwif->dma = 1;
349 wmb();
350}
351
352static int __scc_dma_end(ide_drive_t *drive)
353{
354 ide_hwif_t *hwif = drive->hwif;
355 u8 dma_stat, dma_cmd;
356
357 drive->waiting_for_dma = 0;
358 /* get DMA command mode */
cab7f8ed 359 dma_cmd = scc_ide_inb(hwif->dma_base);
669185e9 360 /* stop DMA */
cab7f8ed 361 scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
669185e9 362 /* get DMA status */
cab7f8ed 363 dma_stat = scc_ide_inb(hwif->dma_base + 4);
669185e9 364 /* clear the INTR & ERROR bits */
cab7f8ed 365 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
669185e9
BZ		 366 /* purge DMA mappings */
367 ide_destroy_dmatable(drive);
368 /* verify good DMA status */
369 hwif->dma = 0;
370 wmb();
371 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
372}
0ecdca26 373
bde18a2e 374/**
5e37bdc0 375 * scc_dma_end - Stop DMA
bde18a2e
KI		 376 * @drive: IDE drive
377 *
378 * Check and clear INT Status register.
669185e9 379 * Then call __scc_dma_end().
bde18a2e
KI		 380 */
381
5e37bdc0 382static int scc_dma_end(ide_drive_t *drive)
bde18a2e
KI		 383{
384 ide_hwif_t *hwif = HWIF(drive);
cab7f8ed 385 void __iomem *dma_base = (void __iomem *)hwif->dma_base;
bde18a2e
KI		 386 unsigned long intsts_port = hwif->dma_base + 0x014;
387 u32 reg;
4ae41ff8
KI		 388 int dma_stat, data_loss = 0;
389 static int retry = 0;
390
391 /* errata A308 workaround: Step5 (check data loss) */
392 /* We don't check non ide_disk because it is limited to UDMA4 */
4c3032d8 393 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
23579a2a 394 & ERR_STAT) &&
4ae41ff8
KI		 395 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
396 reg = in_be32((void __iomem *)intsts_port);
397 if (!(reg & INTSTS_ACTEINT)) {
398 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
399 drive->name);
400 data_loss = 1;
401 if (retry++) {
402 struct request *rq = HWGROUP(drive)->rq;
403 int unit;
404 /* ERROR_RESET and drive->crc_count are needed
405 * to reduce DMA transfer mode in retry process.
406 */
407 if (rq)
408 rq->errors |= ERROR_RESET;
409 for (unit = 0; unit < MAX_DRIVES; unit++) {
410 ide_drive_t *drive = &hwif->drives[unit];
411 drive->crc_count++;
412 }
413 }
414 }
415 }
bde18a2e
KI		 416
417 while (1) {
0ecdca26 418 reg = in_be32((void __iomem *)intsts_port);
bde18a2e
KI		 419
420 if (reg & INTSTS_SERROR) {
421 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
0ecdca26 422 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
bde18a2e 423
cab7f8ed 424 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 425 continue;
426 }
427
428 if (reg & INTSTS_PRERR) {
429 u32 maea0, maec0;
430 unsigned long ctl_base = hwif->config_data;
431
0ecdca26
BZ		 432 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
433 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
bde18a2e
KI		 434
435 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
436
0ecdca26 437 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
bde18a2e 438
cab7f8ed 439 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 440 continue;
441 }
442
443 if (reg & INTSTS_RERR) {
444 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
0ecdca26 445 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
bde18a2e 446
cab7f8ed 447 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 448 continue;
449 }
450
451 if (reg & INTSTS_ICERR) {
cab7f8ed 452 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 453
454 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
0ecdca26 455 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
bde18a2e
KI		 456 continue;
457 }
458
459 if (reg & INTSTS_BMSINT) {
460 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
0ecdca26 461 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
bde18a2e
KI		 462
463 ide_do_reset(drive);
464 continue;
465 }
466
467 if (reg & INTSTS_BMHE) {
0ecdca26 468 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
bde18a2e
KI		 469 continue;
470 }
471
472 if (reg & INTSTS_ACTEINT) {
0ecdca26 473 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
bde18a2e
KI		 474 continue;
475 }
476
477 if (reg & INTSTS_IOIRQS) {
0ecdca26 478 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
bde18a2e
KI		 479 continue;
480 }
481 break;
482 }
483
669185e9 484 dma_stat = __scc_dma_end(drive);
4ae41ff8
KI		 485 if (data_loss)
486 dma_stat |= 2; /* emulate DMA error (to retry command) */
487 return dma_stat;
bde18a2e
KI		 488}
489
06a9952b
AI		 490/* returns 1 if dma irq issued, 0 otherwise */
491static int scc_dma_test_irq(ide_drive_t *drive)
492{
4ae41ff8
KI		 493 ide_hwif_t *hwif = HWIF(drive);
494 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
06a9952b 495
4ae41ff8 496 /* SCC errata A252,A308 workaround: Step4 */
4c3032d8 497 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
23579a2a 498 & ERR_STAT) &&
4ae41ff8 499 (int_stat & INTSTS_INTRQ))
06a9952b
AI		 500 return 1;
501
4ae41ff8
KI		 502 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
503 if (int_stat & INTSTS_IOIRQS)
06a9952b
AI		 504 return 1;
505
506 if (!drive->waiting_for_dma)
507 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
eb63963a 508 drive->name, __func__);
06a9952b
AI		 509 return 0;
510}
511
4ae41ff8
KI		 512static u8 scc_udma_filter(ide_drive_t *drive)
513{
514 ide_hwif_t *hwif = drive->hwif;
515 u8 mask = hwif->ultra_mask;
516
517 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
518 if ((drive->media != ide_disk) && (mask & 0xE0)) {
519 printk(KERN_INFO "%s: limit %s to UDMA4\n",
520 SCC_PATA_NAME, drive->name);
5f8b6c34 521 mask = ATA_UDMA4;
4ae41ff8
KI		 522 }
523
524 return mask;
525}
526
bde18a2e
KI		 527/**
528 * setup_mmio_scc - map CTRL/BMID region
529 * @dev: PCI device we are configuring
530 * @name: device name
531 *
532 */
533
534static int setup_mmio_scc (struct pci_dev *dev, const char *name)
535{
536 unsigned long ctl_base = pci_resource_start(dev, 0);
537 unsigned long dma_base = pci_resource_start(dev, 1);
538 unsigned long ctl_size = pci_resource_len(dev, 0);
539 unsigned long dma_size = pci_resource_len(dev, 1);
0bd8496b
AV		 540 void __iomem *ctl_addr;
541 void __iomem *dma_addr;
0d1bad21 542 int i, ret;
bde18a2e
KI		 543
544 for (i = 0; i < MAX_HWIFS; i++) {
545 if (scc_ports[i].ctl == 0)
546 break;
547 }
548 if (i >= MAX_HWIFS)
549 return -ENOMEM;
550
0d1bad21
BZ		 551 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
552 if (ret < 0) {
553 printk(KERN_ERR "%s: can't reserve resources\n", name);
554 return ret;
bde18a2e
KI		 555 }
556
557 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
0d1bad21 558 goto fail_0;
bde18a2e
KI		 559
560 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
0d1bad21 561 goto fail_1;
bde18a2e
KI		 562
563 pci_set_master(dev);
564 scc_ports[i].ctl = (unsigned long)ctl_addr;
565 scc_ports[i].dma = (unsigned long)dma_addr;
566 pci_set_drvdata(dev, (void *) &scc_ports[i]);
567
568 return 1;
569
bde18a2e 570 fail_1:
0d1bad21 571 iounmap(ctl_addr);
bde18a2e
KI		 572 fail_0:
573 return -ENOMEM;
574}
575
3d53ba87
AI		 576static int scc_ide_setup_pci_device(struct pci_dev *dev,
577 const struct ide_port_info *d)
578{
579 struct scc_ports *ports = pci_get_drvdata(dev);
580 ide_hwif_t *hwif = NULL;
c97c6aca 581 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
3d53ba87
AI		 582 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
583 int i;
584
eb3aff55
BZ		 585 hwif = ide_find_port_slot(d);
586 if (hwif == NULL)
3d53ba87 587 return -ENOMEM;
3d53ba87
AI		 588
589 memset(&hw, 0, sizeof(hw));
4c3032d8
BZ		 590 for (i = 0; i <= 8; i++)
591 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
3d53ba87
AI		 592 hw.irq = dev->irq;
593 hw.dev = &dev->dev;
594 hw.chipset = ide_pci;
3d53ba87
AI		 595
596 idx[0] = hwif->index;
597
c97c6aca 598 ide_device_add(idx, d, hws);
3d53ba87
AI		 599
600 return 0;
601}
602
bde18a2e
KI		 603/**
604 * init_setup_scc - set up an SCC PATA Controller
605 * @dev: PCI device
039788e1 606 * @d: IDE port info
bde18a2e
KI		 607 *
608 * Perform the initial set up for this device.
609 */
610
039788e1 611static int __devinit init_setup_scc(struct pci_dev *dev,
85620436 612 const struct ide_port_info *d)
bde18a2e
KI		 613{
614 unsigned long ctl_base;
615 unsigned long dma_base;
616 unsigned long cckctrl_port;
617 unsigned long intmask_port;
618 unsigned long mode_port;
619 unsigned long ecmode_port;
620 unsigned long dma_status_port;
621 u32 reg = 0;
622 struct scc_ports *ports;
623 int rc;
624
3d53ba87
AI		 625 rc = pci_enable_device(dev);
626 if (rc)
627 goto end;
628
bde18a2e 629 rc = setup_mmio_scc(dev, d->name);
3d53ba87
AI		 630 if (rc < 0)
631 goto end;
bde18a2e
KI		 632
633 ports = pci_get_drvdata(dev);
634 ctl_base = ports->ctl;
635 dma_base = ports->dma;
636 cckctrl_port = ctl_base + 0xff0;
637 intmask_port = dma_base + 0x010;
638 mode_port = ctl_base + 0x024;
639 ecmode_port = ctl_base + 0xf00;
640 dma_status_port = dma_base + 0x004;
641
642 /* controller initialization */
643 reg = 0;
644 out_be32((void*)cckctrl_port, reg);
645 reg |= CCKCTRL_ATACLKOEN;
646 out_be32((void*)cckctrl_port, reg);
647 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
648 out_be32((void*)cckctrl_port, reg);
649 reg |= CCKCTRL_CRST;
650 out_be32((void*)cckctrl_port, reg);
651
652 for (;;) {
653 reg = in_be32((void*)cckctrl_port);
654 if (reg & CCKCTRL_CRST)
655 break;
656 udelay(5000);
657 }
658
659 reg |= CCKCTRL_ATARESET;
660 out_be32((void*)cckctrl_port, reg);
661
662 out_be32((void*)ecmode_port, ECMODE_VALUE);
663 out_be32((void*)mode_port, MODE_JCUSFEN);
664 out_be32((void*)intmask_port, INTMASK_MSK);
665
3d53ba87
AI		 666 rc = scc_ide_setup_pci_device(dev, d);
667
668 end:
669 return rc;
bde18a2e
KI		 670}
671
db2432c4
BZ		 672static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
673{
674 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
675 struct ide_taskfile *tf = &task->tf;
676 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
677
678 if (task->tf_flags & IDE_TFLAG_FLAGGED)
679 HIHI = 0xFF;
680
db2432c4 681 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
7c0daf26
BZ		 682 out_be32((void *)io_ports->data_addr,
683 (tf->hob_data << 8) | tf->data);
db2432c4
BZ		 684
685 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
686 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
687 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
688 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
689 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
690 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
691 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
692 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
693 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
694 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
695
696 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
697 scc_ide_outb(tf->feature, io_ports->feature_addr);
698 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
699 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
700 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
701 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
702 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
703 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
704 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
705 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
706
707 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
708 scc_ide_outb((tf->device & HIHI) | drive->select.all,
709 io_ports->device_addr);
710}
711
712static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
713{
714 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
715 struct ide_taskfile *tf = &task->tf;
716
717 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
7c0daf26 718 u16 data = (u16)in_be32((void *)io_ports->data_addr);
db2432c4
BZ		 719
720 tf->data = data & 0xff;
721 tf->hob_data = (data >> 8) & 0xff;
722 }
723
724 /* be sure we're looking at the low order bits */
ff074883 725 scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
db2432c4
BZ		 726
727 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
728 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
729 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
730 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
731 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
732 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
733 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
734 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
735 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
736 tf->device = scc_ide_inb(io_ports->device_addr);
737
738 if (task->tf_flags & IDE_TFLAG_LBA48) {
ff074883 739 scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
db2432c4
BZ		 740
741 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
742 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
743 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
744 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
745 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
746 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
747 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
748 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
749 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
750 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
751 }
752}
753
efa3db1b
BZ		 754static void scc_input_data(ide_drive_t *drive, struct request *rq,
755 void *buf, unsigned int len)
756{
757 unsigned long data_addr = drive->hwif->io_ports.data_addr;
758
759 len++;
760
761 if (drive->io_32bit) {
762 scc_ide_insl(data_addr, buf, len / 4);
763
764 if ((len & 3) >= 2)
765 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
766 } else
767 scc_ide_insw(data_addr, buf, len / 2);
768}
769
770static void scc_output_data(ide_drive_t *drive, struct request *rq,
771 void *buf, unsigned int len)
772{
773 unsigned long data_addr = drive->hwif->io_ports.data_addr;
774
775 len++;
776
777 if (drive->io_32bit) {
778 scc_ide_outsl(data_addr, buf, len / 4);
779
780 if ((len & 3) >= 2)
781 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
782 } else
783 scc_ide_outsw(data_addr, buf, len / 2);
784}
785
bde18a2e
KI		 786/**
787 * init_mmio_iops_scc - set up the iops for MMIO
788 * @hwif: interface to set up
789 *
790 */
791
792static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
793{
36501650 794 struct pci_dev *dev = to_pci_dev(hwif->dev);
bde18a2e
KI		 795 struct scc_ports *ports = pci_get_drvdata(dev);
796 unsigned long dma_base = ports->dma;
797
798 ide_set_hwifdata(hwif, ports);
799
c6dfa867 800 hwif->exec_command = scc_exec_command;
b73c7ee2 801 hwif->read_status = scc_read_status;
1f6d8a0f 802 hwif->read_altstatus = scc_read_altstatus;
b2f951aa
BZ		 803 hwif->read_sff_dma_status = scc_read_sff_dma_status;
804
db2432c4
BZ		 805 hwif->tf_load = scc_tf_load;
806 hwif->tf_read = scc_tf_read;
807
efa3db1b
BZ		 808 hwif->input_data = scc_input_data;
809 hwif->output_data = scc_output_data;
810
bde18a2e 811 hwif->INB = scc_ide_inb;
bde18a2e
KI		 812 hwif->OUTB = scc_ide_outb;
813 hwif->OUTBSYNC = scc_ide_outbsync;
bde18a2e 814
bde18a2e
KI		 815 hwif->dma_base = dma_base;
816 hwif->config_data = ports->ctl;
bde18a2e
KI		 817}
818
819/**
820 * init_iops_scc - set up iops
821 * @hwif: interface to set up
822 *
823 * Do the basic setup for the SCC hardware interface
824 * and then do the MMIO setup.
825 */
826
827static void __devinit init_iops_scc(ide_hwif_t *hwif)
828{
36501650
BZ		 829 struct pci_dev *dev = to_pci_dev(hwif->dev);
830
bde18a2e
KI		 831 hwif->hwif_data = NULL;
832 if (pci_get_drvdata(dev) == NULL)
833 return;
834 init_mmio_iops_scc(hwif);
835}
836
b4d1c73d
BZ		 837static u8 __devinit scc_cable_detect(ide_hwif_t *hwif)
838{
839 return ATA_CBL_PATA80;
840}
841
bde18a2e
KI		 842/**
843 * init_hwif_scc - set up hwif
844 * @hwif: interface to set up
845 *
846 * We do the basic set up of the interface structure. The SCC
847 * requires several custom handlers so we override the default
848 * ide DMA handlers appropriately.
849 */
850
851static void __devinit init_hwif_scc(ide_hwif_t *hwif)
852{
853 struct scc_ports *ports = ide_get_hwifdata(hwif);
854
589b0626 855 ports->hwif = hwif;
bde18a2e 856
0ecdca26
BZ		 857 /* PTERADD */
858 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
bde18a2e 859
5f8b6c34
BZ		 860 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
861 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
862 else
863 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
bde18a2e
KI		 864}
865
ac95beed
BZ		 866static const struct ide_port_ops scc_port_ops = {
867 .set_pio_mode = scc_set_pio_mode,
868 .set_dma_mode = scc_set_dma_mode,
869 .udma_filter = scc_udma_filter,
870 .cable_detect = scc_cable_detect,
871};
872
f37afdac 873static const struct ide_dma_ops scc_dma_ops = {
669185e9 874 .dma_host_set = scc_dma_host_set,
5e37bdc0 875 .dma_setup = scc_dma_setup,
f37afdac 876 .dma_exec_cmd = ide_dma_exec_cmd,
669185e9 877 .dma_start = scc_dma_start,
5e37bdc0
BZ		 878 .dma_end = scc_dma_end,
879 .dma_test_irq = scc_dma_test_irq,
f37afdac
BZ		 880 .dma_lost_irq = ide_dma_lost_irq,
881 .dma_timeout = ide_dma_timeout,
5e37bdc0
BZ		 882};
883
bde18a2e
KI		 884#define DECLARE_SCC_DEV(name_str) \
885 { \
886 .name = name_str, \
bde18a2e
KI		 887 .init_iops = init_iops_scc, \
888 .init_hwif = init_hwif_scc, \
ac95beed 889 .port_ops = &scc_port_ops, \
5e37bdc0 890 .dma_ops = &scc_dma_ops, \
5e71d9c5 891 .host_flags = IDE_HFLAG_SINGLE, \
4099d143 892 .pio_mask = ATA_PIO4, \
bde18a2e
KI		 893 }
894
85620436 895static const struct ide_port_info scc_chipsets[] __devinitdata = {
bde18a2e
KI		 896 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
897};
898
899/**
900 * scc_init_one - pci layer discovery entry
901 * @dev: PCI device
902 * @id: ident table entry
903 *
904 * Called by the PCI code when it finds an SCC PATA controller.
905 * We then use the IDE PCI generic helper to do most of the work.
906 */
907
908static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
909{
039788e1 910 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
bde18a2e
KI		 911}
912
913/**
914 * scc_remove - pci layer remove entry
915 * @dev: PCI device
916 *
917 * Called by the PCI code when it removes an SCC PATA controller.
918 */
919
920static void __devexit scc_remove(struct pci_dev *dev)
921{
922 struct scc_ports *ports = pci_get_drvdata(dev);
589b0626 923 ide_hwif_t *hwif = ports->hwif;
bde18a2e
KI		 924
925 if (hwif->dmatable_cpu) {
36501650
BZ		 926 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
927 hwif->dmatable_cpu, hwif->dmatable_dma);
bde18a2e
KI		 928 hwif->dmatable_cpu = NULL;
929 }
930
387750c3 931 ide_unregister(hwif);
bde18a2e 932
bde18a2e
KI		 933 iounmap((void*)ports->dma);
934 iounmap((void*)ports->ctl);
0d1bad21 935 pci_release_selected_regions(dev, (1 << 2) - 1);
bde18a2e
KI		 936 memset(ports, 0, sizeof(*ports));
937}
938
9cbcc5e3
BZ		 939static const struct pci_device_id scc_pci_tbl[] = {
940 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
bde18a2e
KI		 941 { 0, },
942};
943MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
944
945static struct pci_driver driver = {
946 .name = "SCC IDE",
947 .id_table = scc_pci_tbl,
948 .probe = scc_init_one,
949 .remove = scc_remove,
950};
951
952static int scc_ide_init(void)
953{
954 return ide_pci_register_driver(&driver);
955}
956
957module_init(scc_ide_init);
958/* -- No exit code?
959static void scc_ide_exit(void)
960{
961 ide_pci_unregister_driver(&driver);
962}
963module_exit(scc_ide_exit);
964 */
965
966
967MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
968MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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