Commit | Line | Data |
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1da177e4 | 1 | /* |
0271fc2d | 2 | * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it would be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public | |
13 | * License along with this program; if not, write the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
15 | * | |
1da177e4 LT |
16 | * For further information regarding this notice, see: |
17 | * | |
18 | * http://oss.sgi.com/projects/GenInfo/NoticeExplan | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/hdreg.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/timer.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/blkdev.h> | |
22329b51 | 32 | #include <linux/ioc4.h> |
1da177e4 LT |
33 | #include <asm/io.h> |
34 | ||
35 | #include <linux/ide.h> | |
36 | ||
ca1997c1 BZ |
37 | #define DRV_NAME "SGIIOC4" |
38 | ||
1da177e4 LT |
39 | /* IOC4 Specific Definitions */ |
40 | #define IOC4_CMD_OFFSET 0x100 | |
41 | #define IOC4_CTRL_OFFSET 0x120 | |
42 | #define IOC4_DMA_OFFSET 0x140 | |
43 | #define IOC4_INTR_OFFSET 0x0 | |
44 | ||
45 | #define IOC4_TIMING 0x00 | |
46 | #define IOC4_DMA_PTR_L 0x01 | |
47 | #define IOC4_DMA_PTR_H 0x02 | |
48 | #define IOC4_DMA_ADDR_L 0x03 | |
49 | #define IOC4_DMA_ADDR_H 0x04 | |
50 | #define IOC4_BC_DEV 0x05 | |
51 | #define IOC4_BC_MEM 0x06 | |
52 | #define IOC4_DMA_CTRL 0x07 | |
53 | #define IOC4_DMA_END_ADDR 0x08 | |
54 | ||
55 | /* Bits in the IOC4 Control/Status Register */ | |
56 | #define IOC4_S_DMA_START 0x01 | |
57 | #define IOC4_S_DMA_STOP 0x02 | |
58 | #define IOC4_S_DMA_DIR 0x04 | |
59 | #define IOC4_S_DMA_ACTIVE 0x08 | |
60 | #define IOC4_S_DMA_ERROR 0x10 | |
61 | #define IOC4_ATA_MEMERR 0x02 | |
62 | ||
63 | /* Read/Write Directions */ | |
64 | #define IOC4_DMA_WRITE 0x04 | |
65 | #define IOC4_DMA_READ 0x00 | |
66 | ||
67 | /* Interrupt Register Offsets */ | |
68 | #define IOC4_INTR_REG 0x03 | |
69 | #define IOC4_INTR_SET 0x05 | |
70 | #define IOC4_INTR_CLEAR 0x07 | |
71 | ||
72 | #define IOC4_IDE_CACHELINE_SIZE 128 | |
73 | #define IOC4_CMD_CTL_BLK_SIZE 0x20 | |
74 | #define IOC4_SUPPORTED_FIRMWARE_REV 46 | |
75 | ||
76 | typedef struct { | |
77 | u32 timing_reg0; | |
78 | u32 timing_reg1; | |
79 | u32 low_mem_ptr; | |
80 | u32 high_mem_ptr; | |
81 | u32 low_mem_addr; | |
82 | u32 high_mem_addr; | |
83 | u32 dev_byte_count; | |
84 | u32 mem_byte_count; | |
85 | u32 status; | |
86 | } ioc4_dma_regs_t; | |
87 | ||
88 | /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */ | |
89 | /* IOC4 has only 1 IDE channel */ | |
90 | #define IOC4_PRD_BYTES 16 | |
91 | #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES)) | |
92 | ||
93 | ||
94 | static void | |
95 | sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port, | |
96 | unsigned long ctrl_port, unsigned long irq_port) | |
97 | { | |
98 | unsigned long reg = data_port; | |
99 | int i; | |
100 | ||
101 | /* Registers are word (32 bit) aligned */ | |
102 | for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) | |
103 | hw->io_ports[i] = reg + i * 4; | |
104 | ||
105 | if (ctrl_port) | |
106 | hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; | |
107 | ||
108 | if (irq_port) | |
109 | hw->io_ports[IDE_IRQ_OFFSET] = irq_port; | |
110 | } | |
111 | ||
112 | static void | |
113 | sgiioc4_maskproc(ide_drive_t * drive, int mask) | |
114 | { | |
0ecdca26 BZ |
115 | writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
116 | (void __iomem *)IDE_CONTROL_REG); | |
1da177e4 LT |
117 | } |
118 | ||
119 | ||
120 | static int | |
121 | sgiioc4_checkirq(ide_hwif_t * hwif) | |
122 | { | |
0ecdca26 BZ |
123 | unsigned long intr_addr = |
124 | hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; | |
1da177e4 | 125 | |
0ecdca26 | 126 | if ((u8)readl((void __iomem *)intr_addr) & 0x03) |
1da177e4 LT |
127 | return 1; |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
0ecdca26 | 132 | static u8 sgiioc4_INB(unsigned long); |
1da177e4 LT |
133 | |
134 | static int | |
135 | sgiioc4_clearirq(ide_drive_t * drive) | |
136 | { | |
137 | u32 intr_reg; | |
138 | ide_hwif_t *hwif = HWIF(drive); | |
139 | unsigned long other_ir = | |
140 | hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); | |
141 | ||
142 | /* Code to check for PCI error conditions */ | |
0ecdca26 | 143 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
144 | if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ |
145 | /* | |
0ecdca26 | 146 | * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect |
1da177e4 LT |
147 | * of clearing the interrupt. The first read should clear it |
148 | * if it is set. The second read should return a "clear" status | |
149 | * if it got cleared. If not, then spin for a bit trying to | |
150 | * clear it. | |
151 | */ | |
0ecdca26 | 152 | u8 stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 | 153 | int count = 0; |
0ecdca26 | 154 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
155 | while ((stat & 0x80) && (count++ < 100)) { |
156 | udelay(1); | |
0ecdca26 | 157 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
158 | } |
159 | ||
160 | if (intr_reg & 0x02) { | |
161 | /* Error when transferring DMA data on PCI bus */ | |
162 | u32 pci_err_addr_low, pci_err_addr_high, | |
163 | pci_stat_cmd_reg; | |
164 | ||
165 | pci_err_addr_low = | |
0ecdca26 | 166 | readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); |
1da177e4 | 167 | pci_err_addr_high = |
0ecdca26 | 168 | readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); |
1da177e4 LT |
169 | pci_read_config_dword(hwif->pci_dev, PCI_COMMAND, |
170 | &pci_stat_cmd_reg); | |
171 | printk(KERN_ERR | |
172 | "%s(%s) : PCI Bus Error when doing DMA:" | |
173 | " status-cmd reg is 0x%x\n", | |
174 | __FUNCTION__, drive->name, pci_stat_cmd_reg); | |
175 | printk(KERN_ERR | |
176 | "%s(%s) : PCI Error Address is 0x%x%x\n", | |
177 | __FUNCTION__, drive->name, | |
178 | pci_err_addr_high, pci_err_addr_low); | |
179 | /* Clear the PCI Error indicator */ | |
180 | pci_write_config_dword(hwif->pci_dev, PCI_COMMAND, | |
181 | 0x00000146); | |
182 | } | |
183 | ||
184 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
0ecdca26 | 185 | writel(0x03, (void __iomem *)other_ir); |
1da177e4 | 186 | |
0ecdca26 | 187 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
188 | } |
189 | ||
190 | return intr_reg & 3; | |
191 | } | |
192 | ||
193 | static void sgiioc4_ide_dma_start(ide_drive_t * drive) | |
194 | { | |
195 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
196 | unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4; |
197 | unsigned int reg = readl((void __iomem *)ioc4_dma_addr); | |
1da177e4 LT |
198 | unsigned int temp_reg = reg | IOC4_S_DMA_START; |
199 | ||
0ecdca26 | 200 | writel(temp_reg, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
201 | } |
202 | ||
203 | static u32 | |
204 | sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base) | |
205 | { | |
0ecdca26 | 206 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; |
1da177e4 LT |
207 | u32 ioc4_dma; |
208 | int count; | |
209 | ||
210 | count = 0; | |
0ecdca26 | 211 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
212 | while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) { |
213 | udelay(1); | |
0ecdca26 | 214 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
215 | } |
216 | return ioc4_dma; | |
217 | } | |
218 | ||
219 | /* Stops the IOC4 DMA Engine */ | |
220 | static int | |
221 | sgiioc4_ide_dma_end(ide_drive_t * drive) | |
222 | { | |
223 | u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0; | |
224 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 | 225 | unsigned long dma_base = hwif->dma_base; |
1da177e4 | 226 | int dma_stat = 0; |
3f63c5e8 | 227 | unsigned long *ending_dma = ide_get_hwifdata(hwif); |
1da177e4 | 228 | |
0ecdca26 | 229 | writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4)); |
1da177e4 LT |
230 | |
231 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); | |
232 | ||
233 | if (ioc4_dma & IOC4_S_DMA_STOP) { | |
234 | printk(KERN_ERR | |
235 | "%s(%s): IOC4 DMA STOP bit is still 1 :" | |
236 | "ioc4_dma_reg 0x%x\n", | |
237 | __FUNCTION__, drive->name, ioc4_dma); | |
238 | dma_stat = 1; | |
239 | } | |
240 | ||
241 | /* | |
242 | * The IOC4 will DMA 1's to the ending dma area to indicate that | |
243 | * previous data DMA is complete. This is necessary because of relaxed | |
244 | * ordering between register reads and DMA writes on the Altix. | |
245 | */ | |
246 | while ((cnt++ < 200) && (!valid)) { | |
247 | for (num = 0; num < 16; num++) { | |
248 | if (ending_dma[num]) { | |
249 | valid = 1; | |
250 | break; | |
251 | } | |
252 | } | |
253 | udelay(1); | |
254 | } | |
255 | if (!valid) { | |
256 | printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__, | |
257 | drive->name); | |
258 | dma_stat = 1; | |
259 | } | |
260 | ||
0ecdca26 BZ |
261 | bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4)); |
262 | bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4)); | |
1da177e4 LT |
263 | |
264 | if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) { | |
265 | if (bc_dev > bc_mem + 8) { | |
266 | printk(KERN_ERR | |
267 | "%s(%s): WARNING!! byte_count_dev %d " | |
268 | "!= byte_count_mem %d\n", | |
269 | __FUNCTION__, drive->name, bc_dev, bc_mem); | |
270 | } | |
271 | } | |
272 | ||
273 | drive->waiting_for_dma = 0; | |
274 | ide_destroy_dmatable(drive); | |
275 | ||
276 | return dma_stat; | |
277 | } | |
278 | ||
1da177e4 LT |
279 | static int |
280 | sgiioc4_ide_dma_on(ide_drive_t * drive) | |
281 | { | |
282 | drive->using_dma = 1; | |
283 | ||
ccf35289 | 284 | return 0; |
1da177e4 LT |
285 | } |
286 | ||
7469aaf6 | 287 | static void sgiioc4_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
288 | { |
289 | drive->using_dma = 0; | |
290 | ||
7469aaf6 | 291 | drive->hwif->dma_host_off(drive); |
1da177e4 LT |
292 | } |
293 | ||
ca1997c1 BZ |
294 | static int sgiioc4_speedproc(ide_drive_t *drive, const u8 speed) |
295 | { | |
296 | if (speed != XFER_MW_DMA_2) | |
297 | return 1; | |
298 | ||
299 | return ide_config_drive_speed(drive, speed); | |
300 | } | |
301 | ||
9ef5791e BZ |
302 | static int sgiioc4_ide_dma_check(ide_drive_t *drive) |
303 | { | |
ca1997c1 | 304 | if (ide_tune_dma(drive)) |
3608b5d7 | 305 | return 0; |
ca1997c1 BZ |
306 | |
307 | /* | |
308 | * ->set_pio_mode is not implemented currently | |
309 | * so this is just for the completness | |
310 | */ | |
311 | ide_set_max_pio(drive); | |
312 | ||
313 | return -1; | |
9ef5791e BZ |
314 | } |
315 | ||
1da177e4 LT |
316 | /* returns 1 if dma irq issued, 0 otherwise */ |
317 | static int | |
318 | sgiioc4_ide_dma_test_irq(ide_drive_t * drive) | |
319 | { | |
320 | return sgiioc4_checkirq(HWIF(drive)); | |
321 | } | |
322 | ||
ccf35289 | 323 | static void sgiioc4_dma_host_on(ide_drive_t * drive) |
1da177e4 | 324 | { |
1da177e4 LT |
325 | } |
326 | ||
7469aaf6 | 327 | static void sgiioc4_dma_host_off(ide_drive_t * drive) |
1da177e4 LT |
328 | { |
329 | sgiioc4_clearirq(drive); | |
1da177e4 LT |
330 | } |
331 | ||
1da177e4 LT |
332 | static void |
333 | sgiioc4_resetproc(ide_drive_t * drive) | |
334 | { | |
335 | sgiioc4_ide_dma_end(drive); | |
336 | sgiioc4_clearirq(drive); | |
337 | } | |
338 | ||
841d2a9b SS |
339 | static void |
340 | sgiioc4_dma_lost_irq(ide_drive_t * drive) | |
341 | { | |
342 | sgiioc4_resetproc(drive); | |
343 | ||
344 | ide_dma_lost_irq(drive); | |
345 | } | |
346 | ||
1da177e4 LT |
347 | static u8 |
348 | sgiioc4_INB(unsigned long port) | |
349 | { | |
a835fa79 | 350 | u8 reg = (u8) readb((void __iomem *) port); |
1da177e4 LT |
351 | |
352 | if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */ | |
353 | if (reg & 0x51) { /* Not busy...check for interrupt */ | |
354 | unsigned long other_ir = port - 0x110; | |
a835fa79 | 355 | unsigned int intr_reg = (u32) readl((void __iomem *) other_ir); |
1da177e4 LT |
356 | |
357 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
358 | if (intr_reg & 0x03) { | |
a835fa79 JH |
359 | writel(0x03, (void __iomem *) other_ir); |
360 | intr_reg = (u32) readl((void __iomem *) other_ir); | |
1da177e4 LT |
361 | } |
362 | } | |
363 | } | |
364 | ||
365 | return reg; | |
366 | } | |
367 | ||
368 | /* Creates a dma map for the scatter-gather list entries */ | |
ca1997c1 | 369 | static int __devinit |
1da177e4 LT |
370 | ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base) |
371 | { | |
1678df37 | 372 | void __iomem *virt_dma_base; |
1da177e4 | 373 | int num_ports = sizeof (ioc4_dma_regs_t); |
3f63c5e8 | 374 | void *pad; |
1da177e4 LT |
375 | |
376 | printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name, | |
377 | dma_base, dma_base + num_ports - 1); | |
378 | ||
1678df37 | 379 | if (!request_mem_region(dma_base, num_ports, hwif->name)) { |
1da177e4 LT |
380 | printk(KERN_ERR |
381 | "%s(%s) -- ERROR, Addresses 0x%p to 0x%p " | |
382 | "ALREADY in use\n", | |
383 | __FUNCTION__, hwif->name, (void *) dma_base, | |
384 | (void *) dma_base + num_ports - 1); | |
ca1997c1 | 385 | return -1; |
1da177e4 LT |
386 | } |
387 | ||
1678df37 JK |
388 | virt_dma_base = ioremap(dma_base, num_ports); |
389 | if (virt_dma_base == NULL) { | |
390 | printk(KERN_ERR | |
391 | "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n", | |
392 | __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1); | |
393 | goto dma_remap_failure; | |
394 | } | |
395 | hwif->dma_base = (unsigned long) virt_dma_base; | |
396 | ||
1da177e4 LT |
397 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, |
398 | IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, | |
399 | &hwif->dmatable_dma); | |
400 | ||
401 | if (!hwif->dmatable_cpu) | |
1678df37 | 402 | goto dma_pci_alloc_failure; |
1da177e4 LT |
403 | |
404 | hwif->sg_max_nents = IOC4_PRD_ENTRIES; | |
405 | ||
3f63c5e8 SS |
406 | pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE, |
407 | (dma_addr_t *) &(hwif->dma_status)); | |
1da177e4 | 408 | |
3f63c5e8 SS |
409 | if (pad) { |
410 | ide_set_hwifdata(hwif, pad); | |
ca1997c1 | 411 | return 0; |
3f63c5e8 | 412 | } |
1da177e4 | 413 | |
1da177e4 LT |
414 | pci_free_consistent(hwif->pci_dev, |
415 | IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, | |
416 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
417 | printk(KERN_INFO | |
418 | "%s() -- Error! Unable to allocate DMA Maps for drive %s\n", | |
419 | __FUNCTION__, hwif->name); | |
420 | printk(KERN_INFO | |
421 | "Changing from DMA to PIO mode for Drive %s\n", hwif->name); | |
422 | ||
1678df37 JK |
423 | dma_pci_alloc_failure: |
424 | iounmap(virt_dma_base); | |
425 | ||
426 | dma_remap_failure: | |
427 | release_mem_region(dma_base, num_ports); | |
428 | ||
ca1997c1 | 429 | return -1; |
1da177e4 LT |
430 | } |
431 | ||
432 | /* Initializes the IOC4 DMA Engine */ | |
433 | static void | |
434 | sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive) | |
435 | { | |
436 | u32 ioc4_dma; | |
437 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
438 | unsigned long dma_base = hwif->dma_base; |
439 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; | |
1da177e4 LT |
440 | u32 dma_addr, ending_dma_addr; |
441 | ||
0ecdca26 | 442 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
443 | |
444 | if (ioc4_dma & IOC4_S_DMA_ACTIVE) { | |
445 | printk(KERN_WARNING | |
446 | "%s(%s):Warning!! DMA from previous transfer was still active\n", | |
447 | __FUNCTION__, drive->name); | |
0ecdca26 | 448 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
449 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
450 | ||
451 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
452 | printk(KERN_ERR | |
453 | "%s(%s) : IOC4 Dma STOP bit is still 1\n", | |
454 | __FUNCTION__, drive->name); | |
455 | } | |
456 | ||
0ecdca26 | 457 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
458 | if (ioc4_dma & IOC4_S_DMA_ERROR) { |
459 | printk(KERN_WARNING | |
460 | "%s(%s) : Warning!! - DMA Error during Previous" | |
461 | " transfer | status 0x%x\n", | |
462 | __FUNCTION__, drive->name, ioc4_dma); | |
0ecdca26 | 463 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
464 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
465 | ||
466 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
467 | printk(KERN_ERR | |
468 | "%s(%s) : IOC4 DMA STOP bit is still 1\n", | |
469 | __FUNCTION__, drive->name); | |
470 | } | |
471 | ||
472 | /* Address of the Scatter Gather List */ | |
473 | dma_addr = cpu_to_le32(hwif->dmatable_dma); | |
0ecdca26 | 474 | writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4)); |
1da177e4 LT |
475 | |
476 | /* Address of the Ending DMA */ | |
3f63c5e8 | 477 | memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE); |
1da177e4 | 478 | ending_dma_addr = cpu_to_le32(hwif->dma_status); |
0ecdca26 | 479 | writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4)); |
1da177e4 | 480 | |
0ecdca26 | 481 | writel(dma_direction, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
482 | drive->waiting_for_dma = 1; |
483 | } | |
484 | ||
485 | /* IOC4 Scatter Gather list Format */ | |
486 | /* 128 Bit entries to support 64 bit addresses in the future */ | |
487 | /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */ | |
488 | /* --------------------------------------------------------------------- */ | |
489 | /* | Upper 32 bits - Zero | Lower 32 bits- address | */ | |
490 | /* --------------------------------------------------------------------- */ | |
491 | /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */ | |
492 | /* --------------------------------------------------------------------- */ | |
493 | /* Creates the scatter gather list, DMA Table */ | |
494 | static unsigned int | |
495 | sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir) | |
496 | { | |
497 | ide_hwif_t *hwif = HWIF(drive); | |
498 | unsigned int *table = hwif->dmatable_cpu; | |
499 | unsigned int count = 0, i = 1; | |
500 | struct scatterlist *sg; | |
501 | ||
502 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
503 | ||
504 | if (!i) | |
505 | return 0; /* sglist of length Zero */ | |
506 | ||
507 | sg = hwif->sg_table; | |
508 | while (i && sg_dma_len(sg)) { | |
509 | dma_addr_t cur_addr; | |
510 | int cur_len; | |
511 | cur_addr = sg_dma_address(sg); | |
512 | cur_len = sg_dma_len(sg); | |
513 | ||
514 | while (cur_len) { | |
515 | if (count++ >= IOC4_PRD_ENTRIES) { | |
516 | printk(KERN_WARNING | |
517 | "%s: DMA table too small\n", | |
518 | drive->name); | |
519 | goto use_pio_instead; | |
520 | } else { | |
0271fc2d | 521 | u32 bcount = |
1da177e4 LT |
522 | 0x10000 - (cur_addr & 0xffff); |
523 | ||
524 | if (bcount > cur_len) | |
525 | bcount = cur_len; | |
526 | ||
527 | /* put the addr, length in | |
528 | * the IOC4 dma-table format */ | |
529 | *table = 0x0; | |
530 | table++; | |
531 | *table = cpu_to_be32(cur_addr); | |
532 | table++; | |
533 | *table = 0x0; | |
534 | table++; | |
535 | ||
0271fc2d | 536 | *table = cpu_to_be32(bcount); |
1da177e4 LT |
537 | table++; |
538 | ||
539 | cur_addr += bcount; | |
540 | cur_len -= bcount; | |
541 | } | |
542 | } | |
543 | ||
544 | sg++; | |
545 | i--; | |
546 | } | |
547 | ||
548 | if (count) { | |
549 | table--; | |
550 | *table |= cpu_to_be32(0x80000000); | |
551 | return count; | |
552 | } | |
553 | ||
554 | use_pio_instead: | |
555 | pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents, | |
556 | hwif->sg_dma_direction); | |
557 | ||
558 | return 0; /* revert to PIO for this request */ | |
559 | } | |
560 | ||
561 | static int sgiioc4_ide_dma_setup(ide_drive_t *drive) | |
562 | { | |
563 | struct request *rq = HWGROUP(drive)->rq; | |
564 | unsigned int count = 0; | |
565 | int ddir; | |
566 | ||
567 | if (rq_data_dir(rq)) | |
568 | ddir = PCI_DMA_TODEVICE; | |
569 | else | |
570 | ddir = PCI_DMA_FROMDEVICE; | |
571 | ||
572 | if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) { | |
573 | /* try PIO instead of DMA */ | |
574 | ide_map_sg(drive, rq); | |
575 | return 1; | |
576 | } | |
577 | ||
578 | if (rq_data_dir(rq)) | |
579 | /* Writes TO the IOC4 FROM Main Memory */ | |
580 | ddir = IOC4_DMA_READ; | |
581 | else | |
582 | /* Writes FROM the IOC4 TO Main Memory */ | |
583 | ddir = IOC4_DMA_WRITE; | |
584 | ||
585 | sgiioc4_configure_for_dma(ddir, drive); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static void __devinit | |
591 | ide_init_sgiioc4(ide_hwif_t * hwif) | |
592 | { | |
2ad1e558 | 593 | hwif->mmio = 1; |
1da177e4 | 594 | hwif->atapi_dma = 1; |
ca1997c1 | 595 | hwif->mwdma_mask = 0x04; |
4099d143 | 596 | hwif->pio_mask = 0x00; |
26bcb879 | 597 | hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */ |
ca1997c1 | 598 | hwif->speedproc = &sgiioc4_speedproc; |
1da177e4 LT |
599 | hwif->selectproc = NULL;/* Use the default routine to select drive */ |
600 | hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */ | |
601 | hwif->pre_reset = NULL; /* No HBA specific pre_set needed */ | |
602 | hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine, | |
603 | clear interrupts */ | |
604 | hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */ | |
605 | hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */ | |
606 | hwif->quirkproc = NULL; | |
607 | hwif->busproc = NULL; | |
608 | ||
609 | hwif->dma_setup = &sgiioc4_ide_dma_setup; | |
610 | hwif->dma_start = &sgiioc4_ide_dma_start; | |
611 | hwif->ide_dma_end = &sgiioc4_ide_dma_end; | |
612 | hwif->ide_dma_check = &sgiioc4_ide_dma_check; | |
613 | hwif->ide_dma_on = &sgiioc4_ide_dma_on; | |
7469aaf6 | 614 | hwif->dma_off_quietly = &sgiioc4_dma_off_quietly; |
1da177e4 | 615 | hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq; |
ccf35289 | 616 | hwif->dma_host_on = &sgiioc4_dma_host_on; |
7469aaf6 | 617 | hwif->dma_host_off = &sgiioc4_dma_host_off; |
841d2a9b | 618 | hwif->dma_lost_irq = &sgiioc4_dma_lost_irq; |
c283f5db | 619 | hwif->dma_timeout = &ide_dma_timeout; |
a835fa79 | 620 | |
1da177e4 LT |
621 | hwif->INB = &sgiioc4_INB; |
622 | } | |
623 | ||
624 | static int __devinit | |
ca1997c1 | 625 | sgiioc4_ide_setup_pci_device(struct pci_dev *dev) |
1da177e4 | 626 | { |
1678df37 JK |
627 | unsigned long cmd_base, dma_base, irqport; |
628 | unsigned long bar0, cmd_phys_base, ctl; | |
629 | void __iomem *virt_base; | |
1da177e4 LT |
630 | ide_hwif_t *hwif; |
631 | int h; | |
632 | ||
deb5e5c0 JH |
633 | /* |
634 | * Find an empty HWIF; if none available, return -ENOMEM. | |
635 | */ | |
1da177e4 LT |
636 | for (h = 0; h < MAX_HWIFS; ++h) { |
637 | hwif = &ide_hwifs[h]; | |
1da177e4 LT |
638 | if (hwif->chipset == ide_unknown) |
639 | break; | |
640 | } | |
deb5e5c0 | 641 | if (h == MAX_HWIFS) { |
ca1997c1 BZ |
642 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", |
643 | DRV_NAME); | |
deb5e5c0 JH |
644 | return -ENOMEM; |
645 | } | |
1da177e4 LT |
646 | |
647 | /* Get the CmdBlk and CtrlBlk Base Registers */ | |
1678df37 JK |
648 | bar0 = pci_resource_start(dev, 0); |
649 | virt_base = ioremap(bar0, pci_resource_len(dev, 0)); | |
650 | if (virt_base == NULL) { | |
651 | printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n", | |
ca1997c1 | 652 | DRV_NAME, bar0); |
1678df37 JK |
653 | return -ENOMEM; |
654 | } | |
655 | cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET; | |
656 | ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET; | |
657 | irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET; | |
1da177e4 LT |
658 | dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET; |
659 | ||
1678df37 JK |
660 | cmd_phys_base = bar0 + IOC4_CMD_OFFSET; |
661 | if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE, | |
662 | hwif->name)) { | |
1da177e4 | 663 | printk(KERN_ERR |
1678df37 | 664 | "%s : %s -- ERROR, Addresses " |
1da177e4 | 665 | "0x%p to 0x%p ALREADY in use\n", |
1678df37 JK |
666 | __FUNCTION__, hwif->name, (void *) cmd_phys_base, |
667 | (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE); | |
1da177e4 LT |
668 | return -ENOMEM; |
669 | } | |
670 | ||
1678df37 | 671 | if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) { |
1da177e4 | 672 | /* Initialize the IO registers */ |
1678df37 | 673 | sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport); |
1da177e4 LT |
674 | memcpy(hwif->io_ports, hwif->hw.io_ports, |
675 | sizeof (hwif->io_ports)); | |
676 | hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; | |
677 | } | |
678 | ||
679 | hwif->irq = dev->irq; | |
680 | hwif->chipset = ide_pci; | |
681 | hwif->pci_dev = dev; | |
682 | hwif->channel = 0; /* Single Channel chip */ | |
1da177e4 LT |
683 | hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */ |
684 | ||
1678df37 JK |
685 | /* The IOC4 uses MMIO rather than Port IO. */ |
686 | default_hwif_mmiops(hwif); | |
687 | ||
1da177e4 | 688 | /* Initializing chipset IRQ Registers */ |
0ecdca26 | 689 | writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); |
1da177e4 LT |
690 | |
691 | ide_init_sgiioc4(hwif); | |
692 | ||
ca1997c1 BZ |
693 | hwif->autodma = 0; |
694 | ||
695 | if (dma_base && ide_dma_sgiioc4(hwif, dma_base) == 0) { | |
696 | hwif->autodma = 1; | |
697 | hwif->drives[1].autodma = hwif->drives[0].autodma = 1; | |
698 | } else | |
1da177e4 | 699 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n", |
ca1997c1 | 700 | hwif->name, DRV_NAME); |
1da177e4 LT |
701 | |
702 | if (probe_hwif_init(hwif)) | |
703 | return -EIO; | |
704 | ||
705 | /* Create /proc/ide entries */ | |
5cbf79cd | 706 | ide_proc_register_port(hwif); |
1da177e4 LT |
707 | |
708 | return 0; | |
709 | } | |
710 | ||
711 | static unsigned int __devinit | |
ca1997c1 | 712 | pci_init_sgiioc4(struct pci_dev *dev) |
1da177e4 LT |
713 | { |
714 | unsigned int class_rev; | |
715 | int ret; | |
716 | ||
717 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
718 | class_rev &= 0xff; | |
719 | printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n", | |
ca1997c1 | 720 | DRV_NAME, pci_name(dev), class_rev); |
1da177e4 LT |
721 | if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) { |
722 | printk(KERN_ERR "Skipping %s IDE controller in slot %s: " | |
ca1997c1 BZ |
723 | "firmware is obsolete - please upgrade to " |
724 | "revision46 or higher\n", | |
725 | DRV_NAME, pci_name(dev)); | |
1da177e4 LT |
726 | ret = -EAGAIN; |
727 | goto out; | |
728 | } | |
ca1997c1 | 729 | ret = sgiioc4_ide_setup_pci_device(dev); |
1da177e4 LT |
730 | out: |
731 | return ret; | |
732 | } | |
733 | ||
1da177e4 | 734 | int |
22329b51 | 735 | ioc4_ide_attach_one(struct ioc4_driver_data *idd) |
1da177e4 | 736 | { |
f5befceb BC |
737 | /* PCI-RT does not bring out IDE connection. |
738 | * Do not attach to this particular IOC4. | |
739 | */ | |
740 | if (idd->idd_variant == IOC4_VARIANT_PCI_RT) | |
741 | return 0; | |
742 | ||
ca1997c1 | 743 | return pci_init_sgiioc4(idd->idd_pdev); |
1da177e4 LT |
744 | } |
745 | ||
22329b51 BC |
746 | static struct ioc4_submodule ioc4_ide_submodule = { |
747 | .is_name = "IOC4_ide", | |
748 | .is_owner = THIS_MODULE, | |
749 | .is_probe = ioc4_ide_attach_one, | |
750 | /* .is_remove = ioc4_ide_remove_one, */ | |
751 | }; | |
752 | ||
82ab1eec | 753 | static int __init ioc4_ide_init(void) |
22329b51 BC |
754 | { |
755 | return ioc4_register_submodule(&ioc4_ide_submodule); | |
756 | } | |
757 | ||
59f14800 | 758 | late_initcall(ioc4_ide_init); /* Call only after IDE init is done */ |
1da177e4 | 759 | |
a835fa79 | 760 | MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon"); |
1da177e4 LT |
761 | MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card"); |
762 | MODULE_LICENSE("GPL"); |