Commit | Line | Data |
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1da177e4 | 1 | /* |
8ac98ce1 | 2 | * linux/drivers/ide/pci/siimage.c Version 1.19 Nov 16 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 6 | * Copyright (C) 2007 MontaVista Software, Inc. |
328dcbb6 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
bf4c796d JG |
11 | * Documentation for CMD680: |
12 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
13 | * | |
14 | * Documentation for SiI 3112: | |
15 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
16 | * | |
17 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
18 | * |
19 | * | |
20 | * FAQ Items: | |
21 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
22 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
23 | * | |
24 | * If you are using WD drives with SATA bridges you must set the | |
25 | * drive to "Single". "Master" will hang | |
26 | * | |
27 | * If you have strange problems with nVidia chipset systems please | |
28 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 29 | * if necessary |
8693d3e4 AC |
30 | * |
31 | * The Dell DRAC4 has some interesting features including effectively hot | |
32 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
33 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
34 | * smarter code in libata. | |
328dcbb6 BZ |
35 | * |
36 | * TODO: | |
37 | * - IORDY fixes | |
38 | * - VDMA support | |
1da177e4 LT |
39 | */ |
40 | ||
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/module.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/hdreg.h> | |
46 | #include <linux/ide.h> | |
47 | #include <linux/init.h> | |
48 | ||
49 | #include <asm/io.h> | |
50 | ||
1da177e4 LT |
51 | /** |
52 | * pdev_is_sata - check if device is SATA | |
53 | * @pdev: PCI device to check | |
54 | * | |
55 | * Returns true if this is a SATA controller | |
56 | */ | |
57 | ||
58 | static int pdev_is_sata(struct pci_dev *pdev) | |
59 | { | |
438c4702 BZ |
60 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
61 | switch(pdev->device) { | |
1da177e4 LT |
62 | case PCI_DEVICE_ID_SII_3112: |
63 | case PCI_DEVICE_ID_SII_1210SA: | |
64 | return 1; | |
65 | case PCI_DEVICE_ID_SII_680: | |
66 | return 0; | |
67 | } | |
68 | BUG(); | |
438c4702 | 69 | #endif |
1da177e4 LT |
70 | return 0; |
71 | } | |
438c4702 | 72 | |
1da177e4 LT |
73 | /** |
74 | * is_sata - check if hwif is SATA | |
75 | * @hwif: interface to check | |
76 | * | |
77 | * Returns true if this is a SATA controller | |
78 | */ | |
79 | ||
80 | static inline int is_sata(ide_hwif_t *hwif) | |
81 | { | |
36501650 | 82 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
83 | } |
84 | ||
85 | /** | |
86 | * siimage_selreg - return register base | |
87 | * @hwif: interface | |
88 | * @r: config offset | |
89 | * | |
90 | * Turn a config register offset into the right address in either | |
91 | * PCI space or MMIO space to access the control register in question | |
92 | * Thankfully this is a configuration operation so isnt performance | |
93 | * criticial. | |
94 | */ | |
95 | ||
96 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
97 | { | |
98 | unsigned long base = (unsigned long)hwif->hwif_data; | |
99 | base += 0xA0 + r; | |
100 | if(hwif->mmio) | |
101 | base += (hwif->channel << 6); | |
102 | else | |
103 | base += (hwif->channel << 4); | |
104 | return base; | |
105 | } | |
106 | ||
107 | /** | |
108 | * siimage_seldev - return register base | |
109 | * @hwif: interface | |
110 | * @r: config offset | |
111 | * | |
112 | * Turn a config register offset into the right address in either | |
113 | * PCI space or MMIO space to access the control register in question | |
114 | * including accounting for the unit shift. | |
115 | */ | |
116 | ||
117 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
118 | { | |
119 | ide_hwif_t *hwif = HWIF(drive); | |
120 | unsigned long base = (unsigned long)hwif->hwif_data; | |
121 | base += 0xA0 + r; | |
122 | if(hwif->mmio) | |
123 | base += (hwif->channel << 6); | |
124 | else | |
125 | base += (hwif->channel << 4); | |
126 | base |= drive->select.b.unit << drive->select.b.unit; | |
127 | return base; | |
128 | } | |
129 | ||
130 | /** | |
2d5eaa6d BZ |
131 | * sil_udma_filter - compute UDMA mask |
132 | * @drive: IDE device | |
133 | * | |
134 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 135 | * |
1da177e4 | 136 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 137 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 138 | */ |
2d5eaa6d | 139 | |
438c4702 | 140 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 141 | { |
2d5eaa6d | 142 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 143 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 144 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 145 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
146 | |
147 | if (hwif->mmio) | |
148 | scsc = hwif->INB(base + 0x4A); | |
149 | else | |
36501650 | 150 | pci_read_config_byte(dev, 0x8A, &scsc); |
1da177e4 | 151 | |
1da177e4 | 152 | if ((scsc & 0x30) == 0x10) /* 133 */ |
438c4702 | 153 | mask = ATA_UDMA6; |
1da177e4 | 154 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
438c4702 | 155 | mask = ATA_UDMA6; |
1da177e4 | 156 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
438c4702 | 157 | mask = ATA_UDMA5; |
1da177e4 LT |
158 | else /* Disabled ? */ |
159 | BUG(); | |
438c4702 | 160 | |
2d5eaa6d | 161 | return mask; |
1da177e4 LT |
162 | } |
163 | ||
438c4702 BZ |
164 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
165 | { | |
166 | return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
167 | } | |
168 | ||
1da177e4 | 169 | /** |
88b2b32b BZ |
170 | * sil_set_pio_mode - set host controller for PIO mode |
171 | * @drive: drive | |
172 | * @pio: PIO mode number | |
1da177e4 LT |
173 | * |
174 | * Load the timing settings for this device mode into the | |
175 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
176 | * monitoring (bit 9). The TF timing is bits 31:16 | |
177 | */ | |
328dcbb6 | 178 | |
88b2b32b | 179 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 180 | { |
328dcbb6 BZ |
181 | const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
182 | const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
183 | ||
1da177e4 | 184 | ide_hwif_t *hwif = HWIF(drive); |
a87a87cc | 185 | ide_drive_t *pair = ide_get_paired_drive(drive); |
1da177e4 LT |
186 | u32 speedt = 0; |
187 | u16 speedp = 0; | |
188 | unsigned long addr = siimage_seldev(drive, 0x04); | |
189 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
ffe5415c | 190 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 191 | u8 tf_pio = pio; |
ffe5415c BZ |
192 | u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) |
193 | : (hwif->mmio ? 0xB4 : 0x80); | |
194 | u8 mode = 0; | |
195 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
196 | |
197 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
198 | if (pair->present) { | |
2134758d | 199 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
200 | |
201 | if (pair_pio < tf_pio) | |
202 | tf_pio = pair_pio; | |
1da177e4 | 203 | } |
075cb655 | 204 | |
328dcbb6 BZ |
205 | /* cheat for now and use the docs */ |
206 | speedp = data_speed[pio]; | |
207 | speedt = tf_speed[tf_pio]; | |
208 | ||
075cb655 SS |
209 | if (hwif->mmio) { |
210 | hwif->OUTW(speedp, addr); | |
211 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 | 212 | /* Now set up IORDY */ |
328dcbb6 | 213 | if (pio > 2) |
1da177e4 LT |
214 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); |
215 | else | |
216 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
ffe5415c BZ |
217 | |
218 | mode = hwif->INB(base + addr_mask); | |
219 | mode &= ~(unit ? 0x30 : 0x03); | |
220 | mode |= (unit ? 0x10 : 0x01); | |
221 | hwif->OUTB(mode, base + addr_mask); | |
075cb655 | 222 | } else { |
36501650 BZ |
223 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
224 | ||
225 | pci_write_config_word(dev, addr, speedp); | |
226 | pci_write_config_word(dev, tfaddr, speedt); | |
227 | pci_read_config_word(dev, tfaddr - 2, &speedp); | |
1da177e4 LT |
228 | speedp &= ~0x200; |
229 | /* Set IORDY for mode 3 or 4 */ | |
328dcbb6 | 230 | if (pio > 2) |
1da177e4 | 231 | speedp |= 0x200; |
36501650 | 232 | pci_write_config_word(dev, tfaddr - 2, speedp); |
ffe5415c | 233 | |
36501650 | 234 | pci_read_config_byte(dev, addr_mask, &mode); |
ffe5415c BZ |
235 | mode &= ~(unit ? 0x30 : 0x03); |
236 | mode |= (unit ? 0x10 : 0x01); | |
36501650 | 237 | pci_write_config_byte(dev, addr_mask, mode); |
1da177e4 LT |
238 | } |
239 | } | |
240 | ||
1da177e4 | 241 | /** |
88b2b32b BZ |
242 | * sil_set_dma_mode - set host controller for DMA mode |
243 | * @drive: drive | |
244 | * @speed: DMA mode | |
1da177e4 | 245 | * |
88b2b32b | 246 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 247 | */ |
f212ff28 | 248 | |
88b2b32b | 249 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
250 | { |
251 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
252 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
253 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
254 | ||
255 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 256 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
257 | u16 ultra = 0, multi = 0; |
258 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 LT |
259 | unsigned long base = (unsigned long)hwif->hwif_data; |
260 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
261 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
262 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
263 | ||
264 | unsigned long ma = siimage_seldev(drive, 0x08); | |
265 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
266 | ||
267 | if (hwif->mmio) { | |
268 | scsc = hwif->INB(base + 0x4A); | |
269 | mode = hwif->INB(base + addr_mask); | |
270 | multi = hwif->INW(ma); | |
271 | ultra = hwif->INW(ua); | |
272 | } else { | |
36501650 BZ |
273 | pci_read_config_byte(dev, 0x8A, &scsc); |
274 | pci_read_config_byte(dev, addr_mask, &mode); | |
275 | pci_read_config_word(dev, ma, &multi); | |
276 | pci_read_config_word(dev, ua, &ultra); | |
1da177e4 LT |
277 | } |
278 | ||
279 | mode &= ~((unit) ? 0x30 : 0x03); | |
280 | ultra &= ~0x3F; | |
281 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
282 | ||
283 | scsc = is_sata(hwif) ? 1 : scsc; | |
284 | ||
4db90a14 BZ |
285 | if (speed >= XFER_UDMA_0) { |
286 | multi = dma[2]; | |
287 | ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : | |
288 | ultra5[speed - XFER_UDMA_0]); | |
289 | mode |= (unit ? 0x30 : 0x03); | |
290 | } else { | |
291 | multi = dma[speed - XFER_MW_DMA_0]; | |
292 | mode |= (unit ? 0x20 : 0x02); | |
1da177e4 LT |
293 | } |
294 | ||
295 | if (hwif->mmio) { | |
296 | hwif->OUTB(mode, base + addr_mask); | |
297 | hwif->OUTW(multi, ma); | |
298 | hwif->OUTW(ultra, ua); | |
299 | } else { | |
36501650 BZ |
300 | pci_write_config_byte(dev, addr_mask, mode); |
301 | pci_write_config_word(dev, ma, multi); | |
302 | pci_write_config_word(dev, ua, ultra); | |
1da177e4 | 303 | } |
1da177e4 LT |
304 | } |
305 | ||
1da177e4 LT |
306 | /* returns 1 if dma irq issued, 0 otherwise */ |
307 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
308 | { | |
309 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 310 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
311 | u8 dma_altstat = 0; |
312 | unsigned long addr = siimage_selreg(hwif, 1); | |
313 | ||
314 | /* return 1 if INTR asserted */ | |
315 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
316 | return 1; | |
317 | ||
318 | /* return 1 if Device INTR asserted */ | |
36501650 | 319 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 LT |
320 | if (dma_altstat & 8) |
321 | return 0; //return 1; | |
322 | return 0; | |
323 | } | |
324 | ||
1da177e4 LT |
325 | /** |
326 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
327 | * @drive: drive we are testing | |
328 | * | |
329 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
330 | * SATA status interrupts, if so we clean them up and continue. | |
331 | */ | |
332 | ||
333 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
334 | { | |
335 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
336 | unsigned long addr = siimage_selreg(hwif, 0x1); |
337 | ||
338 | if (SATA_ERROR_REG) { | |
438c4702 BZ |
339 | unsigned long base = (unsigned long)hwif->hwif_data; |
340 | ||
0ecdca26 | 341 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
342 | u8 watchdog = 0; |
343 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
344 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
345 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 346 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
347 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
348 | "watchdog = %d, %s\n", | |
349 | drive->name, sata_error, watchdog, | |
350 | __FUNCTION__); | |
1da177e4 LT |
351 | |
352 | } else { | |
353 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
354 | } | |
355 | ext_stat >>= 16; | |
356 | ||
357 | if (!(ext_stat & 0x0404) && !watchdog) | |
358 | return 0; | |
359 | } | |
360 | ||
361 | /* return 1 if INTR asserted */ | |
0ecdca26 | 362 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
363 | return 1; |
364 | ||
365 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 366 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
367 | return 0; //return 1; |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | /** | |
438c4702 | 373 | * sil_sata_busproc - bus isolation IOCTL |
1da177e4 LT |
374 | * @drive: drive to isolate/restore |
375 | * @state: bus state to set | |
376 | * | |
377 | * Used by the SII3112 to handle bus isolation. As this is a | |
378 | * SATA controller the work required is quite limited, we | |
379 | * just have to clean up the statistics | |
380 | */ | |
438c4702 BZ |
381 | |
382 | static int sil_sata_busproc(ide_drive_t * drive, int state) | |
1da177e4 LT |
383 | { |
384 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 385 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
386 | u32 stat_config = 0; |
387 | unsigned long addr = siimage_selreg(hwif, 0); | |
388 | ||
0ecdca26 BZ |
389 | if (hwif->mmio) |
390 | stat_config = readl((void __iomem *)addr); | |
391 | else | |
36501650 | 392 | pci_read_config_dword(dev, addr, &stat_config); |
1da177e4 LT |
393 | |
394 | switch (state) { | |
395 | case BUSSTATE_ON: | |
396 | hwif->drives[0].failures = 0; | |
397 | hwif->drives[1].failures = 0; | |
398 | break; | |
399 | case BUSSTATE_OFF: | |
400 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
401 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
402 | break; | |
403 | case BUSSTATE_TRISTATE: | |
404 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
405 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
406 | break; | |
407 | default: | |
408 | return -EINVAL; | |
409 | } | |
410 | hwif->bus_state = state; | |
411 | return 0; | |
412 | } | |
413 | ||
414 | /** | |
438c4702 | 415 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
416 | * @drive: drive we are resetting |
417 | * | |
418 | * Poll the SATA phy and see whether it has come back from the dead | |
419 | * yet. | |
420 | */ | |
438c4702 BZ |
421 | |
422 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 LT |
423 | { |
424 | if (SATA_STATUS_REG) { | |
425 | ide_hwif_t *hwif = HWIF(drive); | |
426 | ||
0ecdca26 BZ |
427 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
428 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 429 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 430 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
431 | HWGROUP(drive)->polling = 0; |
432 | return ide_started; | |
433 | } | |
1da177e4 | 434 | } |
438c4702 BZ |
435 | |
436 | return 0; | |
1da177e4 LT |
437 | } |
438 | ||
439 | /** | |
438c4702 | 440 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
441 | * @drive: IDE device being reset |
442 | * | |
443 | * For the SATA devices we need to handle recalibration/geometry | |
444 | * differently | |
445 | */ | |
1da177e4 | 446 | |
438c4702 BZ |
447 | static void sil_sata_pre_reset(ide_drive_t *drive) |
448 | { | |
449 | if (drive->media == ide_disk) { | |
1da177e4 LT |
450 | drive->special.b.set_geometry = 0; |
451 | drive->special.b.recalibrate = 0; | |
452 | } | |
453 | } | |
454 | ||
1da177e4 LT |
455 | /** |
456 | * proc_reports_siimage - add siimage controller to proc | |
457 | * @dev: PCI device | |
458 | * @clocking: SCSC value | |
459 | * @name: controller name | |
460 | * | |
461 | * Report the clocking mode of the controller and add it to | |
462 | * the /proc interface layer | |
463 | */ | |
464 | ||
465 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
466 | { | |
467 | if (!pdev_is_sata(dev)) { | |
468 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
469 | clocking &= 0x03; | |
470 | switch (clocking) { | |
471 | case 0x03: printk("DISABLED!\n"); break; | |
472 | case 0x02: printk("== 2X PCI\n"); break; | |
473 | case 0x01: printk("== 133\n"); break; | |
474 | case 0x00: printk("== 100\n"); break; | |
475 | } | |
476 | } | |
477 | } | |
478 | ||
479 | /** | |
480 | * setup_mmio_siimage - switch an SI controller into MMIO | |
481 | * @dev: PCI device we are configuring | |
482 | * @name: device name | |
483 | * | |
484 | * Attempt to put the device into mmio mode. There are some slight | |
485 | * complications here with certain systems where the mmio bar isnt | |
486 | * mapped so we have to be sure we can fall back to I/O. | |
487 | */ | |
488 | ||
489 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
490 | { | |
491 | unsigned long bar5 = pci_resource_start(dev, 5); | |
492 | unsigned long barsize = pci_resource_len(dev, 5); | |
493 | u8 tmpbyte = 0; | |
494 | void __iomem *ioaddr; | |
d868dd19 | 495 | u32 tmp, irq_mask; |
1da177e4 LT |
496 | |
497 | /* | |
498 | * Drop back to PIO if we can't map the mmio. Some | |
499 | * systems seem to get terminally confused in the PCI | |
500 | * spaces. | |
501 | */ | |
502 | ||
503 | if(!request_mem_region(bar5, barsize, name)) | |
504 | { | |
505 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
506 | return 0; | |
507 | } | |
508 | ||
509 | ioaddr = ioremap(bar5, barsize); | |
510 | ||
511 | if (ioaddr == NULL) | |
512 | { | |
513 | release_mem_region(bar5, barsize); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | pci_set_master(dev); | |
518 | pci_set_drvdata(dev, (void *) ioaddr); | |
519 | ||
520 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
521 | /* make sure IDE0/1 interrupts are not masked */ |
522 | irq_mask = (1 << 22) | (1 << 23); | |
523 | tmp = readl(ioaddr + 0x48); | |
524 | if (tmp & irq_mask) { | |
525 | tmp &= ~irq_mask; | |
526 | writel(tmp, ioaddr + 0x48); | |
527 | readl(ioaddr + 0x48); /* flush */ | |
528 | } | |
1da177e4 LT |
529 | writel(0, ioaddr + 0x148); |
530 | writel(0, ioaddr + 0x1C8); | |
531 | } | |
532 | ||
533 | writeb(0, ioaddr + 0xB4); | |
534 | writeb(0, ioaddr + 0xF4); | |
535 | tmpbyte = readb(ioaddr + 0x4A); | |
536 | ||
537 | switch(tmpbyte & 0x30) { | |
538 | case 0x00: | |
539 | /* In 100 MHz clocking, try and switch to 133 */ | |
540 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
541 | break; | |
542 | case 0x10: | |
543 | /* On 133Mhz clocking */ | |
544 | break; | |
545 | case 0x20: | |
546 | /* On PCIx2 clocking */ | |
547 | break; | |
548 | case 0x30: | |
549 | /* Clocking is disabled */ | |
550 | /* 133 clock attempt to force it on */ | |
551 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
552 | break; | |
553 | } | |
554 | ||
555 | writeb( 0x72, ioaddr + 0xA1); | |
556 | writew( 0x328A, ioaddr + 0xA2); | |
557 | writel(0x62DD62DD, ioaddr + 0xA4); | |
558 | writel(0x43924392, ioaddr + 0xA8); | |
559 | writel(0x40094009, ioaddr + 0xAC); | |
560 | writeb( 0x72, ioaddr + 0xE1); | |
561 | writew( 0x328A, ioaddr + 0xE2); | |
562 | writel(0x62DD62DD, ioaddr + 0xE4); | |
563 | writel(0x43924392, ioaddr + 0xE8); | |
564 | writel(0x40094009, ioaddr + 0xEC); | |
565 | ||
566 | if (pdev_is_sata(dev)) { | |
567 | writel(0xFFFF0000, ioaddr + 0x108); | |
568 | writel(0xFFFF0000, ioaddr + 0x188); | |
569 | writel(0x00680000, ioaddr + 0x148); | |
570 | writel(0x00680000, ioaddr + 0x1C8); | |
571 | } | |
572 | ||
573 | tmpbyte = readb(ioaddr + 0x4A); | |
574 | ||
575 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
576 | return 1; | |
577 | } | |
578 | ||
579 | /** | |
580 | * init_chipset_siimage - set up an SI device | |
581 | * @dev: PCI device | |
582 | * @name: device name | |
583 | * | |
584 | * Perform the initial PCI set up for this device. Attempt to switch | |
585 | * to 133MHz clocking if the system isn't already set up to do it. | |
586 | */ | |
587 | ||
588 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
589 | { | |
fc212bb1 | 590 | u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0; |
1da177e4 | 591 | |
fc212bb1 | 592 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 LT |
593 | |
594 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
595 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
596 | if (setup_mmio_siimage(dev, name)) { | |
597 | return 0; | |
598 | } | |
599 | } | |
600 | ||
601 | pci_write_config_byte(dev, 0x80, 0x00); | |
602 | pci_write_config_byte(dev, 0x84, 0x00); | |
603 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
604 | switch(tmpbyte & 0x30) { | |
605 | case 0x00: | |
606 | /* 133 clock attempt to force it on */ | |
607 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
608 | case 0x30: | |
609 | /* if clocking is disabled */ | |
610 | /* 133 clock attempt to force it on */ | |
611 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
612 | case 0x10: | |
613 | /* 133 already */ | |
614 | break; | |
615 | case 0x20: | |
616 | /* BIOS set PCI x2 clocking */ | |
617 | break; | |
618 | } | |
619 | ||
620 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
621 | ||
622 | pci_write_config_byte(dev, 0xA1, 0x72); | |
623 | pci_write_config_word(dev, 0xA2, 0x328A); | |
624 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
625 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
626 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
627 | pci_write_config_byte(dev, 0xB1, 0x72); | |
628 | pci_write_config_word(dev, 0xB2, 0x328A); | |
629 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
630 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
631 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
632 | ||
633 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | /** | |
638 | * init_mmio_iops_siimage - set up the iops for MMIO | |
639 | * @hwif: interface to set up | |
640 | * | |
641 | * The basic setup here is fairly simple, we can use standard MMIO | |
642 | * operations. However we do have to set the taskfile register offsets | |
643 | * by hand as there isnt a standard defined layout for them this | |
644 | * time. | |
645 | * | |
646 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 647 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
648 | */ |
649 | ||
650 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
651 | { | |
36501650 | 652 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
653 | void *addr = pci_get_drvdata(dev); |
654 | u8 ch = hwif->channel; | |
655 | hw_regs_t hw; | |
656 | unsigned long base; | |
657 | ||
658 | /* | |
659 | * Fill in the basic HWIF bits | |
660 | */ | |
661 | ||
662 | default_hwif_mmiops(hwif); | |
663 | hwif->hwif_data = addr; | |
664 | ||
665 | /* | |
666 | * Now set up the hw. We have to do this ourselves as | |
59c51591 | 667 | * the MMIO layout isnt the same as the standard port |
1da177e4 LT |
668 | * based I/O |
669 | */ | |
670 | ||
671 | memset(&hw, 0, sizeof(hw_regs_t)); | |
672 | ||
673 | base = (unsigned long)addr; | |
674 | if (ch) | |
675 | base += 0xC0; | |
676 | else | |
677 | base += 0x80; | |
678 | ||
679 | /* | |
680 | * The buffered task file doesn't have status/control | |
681 | * so we can't currently use it sanely since we want to | |
682 | * use LBA48 mode. | |
683 | */ | |
1da177e4 LT |
684 | hw.io_ports[IDE_DATA_OFFSET] = base; |
685 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
686 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
687 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
688 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
689 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
690 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
691 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
692 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
693 | ||
694 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
695 | ||
696 | if (pdev_is_sata(dev)) { | |
697 | base = (unsigned long)addr; | |
698 | if (ch) | |
699 | base += 0x80; | |
700 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
701 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
702 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
703 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
704 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
705 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
706 | } | |
707 | ||
9239b333 | 708 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); |
1da177e4 | 709 | |
9239b333 | 710 | hwif->irq = dev->irq; |
1da177e4 | 711 | |
9239b333 | 712 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
713 | |
714 | hwif->mmio = 1; | |
1da177e4 LT |
715 | } |
716 | ||
717 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
718 | { | |
719 | const char *s = &drive->id->model[0]; | |
720 | unsigned len; | |
721 | ||
1da177e4 LT |
722 | len = strnlen(s, sizeof(drive->id->model)); |
723 | ||
724 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
725 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
726 | (!memcmp(s + len - 3, "ASL", 3))) { | |
727 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
728 | "errata fix\n", drive->name); | |
729 | return 1; | |
730 | } | |
731 | } | |
732 | return 0; | |
733 | } | |
734 | ||
735 | /** | |
f01393e4 BZ |
736 | * sil_quirkproc - post probe fixups |
737 | * @drive: drive | |
1da177e4 LT |
738 | * |
739 | * Called after drive probe we use this to decide whether the | |
740 | * Seagate fixup must be applied. This used to be in init_iops but | |
741 | * that can occur before we know what drives are present. | |
742 | */ | |
743 | ||
f01393e4 | 744 | static void __devinit sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 745 | { |
f01393e4 BZ |
746 | ide_hwif_t *hwif = drive->hwif; |
747 | ||
1da177e4 | 748 | /* Try and raise the rqsize */ |
f01393e4 | 749 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
750 | hwif->rqsize = 128; |
751 | } | |
752 | ||
753 | /** | |
754 | * init_iops_siimage - set up iops | |
755 | * @hwif: interface to set up | |
756 | * | |
757 | * Do the basic setup for the SIIMAGE hardware interface | |
758 | * and then do the MMIO setup if we can. This is the first | |
759 | * look in we get for setting up the hwif so that we | |
760 | * can get the iops right before using them. | |
761 | */ | |
762 | ||
763 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
764 | { | |
36501650 BZ |
765 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
766 | ||
1da177e4 LT |
767 | hwif->hwif_data = NULL; |
768 | ||
769 | /* Pessimal until we finish probing */ | |
770 | hwif->rqsize = 15; | |
771 | ||
36501650 | 772 | if (pci_get_drvdata(dev) == NULL) |
1da177e4 | 773 | return; |
fc212bb1 | 774 | |
1da177e4 LT |
775 | init_mmio_iops_siimage(hwif); |
776 | } | |
777 | ||
778 | /** | |
779 | * ata66_siimage - check for 80 pin cable | |
780 | * @hwif: interface to check | |
781 | * | |
782 | * Check for the presence of an ATA66 capable cable on the | |
783 | * interface. | |
784 | */ | |
785 | ||
49521f97 | 786 | static u8 __devinit ata66_siimage(ide_hwif_t *hwif) |
1da177e4 | 787 | { |
36501650 | 788 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 789 | unsigned long addr = siimage_selreg(hwif, 0); |
49521f97 BZ |
790 | u8 ata66 = 0; |
791 | ||
36501650 BZ |
792 | if (pci_get_drvdata(dev) == NULL) |
793 | pci_read_config_byte(dev, addr, &ata66); | |
49521f97 BZ |
794 | else |
795 | ata66 = hwif->INB(addr); | |
1da177e4 | 796 | |
49521f97 | 797 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
798 | } |
799 | ||
800 | /** | |
801 | * init_hwif_siimage - set up hwif structs | |
802 | * @hwif: interface to set up | |
803 | * | |
804 | * We do the basic set up of the interface structure. The SIIMAGE | |
805 | * requires several custom handlers so we override the default | |
806 | * ide DMA handlers appropriately | |
807 | */ | |
808 | ||
809 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
810 | { | |
438c4702 BZ |
811 | u8 sata = is_sata(hwif); |
812 | ||
26bcb879 | 813 | hwif->set_pio_mode = &sil_set_pio_mode; |
88b2b32b | 814 | hwif->set_dma_mode = &sil_set_dma_mode; |
f01393e4 | 815 | hwif->quirkproc = &sil_quirkproc; |
1da177e4 | 816 | |
438c4702 | 817 | if (sata) { |
19c1ef5f AC |
818 | static int first = 1; |
819 | ||
438c4702 BZ |
820 | hwif->busproc = &sil_sata_busproc; |
821 | hwif->reset_poll = &sil_sata_reset_poll; | |
822 | hwif->pre_reset = &sil_sata_pre_reset; | |
823 | hwif->udma_filter = &sil_sata_udma_filter; | |
1da177e4 | 824 | |
19c1ef5f AC |
825 | if (first) { |
826 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
827 | first = 0; | |
828 | } | |
438c4702 BZ |
829 | } else |
830 | hwif->udma_filter = &sil_pata_udma_filter; | |
328dcbb6 | 831 | |
328dcbb6 | 832 | if (hwif->dma_base == 0) |
1da177e4 | 833 | return; |
1da177e4 | 834 | |
438c4702 | 835 | if (sata) |
33c1002e | 836 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
1da177e4 | 837 | |
49521f97 BZ |
838 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
839 | hwif->cbl = ata66_siimage(hwif); | |
1da177e4 LT |
840 | |
841 | if (hwif->mmio) { | |
842 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
843 | } else { | |
844 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
845 | } | |
1da177e4 LT |
846 | } |
847 | ||
848 | #define DECLARE_SII_DEV(name_str) \ | |
849 | { \ | |
850 | .name = name_str, \ | |
851 | .init_chipset = init_chipset_siimage, \ | |
852 | .init_iops = init_iops_siimage, \ | |
853 | .init_hwif = init_hwif_siimage, \ | |
7cab14a7 | 854 | .host_flags = IDE_HFLAG_BOOTABLE, \ |
4099d143 | 855 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
856 | .mwdma_mask = ATA_MWDMA2, \ |
857 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
858 | } |
859 | ||
85620436 | 860 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
1da177e4 LT |
861 | /* 0 */ DECLARE_SII_DEV("SiI680"), |
862 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
863 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
864 | }; | |
865 | ||
866 | /** | |
867 | * siimage_init_one - pci layer discovery entry | |
868 | * @dev: PCI device | |
869 | * @id: ident table entry | |
870 | * | |
871 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
872 | * We then use the IDE PCI generic helper to do most of the work. | |
873 | */ | |
874 | ||
875 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
876 | { | |
877 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
878 | } | |
879 | ||
9cbcc5e3 BZ |
880 | static const struct pci_device_id siimage_pci_tbl[] = { |
881 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 882 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
883 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
884 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 }, | |
1da177e4 LT |
885 | #endif |
886 | { 0, }, | |
887 | }; | |
888 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
889 | ||
890 | static struct pci_driver driver = { | |
891 | .name = "SiI_IDE", | |
892 | .id_table = siimage_pci_tbl, | |
893 | .probe = siimage_init_one, | |
894 | }; | |
895 | ||
82ab1eec | 896 | static int __init siimage_ide_init(void) |
1da177e4 LT |
897 | { |
898 | return ide_pci_register_driver(&driver); | |
899 | } | |
900 | ||
901 | module_init(siimage_ide_init); | |
902 | ||
903 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
904 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
905 | MODULE_LICENSE("GPL"); |