Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
7b255436 | 4 | * Copyright (C) 2007-2008 MontaVista Software, Inc. |
165701d9 | 5 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
7b255436 | 20 | * ensure the system is set up for ATA100/UDMA5, not UDMA6. |
1da177e4 LT |
21 | * |
22 | * If you are using WD drives with SATA bridges you must set the | |
7b255436 | 23 | * drive to "Single". "Master" will hang. |
1da177e4 LT |
24 | * |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
35 | * - IORDY fixes | |
36 | * - VDMA support | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
1da177e4 LT |
42 | #include <linux/hdreg.h> |
43 | #include <linux/ide.h> | |
44 | #include <linux/init.h> | |
7b255436 | 45 | #include <linux/io.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /** |
48 | * pdev_is_sata - check if device is SATA | |
49 | * @pdev: PCI device to check | |
7b255436 | 50 | * |
1da177e4 LT |
51 | * Returns true if this is a SATA controller |
52 | */ | |
7b255436 | 53 | |
1da177e4 LT |
54 | static int pdev_is_sata(struct pci_dev *pdev) |
55 | { | |
438c4702 | 56 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
7b255436 SS |
57 | switch (pdev->device) { |
58 | case PCI_DEVICE_ID_SII_3112: | |
59 | case PCI_DEVICE_ID_SII_1210SA: | |
60 | return 1; | |
61 | case PCI_DEVICE_ID_SII_680: | |
62 | return 0; | |
1da177e4 LT |
63 | } |
64 | BUG(); | |
438c4702 | 65 | #endif |
1da177e4 LT |
66 | return 0; |
67 | } | |
438c4702 | 68 | |
1da177e4 LT |
69 | /** |
70 | * is_sata - check if hwif is SATA | |
71 | * @hwif: interface to check | |
7b255436 | 72 | * |
1da177e4 LT |
73 | * Returns true if this is a SATA controller |
74 | */ | |
7b255436 | 75 | |
1da177e4 LT |
76 | static inline int is_sata(ide_hwif_t *hwif) |
77 | { | |
36501650 | 78 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
79 | } |
80 | ||
81 | /** | |
82 | * siimage_selreg - return register base | |
83 | * @hwif: interface | |
84 | * @r: config offset | |
85 | * | |
86 | * Turn a config register offset into the right address in either | |
87 | * PCI space or MMIO space to access the control register in question | |
7b255436 SS |
88 | * Thankfully this is a configuration operation, so isn't performance |
89 | * critical. | |
1da177e4 | 90 | */ |
7b255436 | 91 | |
1da177e4 LT |
92 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
93 | { | |
94 | unsigned long base = (unsigned long)hwif->hwif_data; | |
7b255436 | 95 | |
1da177e4 | 96 | base += 0xA0 + r; |
13572144 | 97 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 98 | base += hwif->channel << 6; |
1da177e4 | 99 | else |
7b255436 | 100 | base += hwif->channel << 4; |
1da177e4 LT |
101 | return base; |
102 | } | |
7b255436 | 103 | |
1da177e4 LT |
104 | /** |
105 | * siimage_seldev - return register base | |
106 | * @hwif: interface | |
107 | * @r: config offset | |
108 | * | |
109 | * Turn a config register offset into the right address in either | |
110 | * PCI space or MMIO space to access the control register in question | |
111 | * including accounting for the unit shift. | |
112 | */ | |
7b255436 | 113 | |
1da177e4 LT |
114 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
115 | { | |
116 | ide_hwif_t *hwif = HWIF(drive); | |
7b255436 SS |
117 | unsigned long base = (unsigned long)hwif->hwif_data; |
118 | ||
1da177e4 | 119 | base += 0xA0 + r; |
13572144 | 120 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 121 | base += hwif->channel << 6; |
1da177e4 | 122 | else |
7b255436 | 123 | base += hwif->channel << 4; |
1da177e4 LT |
124 | base |= drive->select.b.unit << drive->select.b.unit; |
125 | return base; | |
126 | } | |
127 | ||
165701d9 BZ |
128 | static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) |
129 | { | |
4c674235 | 130 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
131 | u8 tmp = 0; |
132 | ||
4c674235 | 133 | if (host->host_priv) |
165701d9 BZ |
134 | tmp = readb((void __iomem *)addr); |
135 | else | |
136 | pci_read_config_byte(dev, addr, &tmp); | |
137 | ||
138 | return tmp; | |
139 | } | |
140 | ||
141 | static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) | |
142 | { | |
4c674235 | 143 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
144 | u16 tmp = 0; |
145 | ||
4c674235 | 146 | if (host->host_priv) |
165701d9 BZ |
147 | tmp = readw((void __iomem *)addr); |
148 | else | |
149 | pci_read_config_word(dev, addr, &tmp); | |
150 | ||
151 | return tmp; | |
152 | } | |
153 | ||
154 | static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) | |
155 | { | |
4c674235 BZ |
156 | struct ide_host *host = pci_get_drvdata(dev); |
157 | ||
158 | if (host->host_priv) | |
165701d9 BZ |
159 | writeb(val, (void __iomem *)addr); |
160 | else | |
161 | pci_write_config_byte(dev, addr, val); | |
162 | } | |
163 | ||
164 | static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) | |
165 | { | |
4c674235 BZ |
166 | struct ide_host *host = pci_get_drvdata(dev); |
167 | ||
168 | if (host->host_priv) | |
165701d9 BZ |
169 | writew(val, (void __iomem *)addr); |
170 | else | |
171 | pci_write_config_word(dev, addr, val); | |
172 | } | |
173 | ||
174 | static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) | |
175 | { | |
4c674235 BZ |
176 | struct ide_host *host = pci_get_drvdata(dev); |
177 | ||
178 | if (host->host_priv) | |
165701d9 BZ |
179 | writel(val, (void __iomem *)addr); |
180 | else | |
181 | pci_write_config_dword(dev, addr, val); | |
182 | } | |
183 | ||
1da177e4 | 184 | /** |
2d5eaa6d BZ |
185 | * sil_udma_filter - compute UDMA mask |
186 | * @drive: IDE device | |
187 | * | |
188 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 189 | * |
1da177e4 | 190 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 191 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 192 | */ |
2d5eaa6d | 193 | |
438c4702 | 194 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 195 | { |
7b255436 SS |
196 | ide_hwif_t *hwif = drive->hwif; |
197 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
198 | unsigned long base = (unsigned long)hwif->hwif_data; | |
199 | u8 scsc, mask = 0; | |
1da177e4 | 200 | |
13572144 BZ |
201 | base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; |
202 | ||
203 | scsc = sil_ioread8(dev, base); | |
1da177e4 | 204 | |
7b255436 SS |
205 | switch (scsc & 0x30) { |
206 | case 0x10: /* 133 */ | |
438c4702 | 207 | mask = ATA_UDMA6; |
7b255436 SS |
208 | break; |
209 | case 0x20: /* 2xPCI */ | |
438c4702 | 210 | mask = ATA_UDMA6; |
7b255436 SS |
211 | break; |
212 | case 0x00: /* 100 */ | |
438c4702 | 213 | mask = ATA_UDMA5; |
7b255436 SS |
214 | break; |
215 | default: /* Disabled ? */ | |
1da177e4 | 216 | BUG(); |
7b255436 | 217 | } |
438c4702 | 218 | |
2d5eaa6d | 219 | return mask; |
1da177e4 LT |
220 | } |
221 | ||
438c4702 BZ |
222 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
223 | { | |
224 | return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
225 | } | |
226 | ||
1da177e4 | 227 | /** |
88b2b32b BZ |
228 | * sil_set_pio_mode - set host controller for PIO mode |
229 | * @drive: drive | |
230 | * @pio: PIO mode number | |
1da177e4 LT |
231 | * |
232 | * Load the timing settings for this device mode into the | |
233 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
234 | * monitoring (bit 9). The TF timing is bits 31:16 | |
235 | */ | |
328dcbb6 | 236 | |
88b2b32b | 237 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 238 | { |
7b255436 SS |
239 | static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
240 | static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
328dcbb6 | 241 | |
1da177e4 | 242 | ide_hwif_t *hwif = HWIF(drive); |
165701d9 | 243 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
a87a87cc | 244 | ide_drive_t *pair = ide_get_paired_drive(drive); |
1da177e4 LT |
245 | u32 speedt = 0; |
246 | u16 speedp = 0; | |
247 | unsigned long addr = siimage_seldev(drive, 0x04); | |
7b255436 | 248 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); |
ffe5415c | 249 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 250 | u8 tf_pio = pio; |
13572144 BZ |
251 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
252 | u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
253 | : (mmio ? 0xB4 : 0x80); | |
ffe5415c BZ |
254 | u8 mode = 0; |
255 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
256 | |
257 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
258 | if (pair->present) { | |
2134758d | 259 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
260 | |
261 | if (pair_pio < tf_pio) | |
262 | tf_pio = pair_pio; | |
1da177e4 | 263 | } |
075cb655 | 264 | |
328dcbb6 BZ |
265 | /* cheat for now and use the docs */ |
266 | speedp = data_speed[pio]; | |
267 | speedt = tf_speed[tf_pio]; | |
268 | ||
165701d9 BZ |
269 | sil_iowrite16(dev, speedp, addr); |
270 | sil_iowrite16(dev, speedt, tfaddr); | |
271 | ||
272 | /* now set up IORDY */ | |
273 | speedp = sil_ioread16(dev, tfaddr - 2); | |
274 | speedp &= ~0x200; | |
275 | if (pio > 2) | |
276 | speedp |= 0x200; | |
277 | sil_iowrite16(dev, speedp, tfaddr - 2); | |
278 | ||
279 | mode = sil_ioread8(dev, base + addr_mask); | |
280 | mode &= ~(unit ? 0x30 : 0x03); | |
7b255436 | 281 | mode |= unit ? 0x10 : 0x01; |
165701d9 | 282 | sil_iowrite8(dev, mode, base + addr_mask); |
1da177e4 LT |
283 | } |
284 | ||
1da177e4 | 285 | /** |
88b2b32b BZ |
286 | * sil_set_dma_mode - set host controller for DMA mode |
287 | * @drive: drive | |
288 | * @speed: DMA mode | |
1da177e4 | 289 | * |
88b2b32b | 290 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 291 | */ |
f212ff28 | 292 | |
88b2b32b | 293 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 294 | { |
7b255436 SS |
295 | static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; |
296 | static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
297 | static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
1da177e4 LT |
298 | |
299 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 300 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
301 | u16 ultra = 0, multi = 0; |
302 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 | 303 | unsigned long base = (unsigned long)hwif->hwif_data; |
13572144 BZ |
304 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
305 | u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
306 | : (mmio ? 0xB4 : 0x80); | |
1da177e4 LT |
307 | unsigned long ma = siimage_seldev(drive, 0x08); |
308 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
309 | ||
13572144 | 310 | scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); |
7b255436 | 311 | mode = sil_ioread8 (dev, base + addr_mask); |
165701d9 BZ |
312 | multi = sil_ioread16(dev, ma); |
313 | ultra = sil_ioread16(dev, ua); | |
1da177e4 | 314 | |
7b255436 | 315 | mode &= ~(unit ? 0x30 : 0x03); |
1da177e4 LT |
316 | ultra &= ~0x3F; |
317 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
318 | ||
319 | scsc = is_sata(hwif) ? 1 : scsc; | |
320 | ||
4db90a14 | 321 | if (speed >= XFER_UDMA_0) { |
7b255436 SS |
322 | multi = dma[2]; |
323 | ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : | |
324 | ultra5[speed - XFER_UDMA_0]; | |
325 | mode |= unit ? 0x30 : 0x03; | |
4db90a14 BZ |
326 | } else { |
327 | multi = dma[speed - XFER_MW_DMA_0]; | |
7b255436 | 328 | mode |= unit ? 0x20 : 0x02; |
1da177e4 LT |
329 | } |
330 | ||
7b255436 | 331 | sil_iowrite8 (dev, mode, base + addr_mask); |
165701d9 BZ |
332 | sil_iowrite16(dev, multi, ma); |
333 | sil_iowrite16(dev, ultra, ua); | |
1da177e4 LT |
334 | } |
335 | ||
1da177e4 | 336 | /* returns 1 if dma irq issued, 0 otherwise */ |
5e37bdc0 | 337 | static int siimage_io_dma_test_irq(ide_drive_t *drive) |
1da177e4 LT |
338 | { |
339 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 340 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
341 | u8 dma_altstat = 0; |
342 | unsigned long addr = siimage_selreg(hwif, 1); | |
343 | ||
344 | /* return 1 if INTR asserted */ | |
cab7f8ed | 345 | if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4) |
1da177e4 LT |
346 | return 1; |
347 | ||
348 | /* return 1 if Device INTR asserted */ | |
36501650 | 349 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 | 350 | if (dma_altstat & 8) |
7b255436 SS |
351 | return 0; /* return 1; */ |
352 | ||
1da177e4 LT |
353 | return 0; |
354 | } | |
355 | ||
1da177e4 | 356 | /** |
5e37bdc0 | 357 | * siimage_mmio_dma_test_irq - check we caused an IRQ |
1da177e4 LT |
358 | * @drive: drive we are testing |
359 | * | |
360 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
361 | * SATA status interrupts, if so we clean them up and continue. | |
362 | */ | |
5e37bdc0 BZ |
363 | |
364 | static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |
1da177e4 LT |
365 | { |
366 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 | 367 | unsigned long addr = siimage_selreg(hwif, 0x1); |
835457de BZ |
368 | void __iomem *sata_error_addr |
369 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; | |
1da177e4 | 370 | |
835457de | 371 | if (sata_error_addr) { |
7b255436 SS |
372 | unsigned long base = (unsigned long)hwif->hwif_data; |
373 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
374 | u8 watchdog = 0; | |
835457de | 375 | |
1da177e4 | 376 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
835457de BZ |
377 | u32 sata_error = readl(sata_error_addr); |
378 | ||
379 | writel(sata_error, sata_error_addr); | |
1da177e4 | 380 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
381 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
382 | "watchdog = %d, %s\n", | |
7b255436 SS |
383 | drive->name, sata_error, watchdog, __func__); |
384 | } else | |
1da177e4 | 385 | watchdog = (ext_stat & 0x8000) ? 1 : 0; |
1da177e4 | 386 | |
7b255436 | 387 | ext_stat >>= 16; |
1da177e4 LT |
388 | if (!(ext_stat & 0x0404) && !watchdog) |
389 | return 0; | |
390 | } | |
391 | ||
392 | /* return 1 if INTR asserted */ | |
cab7f8ed | 393 | if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) |
1da177e4 LT |
394 | return 1; |
395 | ||
396 | /* return 1 if Device INTR asserted */ | |
7b255436 SS |
397 | if (readb((void __iomem *)addr) & 8) |
398 | return 0; /* return 1; */ | |
1da177e4 LT |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
5e37bdc0 BZ |
403 | static int siimage_dma_test_irq(ide_drive_t *drive) |
404 | { | |
13572144 | 405 | if (drive->hwif->host_flags & IDE_HFLAG_MMIO) |
5e37bdc0 BZ |
406 | return siimage_mmio_dma_test_irq(drive); |
407 | else | |
408 | return siimage_io_dma_test_irq(drive); | |
409 | } | |
410 | ||
1da177e4 | 411 | /** |
438c4702 | 412 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
413 | * @drive: drive we are resetting |
414 | * | |
415 | * Poll the SATA phy and see whether it has come back from the dead | |
416 | * yet. | |
417 | */ | |
438c4702 BZ |
418 | |
419 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 | 420 | { |
835457de BZ |
421 | ide_hwif_t *hwif = drive->hwif; |
422 | void __iomem *sata_status_addr | |
423 | = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; | |
424 | ||
425 | if (sata_status_addr) { | |
426 | /* SATA Status is available only when in MMIO mode */ | |
427 | u32 sata_stat = readl(sata_status_addr); | |
1da177e4 | 428 | |
835457de | 429 | if ((sata_stat & 0x03) != 0x03) { |
1da177e4 | 430 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
835457de | 431 | hwif->name, sata_stat); |
64a8f00f | 432 | return -ENXIO; |
1da177e4 | 433 | } |
1da177e4 | 434 | } |
438c4702 BZ |
435 | |
436 | return 0; | |
1da177e4 LT |
437 | } |
438 | ||
439 | /** | |
438c4702 | 440 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
441 | * @drive: IDE device being reset |
442 | * | |
443 | * For the SATA devices we need to handle recalibration/geometry | |
444 | * differently | |
445 | */ | |
1da177e4 | 446 | |
438c4702 BZ |
447 | static void sil_sata_pre_reset(ide_drive_t *drive) |
448 | { | |
449 | if (drive->media == ide_disk) { | |
1da177e4 LT |
450 | drive->special.b.set_geometry = 0; |
451 | drive->special.b.recalibrate = 0; | |
452 | } | |
453 | } | |
454 | ||
1da177e4 LT |
455 | /** |
456 | * init_chipset_siimage - set up an SI device | |
457 | * @dev: PCI device | |
458 | * @name: device name | |
459 | * | |
460 | * Perform the initial PCI set up for this device. Attempt to switch | |
7b255436 | 461 | * to 133 MHz clocking if the system isn't already set up to do it. |
1da177e4 LT |
462 | */ |
463 | ||
7b255436 SS |
464 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, |
465 | const char *name) | |
1da177e4 | 466 | { |
4c674235 BZ |
467 | struct ide_host *host = pci_get_drvdata(dev); |
468 | void __iomem *ioaddr = host->host_priv; | |
165701d9 | 469 | unsigned long base, scsc_addr; |
4c674235 | 470 | u8 rev = dev->revision, tmp; |
1da177e4 | 471 | |
fc212bb1 | 472 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 | 473 | |
4c674235 BZ |
474 | if (ioaddr) |
475 | pci_set_master(dev); | |
165701d9 BZ |
476 | |
477 | base = (unsigned long)ioaddr; | |
478 | ||
479 | if (ioaddr && pdev_is_sata(dev)) { | |
480 | u32 tmp32, irq_mask; | |
481 | ||
482 | /* make sure IDE0/1 interrupts are not masked */ | |
483 | irq_mask = (1 << 22) | (1 << 23); | |
484 | tmp32 = readl(ioaddr + 0x48); | |
485 | if (tmp32 & irq_mask) { | |
486 | tmp32 &= ~irq_mask; | |
487 | writel(tmp32, ioaddr + 0x48); | |
488 | readl(ioaddr + 0x48); /* flush */ | |
1da177e4 | 489 | } |
165701d9 BZ |
490 | writel(0, ioaddr + 0x148); |
491 | writel(0, ioaddr + 0x1C8); | |
1da177e4 LT |
492 | } |
493 | ||
165701d9 BZ |
494 | sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); |
495 | sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); | |
496 | ||
497 | scsc_addr = base ? (base + 0x4A) : 0x8A; | |
498 | tmp = sil_ioread8(dev, scsc_addr); | |
499 | ||
500 | switch (tmp & 0x30) { | |
501 | case 0x00: | |
7b255436 | 502 | /* On 100 MHz clocking, try and switch to 133 MHz */ |
165701d9 BZ |
503 | sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
504 | break; | |
505 | case 0x30: | |
506 | /* Clocking is disabled, attempt to force 133MHz clocking. */ | |
507 | sil_iowrite8(dev, tmp & ~0x20, scsc_addr); | |
508 | case 0x10: | |
509 | /* On 133Mhz clocking. */ | |
510 | break; | |
511 | case 0x20: | |
512 | /* On PCIx2 clocking. */ | |
513 | break; | |
1da177e4 LT |
514 | } |
515 | ||
165701d9 | 516 | tmp = sil_ioread8(dev, scsc_addr); |
1da177e4 | 517 | |
7b255436 | 518 | sil_iowrite8 (dev, 0x72, base + 0xA1); |
165701d9 BZ |
519 | sil_iowrite16(dev, 0x328A, base + 0xA2); |
520 | sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); | |
521 | sil_iowrite32(dev, 0x43924392, base + 0xA8); | |
522 | sil_iowrite32(dev, 0x40094009, base + 0xAC); | |
7b255436 | 523 | sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); |
165701d9 BZ |
524 | sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
525 | sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); | |
526 | sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); | |
527 | sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); | |
528 | ||
529 | if (base && pdev_is_sata(dev)) { | |
530 | writel(0xFFFF0000, ioaddr + 0x108); | |
531 | writel(0xFFFF0000, ioaddr + 0x188); | |
532 | writel(0x00680000, ioaddr + 0x148); | |
533 | writel(0x00680000, ioaddr + 0x1C8); | |
534 | } | |
535 | ||
24cc434a BZ |
536 | /* report the clocking mode of the controller */ |
537 | if (!pdev_is_sata(dev)) { | |
538 | static const char *clk_str[] = | |
539 | { "== 100", "== 133", "== 2X PCI", "DISABLED!" }; | |
540 | ||
541 | tmp >>= 4; | |
542 | printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]); | |
543 | } | |
1da177e4 | 544 | |
1da177e4 LT |
545 | return 0; |
546 | } | |
547 | ||
548 | /** | |
549 | * init_mmio_iops_siimage - set up the iops for MMIO | |
550 | * @hwif: interface to set up | |
551 | * | |
552 | * The basic setup here is fairly simple, we can use standard MMIO | |
553 | * operations. However we do have to set the taskfile register offsets | |
7b255436 | 554 | * by hand as there isn't a standard defined layout for them this time. |
1da177e4 LT |
555 | * |
556 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 557 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
558 | */ |
559 | ||
560 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
561 | { | |
36501650 | 562 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 BZ |
563 | struct ide_host *host = pci_get_drvdata(dev); |
564 | void *addr = host->host_priv; | |
1da177e4 | 565 | u8 ch = hwif->channel; |
4c3032d8 | 566 | struct ide_io_ports *io_ports = &hwif->io_ports; |
7b255436 | 567 | unsigned long base; |
4c3032d8 | 568 | |
1da177e4 | 569 | /* |
7b255436 | 570 | * Fill in the basic hwif bits |
1da177e4 | 571 | */ |
c5dd43ec | 572 | hwif->host_flags |= IDE_HFLAG_MMIO; |
761052e6 | 573 | |
7b255436 | 574 | hwif->hwif_data = addr; |
1da177e4 LT |
575 | |
576 | /* | |
7b255436 SS |
577 | * Now set up the hw. We have to do this ourselves as the |
578 | * MMIO layout isn't the same as the standard port based I/O. | |
1da177e4 | 579 | */ |
4c3032d8 | 580 | memset(io_ports, 0, sizeof(*io_ports)); |
1da177e4 LT |
581 | |
582 | base = (unsigned long)addr; | |
583 | if (ch) | |
584 | base += 0xC0; | |
585 | else | |
586 | base += 0x80; | |
587 | ||
588 | /* | |
7b255436 SS |
589 | * The buffered task file doesn't have status/control, so we |
590 | * can't currently use it sanely since we want to use LBA48 mode. | |
591 | */ | |
4c3032d8 BZ |
592 | io_ports->data_addr = base; |
593 | io_ports->error_addr = base + 1; | |
594 | io_ports->nsect_addr = base + 2; | |
595 | io_ports->lbal_addr = base + 3; | |
596 | io_ports->lbam_addr = base + 4; | |
597 | io_ports->lbah_addr = base + 5; | |
598 | io_ports->device_addr = base + 6; | |
599 | io_ports->status_addr = base + 7; | |
600 | io_ports->ctl_addr = base + 10; | |
1da177e4 LT |
601 | |
602 | if (pdev_is_sata(dev)) { | |
603 | base = (unsigned long)addr; | |
604 | if (ch) | |
605 | base += 0x80; | |
606 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
607 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
608 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
1da177e4 LT |
609 | } |
610 | ||
9239b333 | 611 | hwif->irq = dev->irq; |
1da177e4 | 612 | |
9239b333 | 613 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
1da177e4 LT |
614 | } |
615 | ||
616 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
617 | { | |
7b255436 SS |
618 | const char *s = &drive->id->model[0]; |
619 | unsigned len = strnlen(s, sizeof(drive->id->model)); | |
1da177e4 | 620 | |
7b255436 | 621 | if ((len > 4) && (!memcmp(s, "ST", 2))) |
1da177e4 LT |
622 | if ((!memcmp(s + len - 2, "AS", 2)) || |
623 | (!memcmp(s + len - 3, "ASL", 3))) { | |
624 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
625 | "errata fix\n", drive->name); | |
626 | return 1; | |
627 | } | |
7b255436 | 628 | |
1da177e4 LT |
629 | return 0; |
630 | } | |
631 | ||
632 | /** | |
f01393e4 BZ |
633 | * sil_quirkproc - post probe fixups |
634 | * @drive: drive | |
1da177e4 LT |
635 | * |
636 | * Called after drive probe we use this to decide whether the | |
637 | * Seagate fixup must be applied. This used to be in init_iops but | |
638 | * that can occur before we know what drives are present. | |
639 | */ | |
640 | ||
f01393e4 | 641 | static void __devinit sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 642 | { |
f01393e4 BZ |
643 | ide_hwif_t *hwif = drive->hwif; |
644 | ||
7b255436 | 645 | /* Try and rise the rqsize */ |
f01393e4 | 646 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
647 | hwif->rqsize = 128; |
648 | } | |
649 | ||
650 | /** | |
651 | * init_iops_siimage - set up iops | |
652 | * @hwif: interface to set up | |
653 | * | |
654 | * Do the basic setup for the SIIMAGE hardware interface | |
655 | * and then do the MMIO setup if we can. This is the first | |
656 | * look in we get for setting up the hwif so that we | |
657 | * can get the iops right before using them. | |
658 | */ | |
659 | ||
660 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
661 | { | |
36501650 | 662 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 | 663 | struct ide_host *host = pci_get_drvdata(dev); |
36501650 | 664 | |
1da177e4 LT |
665 | hwif->hwif_data = NULL; |
666 | ||
667 | /* Pessimal until we finish probing */ | |
668 | hwif->rqsize = 15; | |
669 | ||
4c674235 BZ |
670 | if (host->host_priv) |
671 | init_mmio_iops_siimage(hwif); | |
1da177e4 LT |
672 | } |
673 | ||
674 | /** | |
ac95beed | 675 | * sil_cable_detect - cable detection |
1da177e4 LT |
676 | * @hwif: interface to check |
677 | * | |
7b255436 | 678 | * Check for the presence of an ATA66 capable cable on the interface. |
1da177e4 LT |
679 | */ |
680 | ||
ac95beed | 681 | static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 682 | { |
7b255436 SS |
683 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
684 | unsigned long addr = siimage_selreg(hwif, 0); | |
685 | u8 ata66 = sil_ioread8(dev, addr); | |
1da177e4 | 686 | |
49521f97 | 687 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
688 | } |
689 | ||
ac95beed BZ |
690 | static const struct ide_port_ops sil_pata_port_ops = { |
691 | .set_pio_mode = sil_set_pio_mode, | |
692 | .set_dma_mode = sil_set_dma_mode, | |
693 | .quirkproc = sil_quirkproc, | |
694 | .udma_filter = sil_pata_udma_filter, | |
695 | .cable_detect = sil_cable_detect, | |
696 | }; | |
697 | ||
698 | static const struct ide_port_ops sil_sata_port_ops = { | |
699 | .set_pio_mode = sil_set_pio_mode, | |
700 | .set_dma_mode = sil_set_dma_mode, | |
701 | .reset_poll = sil_sata_reset_poll, | |
702 | .pre_reset = sil_sata_pre_reset, | |
703 | .quirkproc = sil_quirkproc, | |
704 | .udma_filter = sil_sata_udma_filter, | |
705 | .cable_detect = sil_cable_detect, | |
706 | }; | |
707 | ||
b26b0c59 BH |
708 | static const struct ide_dma_ops sil_dma_ops = { |
709 | .dma_host_set = ide_dma_host_set, | |
710 | .dma_setup = ide_dma_setup, | |
711 | .dma_exec_cmd = ide_dma_exec_cmd, | |
712 | .dma_start = ide_dma_start, | |
713 | .dma_end = __ide_dma_end, | |
5e37bdc0 | 714 | .dma_test_irq = siimage_dma_test_irq, |
b26b0c59 BH |
715 | .dma_timeout = ide_dma_timeout, |
716 | .dma_lost_irq = ide_dma_lost_irq, | |
5e37bdc0 BZ |
717 | }; |
718 | ||
ac95beed | 719 | #define DECLARE_SII_DEV(name_str, p_ops) \ |
1da177e4 LT |
720 | { \ |
721 | .name = name_str, \ | |
722 | .init_chipset = init_chipset_siimage, \ | |
723 | .init_iops = init_iops_siimage, \ | |
ac95beed | 724 | .port_ops = p_ops, \ |
5e37bdc0 | 725 | .dma_ops = &sil_dma_ops, \ |
4099d143 | 726 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
727 | .mwdma_mask = ATA_MWDMA2, \ |
728 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
729 | } |
730 | ||
85620436 | 731 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
ac95beed BZ |
732 | /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops), |
733 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops), | |
734 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops) | |
1da177e4 LT |
735 | }; |
736 | ||
737 | /** | |
7b255436 | 738 | * siimage_init_one - PCI layer discovery entry |
1da177e4 LT |
739 | * @dev: PCI device |
740 | * @id: ident table entry | |
741 | * | |
7b255436 | 742 | * Called by the PCI code when it finds an SiI680 or SiI3112 controller. |
1da177e4 LT |
743 | * We then use the IDE PCI generic helper to do most of the work. |
744 | */ | |
7b255436 SS |
745 | |
746 | static int __devinit siimage_init_one(struct pci_dev *dev, | |
747 | const struct pci_device_id *id) | |
1da177e4 | 748 | { |
4c674235 BZ |
749 | void __iomem *ioaddr = NULL; |
750 | resource_size_t bar5 = pci_resource_start(dev, 5); | |
751 | unsigned long barsize = pci_resource_len(dev, 5); | |
752 | int rc; | |
5e37bdc0 BZ |
753 | struct ide_port_info d; |
754 | u8 idx = id->driver_data; | |
4c674235 | 755 | u8 BA5_EN; |
5e37bdc0 BZ |
756 | |
757 | d = siimage_chipsets[idx]; | |
758 | ||
759 | if (idx) { | |
760 | static int first = 1; | |
761 | ||
762 | if (first) { | |
763 | printk(KERN_INFO "siimage: For full SATA support you " | |
764 | "should use the libata sata_sil module.\n"); | |
765 | first = 0; | |
766 | } | |
767 | ||
768 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | |
769 | } | |
770 | ||
4c674235 BZ |
771 | rc = pci_enable_device(dev); |
772 | if (rc) | |
773 | return rc; | |
774 | ||
775 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
776 | if ((BA5_EN & 0x01) || bar5) { | |
777 | /* | |
778 | * Drop back to PIO if we can't map the MMIO. Some systems | |
779 | * seem to get terminally confused in the PCI spaces. | |
780 | */ | |
781 | if (!request_mem_region(bar5, barsize, d.name)) { | |
782 | printk(KERN_WARNING "siimage: IDE controller MMIO " | |
783 | "ports not available.\n"); | |
784 | } else { | |
785 | ioaddr = ioremap(bar5, barsize); | |
786 | if (ioaddr == NULL) | |
787 | release_mem_region(bar5, barsize); | |
788 | } | |
789 | } | |
790 | ||
791 | rc = ide_pci_init_one(dev, &d, ioaddr); | |
792 | if (rc) { | |
793 | if (ioaddr) { | |
794 | iounmap(ioaddr); | |
795 | release_mem_region(bar5, barsize); | |
796 | } | |
797 | pci_disable_device(dev); | |
798 | } | |
799 | ||
800 | return rc; | |
1da177e4 LT |
801 | } |
802 | ||
9cbcc5e3 BZ |
803 | static const struct pci_device_id siimage_pci_tbl[] = { |
804 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 805 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
806 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
807 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 }, | |
1da177e4 LT |
808 | #endif |
809 | { 0, }, | |
810 | }; | |
811 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
812 | ||
813 | static struct pci_driver driver = { | |
814 | .name = "SiI_IDE", | |
815 | .id_table = siimage_pci_tbl, | |
816 | .probe = siimage_init_one, | |
817 | }; | |
818 | ||
82ab1eec | 819 | static int __init siimage_ide_init(void) |
1da177e4 LT |
820 | { |
821 | return ide_pci_register_driver(&driver); | |
822 | } | |
823 | ||
824 | module_init(siimage_ide_init); | |
825 | ||
826 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
827 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
828 | MODULE_LICENSE("GPL"); |