Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
328dcbb6 | 2 | * linux/drivers/ide/pci/siimage.c Version 1.15 Jun 29 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 6 | * Copyright (C) 2007 MontaVista Software, Inc. |
328dcbb6 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
bf4c796d JG |
11 | * Documentation for CMD680: |
12 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
13 | * | |
14 | * Documentation for SiI 3112: | |
15 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
16 | * | |
17 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
18 | * |
19 | * | |
20 | * FAQ Items: | |
21 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
22 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
23 | * | |
24 | * If you are using WD drives with SATA bridges you must set the | |
25 | * drive to "Single". "Master" will hang | |
26 | * | |
27 | * If you have strange problems with nVidia chipset systems please | |
28 | * see the SI support documentation and update your system BIOS | |
29 | * if neccessary | |
8693d3e4 AC |
30 | * |
31 | * The Dell DRAC4 has some interesting features including effectively hot | |
32 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
33 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
34 | * smarter code in libata. | |
328dcbb6 BZ |
35 | * |
36 | * TODO: | |
37 | * - IORDY fixes | |
38 | * - VDMA support | |
1da177e4 LT |
39 | */ |
40 | ||
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/module.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/hdreg.h> | |
46 | #include <linux/ide.h> | |
47 | #include <linux/init.h> | |
48 | ||
49 | #include <asm/io.h> | |
50 | ||
1da177e4 LT |
51 | /** |
52 | * pdev_is_sata - check if device is SATA | |
53 | * @pdev: PCI device to check | |
54 | * | |
55 | * Returns true if this is a SATA controller | |
56 | */ | |
57 | ||
58 | static int pdev_is_sata(struct pci_dev *pdev) | |
59 | { | |
60 | switch(pdev->device) | |
61 | { | |
62 | case PCI_DEVICE_ID_SII_3112: | |
63 | case PCI_DEVICE_ID_SII_1210SA: | |
64 | return 1; | |
65 | case PCI_DEVICE_ID_SII_680: | |
66 | return 0; | |
67 | } | |
68 | BUG(); | |
69 | return 0; | |
70 | } | |
71 | ||
72 | /** | |
73 | * is_sata - check if hwif is SATA | |
74 | * @hwif: interface to check | |
75 | * | |
76 | * Returns true if this is a SATA controller | |
77 | */ | |
78 | ||
79 | static inline int is_sata(ide_hwif_t *hwif) | |
80 | { | |
81 | return pdev_is_sata(hwif->pci_dev); | |
82 | } | |
83 | ||
84 | /** | |
85 | * siimage_selreg - return register base | |
86 | * @hwif: interface | |
87 | * @r: config offset | |
88 | * | |
89 | * Turn a config register offset into the right address in either | |
90 | * PCI space or MMIO space to access the control register in question | |
91 | * Thankfully this is a configuration operation so isnt performance | |
92 | * criticial. | |
93 | */ | |
94 | ||
95 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
96 | { | |
97 | unsigned long base = (unsigned long)hwif->hwif_data; | |
98 | base += 0xA0 + r; | |
99 | if(hwif->mmio) | |
100 | base += (hwif->channel << 6); | |
101 | else | |
102 | base += (hwif->channel << 4); | |
103 | return base; | |
104 | } | |
105 | ||
106 | /** | |
107 | * siimage_seldev - return register base | |
108 | * @hwif: interface | |
109 | * @r: config offset | |
110 | * | |
111 | * Turn a config register offset into the right address in either | |
112 | * PCI space or MMIO space to access the control register in question | |
113 | * including accounting for the unit shift. | |
114 | */ | |
115 | ||
116 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
117 | { | |
118 | ide_hwif_t *hwif = HWIF(drive); | |
119 | unsigned long base = (unsigned long)hwif->hwif_data; | |
120 | base += 0xA0 + r; | |
121 | if(hwif->mmio) | |
122 | base += (hwif->channel << 6); | |
123 | else | |
124 | base += (hwif->channel << 4); | |
125 | base |= drive->select.b.unit << drive->select.b.unit; | |
126 | return base; | |
127 | } | |
128 | ||
129 | /** | |
2d5eaa6d BZ |
130 | * sil_udma_filter - compute UDMA mask |
131 | * @drive: IDE device | |
132 | * | |
133 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 134 | * |
1da177e4 | 135 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 136 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 137 | */ |
2d5eaa6d BZ |
138 | |
139 | static u8 sil_udma_filter(ide_drive_t *drive) | |
1da177e4 | 140 | { |
2d5eaa6d | 141 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 142 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 143 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
144 | |
145 | if (hwif->mmio) | |
146 | scsc = hwif->INB(base + 0x4A); | |
147 | else | |
148 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
149 | ||
2d5eaa6d BZ |
150 | if (is_sata(hwif)) { |
151 | mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f; | |
152 | goto out; | |
1da177e4 | 153 | } |
2d5eaa6d | 154 | |
1da177e4 | 155 | if ((scsc & 0x30) == 0x10) /* 133 */ |
2d5eaa6d | 156 | mask = 0x7f; |
1da177e4 | 157 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
2d5eaa6d | 158 | mask = 0x7f; |
1da177e4 | 159 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
2d5eaa6d | 160 | mask = 0x3f; |
1da177e4 LT |
161 | else /* Disabled ? */ |
162 | BUG(); | |
2d5eaa6d BZ |
163 | out: |
164 | return mask; | |
1da177e4 LT |
165 | } |
166 | ||
167 | /** | |
328dcbb6 | 168 | * sil_tune_pio - tune a drive |
1da177e4 | 169 | * @drive: drive to tune |
328dcbb6 | 170 | * @pio: the desired PIO mode |
1da177e4 LT |
171 | * |
172 | * Load the timing settings for this device mode into the | |
173 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
174 | * monitoring (bit 9). The TF timing is bits 31:16 | |
175 | */ | |
328dcbb6 BZ |
176 | |
177 | static void sil_tune_pio(ide_drive_t *drive, u8 pio) | |
1da177e4 | 178 | { |
328dcbb6 BZ |
179 | const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
180 | const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
181 | ||
1da177e4 | 182 | ide_hwif_t *hwif = HWIF(drive); |
328dcbb6 | 183 | ide_drive_t *pair = &hwif->drives[drive->dn ^ 1]; |
1da177e4 LT |
184 | u32 speedt = 0; |
185 | u16 speedp = 0; | |
186 | unsigned long addr = siimage_seldev(drive, 0x04); | |
187 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
328dcbb6 BZ |
188 | u8 tf_pio = pio; |
189 | ||
190 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
191 | if (pair->present) { | |
2134758d | 192 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
193 | |
194 | if (pair_pio < tf_pio) | |
195 | tf_pio = pair_pio; | |
1da177e4 | 196 | } |
075cb655 | 197 | |
328dcbb6 BZ |
198 | /* cheat for now and use the docs */ |
199 | speedp = data_speed[pio]; | |
200 | speedt = tf_speed[tf_pio]; | |
201 | ||
075cb655 SS |
202 | if (hwif->mmio) { |
203 | hwif->OUTW(speedp, addr); | |
204 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 | 205 | /* Now set up IORDY */ |
328dcbb6 | 206 | if (pio > 2) |
1da177e4 LT |
207 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); |
208 | else | |
209 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
075cb655 | 210 | } else { |
1da177e4 LT |
211 | pci_write_config_word(hwif->pci_dev, addr, speedp); |
212 | pci_write_config_word(hwif->pci_dev, tfaddr, speedt); | |
213 | pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp); | |
214 | speedp &= ~0x200; | |
215 | /* Set IORDY for mode 3 or 4 */ | |
328dcbb6 | 216 | if (pio > 2) |
1da177e4 LT |
217 | speedp |= 0x200; |
218 | pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp); | |
219 | } | |
220 | } | |
221 | ||
328dcbb6 | 222 | static void sil_tuneproc(ide_drive_t *drive, u8 pio) |
1da177e4 | 223 | { |
2134758d | 224 | pio = ide_get_best_pio_mode(drive, pio, 4); |
328dcbb6 BZ |
225 | sil_tune_pio(drive, pio); |
226 | (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
227 | } |
228 | ||
1da177e4 LT |
229 | /** |
230 | * siimage_tune_chipset - set controller timings | |
231 | * @drive: Drive to set up | |
f212ff28 | 232 | * @speed: speed we want to achieve |
1da177e4 | 233 | * |
f212ff28 | 234 | * Tune the SII chipset for the desired mode. |
1da177e4 | 235 | */ |
f212ff28 BZ |
236 | |
237 | static int siimage_tune_chipset(ide_drive_t *drive, const u8 speed) | |
1da177e4 LT |
238 | { |
239 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
240 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
241 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
242 | ||
243 | ide_hwif_t *hwif = HWIF(drive); | |
244 | u16 ultra = 0, multi = 0; | |
245 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 LT |
246 | unsigned long base = (unsigned long)hwif->hwif_data; |
247 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
248 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
249 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
250 | ||
251 | unsigned long ma = siimage_seldev(drive, 0x08); | |
252 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
253 | ||
254 | if (hwif->mmio) { | |
255 | scsc = hwif->INB(base + 0x4A); | |
256 | mode = hwif->INB(base + addr_mask); | |
257 | multi = hwif->INW(ma); | |
258 | ultra = hwif->INW(ua); | |
259 | } else { | |
260 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
261 | pci_read_config_byte(hwif->pci_dev, addr_mask, &mode); | |
262 | pci_read_config_word(hwif->pci_dev, ma, &multi); | |
263 | pci_read_config_word(hwif->pci_dev, ua, &ultra); | |
264 | } | |
265 | ||
266 | mode &= ~((unit) ? 0x30 : 0x03); | |
267 | ultra &= ~0x3F; | |
268 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
269 | ||
270 | scsc = is_sata(hwif) ? 1 : scsc; | |
271 | ||
272 | switch(speed) { | |
273 | case XFER_PIO_4: | |
274 | case XFER_PIO_3: | |
275 | case XFER_PIO_2: | |
276 | case XFER_PIO_1: | |
277 | case XFER_PIO_0: | |
328dcbb6 | 278 | sil_tune_pio(drive, speed - XFER_PIO_0); |
1da177e4 LT |
279 | mode |= ((unit) ? 0x10 : 0x01); |
280 | break; | |
281 | case XFER_MW_DMA_2: | |
282 | case XFER_MW_DMA_1: | |
283 | case XFER_MW_DMA_0: | |
284 | multi = dma[speed - XFER_MW_DMA_0]; | |
285 | mode |= ((unit) ? 0x20 : 0x02); | |
1da177e4 LT |
286 | break; |
287 | case XFER_UDMA_6: | |
288 | case XFER_UDMA_5: | |
289 | case XFER_UDMA_4: | |
290 | case XFER_UDMA_3: | |
291 | case XFER_UDMA_2: | |
292 | case XFER_UDMA_1: | |
293 | case XFER_UDMA_0: | |
294 | multi = dma[2]; | |
295 | ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : | |
296 | (ultra5[speed - XFER_UDMA_0])); | |
297 | mode |= ((unit) ? 0x30 : 0x03); | |
1da177e4 LT |
298 | break; |
299 | default: | |
300 | return 1; | |
301 | } | |
302 | ||
303 | if (hwif->mmio) { | |
304 | hwif->OUTB(mode, base + addr_mask); | |
305 | hwif->OUTW(multi, ma); | |
306 | hwif->OUTW(ultra, ua); | |
307 | } else { | |
308 | pci_write_config_byte(hwif->pci_dev, addr_mask, mode); | |
309 | pci_write_config_word(hwif->pci_dev, ma, multi); | |
310 | pci_write_config_word(hwif->pci_dev, ua, ultra); | |
311 | } | |
312 | return (ide_config_drive_speed(drive, speed)); | |
313 | } | |
314 | ||
1da177e4 LT |
315 | /** |
316 | * siimage_configure_drive_for_dma - set up for DMA transfers | |
317 | * @drive: drive we are going to set up | |
318 | * | |
319 | * Set up the drive for DMA, tune the controller and drive as | |
320 | * required. If the drive isn't suitable for DMA or we hit | |
321 | * other problems then we will drop down to PIO and set up | |
322 | * PIO appropriately | |
323 | */ | |
324 | ||
325 | static int siimage_config_drive_for_dma (ide_drive_t *drive) | |
326 | { | |
4728d546 | 327 | if (ide_tune_dma(drive)) |
3608b5d7 | 328 | return 0; |
1da177e4 | 329 | |
d8f4469d | 330 | if (ide_use_fast_pio(drive)) |
328dcbb6 | 331 | sil_tuneproc(drive, 255); |
d8f4469d | 332 | |
3608b5d7 | 333 | return -1; |
1da177e4 LT |
334 | } |
335 | ||
336 | /* returns 1 if dma irq issued, 0 otherwise */ | |
337 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
338 | { | |
339 | ide_hwif_t *hwif = HWIF(drive); | |
340 | u8 dma_altstat = 0; | |
341 | unsigned long addr = siimage_selreg(hwif, 1); | |
342 | ||
343 | /* return 1 if INTR asserted */ | |
344 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
345 | return 1; | |
346 | ||
347 | /* return 1 if Device INTR asserted */ | |
348 | pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat); | |
349 | if (dma_altstat & 8) | |
350 | return 0; //return 1; | |
351 | return 0; | |
352 | } | |
353 | ||
1da177e4 LT |
354 | /** |
355 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
356 | * @drive: drive we are testing | |
357 | * | |
358 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
359 | * SATA status interrupts, if so we clean them up and continue. | |
360 | */ | |
361 | ||
362 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
363 | { | |
364 | ide_hwif_t *hwif = HWIF(drive); | |
365 | unsigned long base = (unsigned long)hwif->hwif_data; | |
366 | unsigned long addr = siimage_selreg(hwif, 0x1); | |
367 | ||
368 | if (SATA_ERROR_REG) { | |
0ecdca26 | 369 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
370 | u8 watchdog = 0; |
371 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
372 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
373 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 374 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
375 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
376 | "watchdog = %d, %s\n", | |
377 | drive->name, sata_error, watchdog, | |
378 | __FUNCTION__); | |
1da177e4 LT |
379 | |
380 | } else { | |
381 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
382 | } | |
383 | ext_stat >>= 16; | |
384 | ||
385 | if (!(ext_stat & 0x0404) && !watchdog) | |
386 | return 0; | |
387 | } | |
388 | ||
389 | /* return 1 if INTR asserted */ | |
0ecdca26 | 390 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
391 | return 1; |
392 | ||
393 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 394 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
395 | return 0; //return 1; |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | /** | |
401 | * siimage_busproc - bus isolation ioctl | |
402 | * @drive: drive to isolate/restore | |
403 | * @state: bus state to set | |
404 | * | |
405 | * Used by the SII3112 to handle bus isolation. As this is a | |
406 | * SATA controller the work required is quite limited, we | |
407 | * just have to clean up the statistics | |
408 | */ | |
409 | ||
410 | static int siimage_busproc (ide_drive_t * drive, int state) | |
411 | { | |
412 | ide_hwif_t *hwif = HWIF(drive); | |
413 | u32 stat_config = 0; | |
414 | unsigned long addr = siimage_selreg(hwif, 0); | |
415 | ||
0ecdca26 BZ |
416 | if (hwif->mmio) |
417 | stat_config = readl((void __iomem *)addr); | |
418 | else | |
1da177e4 LT |
419 | pci_read_config_dword(hwif->pci_dev, addr, &stat_config); |
420 | ||
421 | switch (state) { | |
422 | case BUSSTATE_ON: | |
423 | hwif->drives[0].failures = 0; | |
424 | hwif->drives[1].failures = 0; | |
425 | break; | |
426 | case BUSSTATE_OFF: | |
427 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
428 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
429 | break; | |
430 | case BUSSTATE_TRISTATE: | |
431 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
432 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
433 | break; | |
434 | default: | |
435 | return -EINVAL; | |
436 | } | |
437 | hwif->bus_state = state; | |
438 | return 0; | |
439 | } | |
440 | ||
441 | /** | |
442 | * siimage_reset_poll - wait for sata reset | |
443 | * @drive: drive we are resetting | |
444 | * | |
445 | * Poll the SATA phy and see whether it has come back from the dead | |
446 | * yet. | |
447 | */ | |
448 | ||
449 | static int siimage_reset_poll (ide_drive_t *drive) | |
450 | { | |
451 | if (SATA_STATUS_REG) { | |
452 | ide_hwif_t *hwif = HWIF(drive); | |
453 | ||
0ecdca26 BZ |
454 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
455 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 456 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 457 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
458 | HWGROUP(drive)->polling = 0; |
459 | return ide_started; | |
460 | } | |
461 | return 0; | |
462 | } else { | |
463 | return 0; | |
464 | } | |
465 | } | |
466 | ||
467 | /** | |
468 | * siimage_pre_reset - reset hook | |
469 | * @drive: IDE device being reset | |
470 | * | |
471 | * For the SATA devices we need to handle recalibration/geometry | |
472 | * differently | |
473 | */ | |
474 | ||
475 | static void siimage_pre_reset (ide_drive_t *drive) | |
476 | { | |
477 | if (drive->media != ide_disk) | |
478 | return; | |
479 | ||
480 | if (is_sata(HWIF(drive))) | |
481 | { | |
482 | drive->special.b.set_geometry = 0; | |
483 | drive->special.b.recalibrate = 0; | |
484 | } | |
485 | } | |
486 | ||
487 | /** | |
488 | * siimage_reset - reset a device on an siimage controller | |
489 | * @drive: drive to reset | |
490 | * | |
491 | * Perform a controller level reset fo the device. For | |
492 | * SATA we must also check the PHY. | |
493 | */ | |
494 | ||
495 | static void siimage_reset (ide_drive_t *drive) | |
496 | { | |
497 | ide_hwif_t *hwif = HWIF(drive); | |
498 | u8 reset = 0; | |
499 | unsigned long addr = siimage_selreg(hwif, 0); | |
500 | ||
501 | if (hwif->mmio) { | |
502 | reset = hwif->INB(addr); | |
503 | hwif->OUTB((reset|0x03), addr); | |
504 | /* FIXME:posting */ | |
505 | udelay(25); | |
506 | hwif->OUTB(reset, addr); | |
507 | (void) hwif->INB(addr); | |
508 | } else { | |
509 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
510 | pci_write_config_byte(hwif->pci_dev, addr, reset|0x03); | |
511 | udelay(25); | |
512 | pci_write_config_byte(hwif->pci_dev, addr, reset); | |
513 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
514 | } | |
515 | ||
516 | if (SATA_STATUS_REG) { | |
0ecdca26 BZ |
517 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
518 | u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); | |
1da177e4 LT |
519 | printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", |
520 | hwif->name, sata_stat, __FUNCTION__); | |
521 | if (!(sata_stat)) { | |
522 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", | |
523 | hwif->name, sata_stat); | |
524 | drive->failures++; | |
525 | } | |
526 | } | |
527 | ||
528 | } | |
529 | ||
530 | /** | |
531 | * proc_reports_siimage - add siimage controller to proc | |
532 | * @dev: PCI device | |
533 | * @clocking: SCSC value | |
534 | * @name: controller name | |
535 | * | |
536 | * Report the clocking mode of the controller and add it to | |
537 | * the /proc interface layer | |
538 | */ | |
539 | ||
540 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
541 | { | |
542 | if (!pdev_is_sata(dev)) { | |
543 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
544 | clocking &= 0x03; | |
545 | switch (clocking) { | |
546 | case 0x03: printk("DISABLED!\n"); break; | |
547 | case 0x02: printk("== 2X PCI\n"); break; | |
548 | case 0x01: printk("== 133\n"); break; | |
549 | case 0x00: printk("== 100\n"); break; | |
550 | } | |
551 | } | |
552 | } | |
553 | ||
554 | /** | |
555 | * setup_mmio_siimage - switch an SI controller into MMIO | |
556 | * @dev: PCI device we are configuring | |
557 | * @name: device name | |
558 | * | |
559 | * Attempt to put the device into mmio mode. There are some slight | |
560 | * complications here with certain systems where the mmio bar isnt | |
561 | * mapped so we have to be sure we can fall back to I/O. | |
562 | */ | |
563 | ||
564 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
565 | { | |
566 | unsigned long bar5 = pci_resource_start(dev, 5); | |
567 | unsigned long barsize = pci_resource_len(dev, 5); | |
568 | u8 tmpbyte = 0; | |
569 | void __iomem *ioaddr; | |
d868dd19 | 570 | u32 tmp, irq_mask; |
1da177e4 LT |
571 | |
572 | /* | |
573 | * Drop back to PIO if we can't map the mmio. Some | |
574 | * systems seem to get terminally confused in the PCI | |
575 | * spaces. | |
576 | */ | |
577 | ||
578 | if(!request_mem_region(bar5, barsize, name)) | |
579 | { | |
580 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
581 | return 0; | |
582 | } | |
583 | ||
584 | ioaddr = ioremap(bar5, barsize); | |
585 | ||
586 | if (ioaddr == NULL) | |
587 | { | |
588 | release_mem_region(bar5, barsize); | |
589 | return 0; | |
590 | } | |
591 | ||
592 | pci_set_master(dev); | |
593 | pci_set_drvdata(dev, (void *) ioaddr); | |
594 | ||
595 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
596 | /* make sure IDE0/1 interrupts are not masked */ |
597 | irq_mask = (1 << 22) | (1 << 23); | |
598 | tmp = readl(ioaddr + 0x48); | |
599 | if (tmp & irq_mask) { | |
600 | tmp &= ~irq_mask; | |
601 | writel(tmp, ioaddr + 0x48); | |
602 | readl(ioaddr + 0x48); /* flush */ | |
603 | } | |
1da177e4 LT |
604 | writel(0, ioaddr + 0x148); |
605 | writel(0, ioaddr + 0x1C8); | |
606 | } | |
607 | ||
608 | writeb(0, ioaddr + 0xB4); | |
609 | writeb(0, ioaddr + 0xF4); | |
610 | tmpbyte = readb(ioaddr + 0x4A); | |
611 | ||
612 | switch(tmpbyte & 0x30) { | |
613 | case 0x00: | |
614 | /* In 100 MHz clocking, try and switch to 133 */ | |
615 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
616 | break; | |
617 | case 0x10: | |
618 | /* On 133Mhz clocking */ | |
619 | break; | |
620 | case 0x20: | |
621 | /* On PCIx2 clocking */ | |
622 | break; | |
623 | case 0x30: | |
624 | /* Clocking is disabled */ | |
625 | /* 133 clock attempt to force it on */ | |
626 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
627 | break; | |
628 | } | |
629 | ||
630 | writeb( 0x72, ioaddr + 0xA1); | |
631 | writew( 0x328A, ioaddr + 0xA2); | |
632 | writel(0x62DD62DD, ioaddr + 0xA4); | |
633 | writel(0x43924392, ioaddr + 0xA8); | |
634 | writel(0x40094009, ioaddr + 0xAC); | |
635 | writeb( 0x72, ioaddr + 0xE1); | |
636 | writew( 0x328A, ioaddr + 0xE2); | |
637 | writel(0x62DD62DD, ioaddr + 0xE4); | |
638 | writel(0x43924392, ioaddr + 0xE8); | |
639 | writel(0x40094009, ioaddr + 0xEC); | |
640 | ||
641 | if (pdev_is_sata(dev)) { | |
642 | writel(0xFFFF0000, ioaddr + 0x108); | |
643 | writel(0xFFFF0000, ioaddr + 0x188); | |
644 | writel(0x00680000, ioaddr + 0x148); | |
645 | writel(0x00680000, ioaddr + 0x1C8); | |
646 | } | |
647 | ||
648 | tmpbyte = readb(ioaddr + 0x4A); | |
649 | ||
650 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
651 | return 1; | |
652 | } | |
653 | ||
654 | /** | |
655 | * init_chipset_siimage - set up an SI device | |
656 | * @dev: PCI device | |
657 | * @name: device name | |
658 | * | |
659 | * Perform the initial PCI set up for this device. Attempt to switch | |
660 | * to 133MHz clocking if the system isn't already set up to do it. | |
661 | */ | |
662 | ||
663 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
664 | { | |
665 | u32 class_rev = 0; | |
666 | u8 tmpbyte = 0; | |
667 | u8 BA5_EN = 0; | |
668 | ||
669 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
670 | class_rev &= 0xff; | |
671 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
672 | ||
673 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
674 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
675 | if (setup_mmio_siimage(dev, name)) { | |
676 | return 0; | |
677 | } | |
678 | } | |
679 | ||
680 | pci_write_config_byte(dev, 0x80, 0x00); | |
681 | pci_write_config_byte(dev, 0x84, 0x00); | |
682 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
683 | switch(tmpbyte & 0x30) { | |
684 | case 0x00: | |
685 | /* 133 clock attempt to force it on */ | |
686 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
687 | case 0x30: | |
688 | /* if clocking is disabled */ | |
689 | /* 133 clock attempt to force it on */ | |
690 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
691 | case 0x10: | |
692 | /* 133 already */ | |
693 | break; | |
694 | case 0x20: | |
695 | /* BIOS set PCI x2 clocking */ | |
696 | break; | |
697 | } | |
698 | ||
699 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
700 | ||
701 | pci_write_config_byte(dev, 0xA1, 0x72); | |
702 | pci_write_config_word(dev, 0xA2, 0x328A); | |
703 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
704 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
705 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
706 | pci_write_config_byte(dev, 0xB1, 0x72); | |
707 | pci_write_config_word(dev, 0xB2, 0x328A); | |
708 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
709 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
710 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
711 | ||
712 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
713 | return 0; | |
714 | } | |
715 | ||
716 | /** | |
717 | * init_mmio_iops_siimage - set up the iops for MMIO | |
718 | * @hwif: interface to set up | |
719 | * | |
720 | * The basic setup here is fairly simple, we can use standard MMIO | |
721 | * operations. However we do have to set the taskfile register offsets | |
722 | * by hand as there isnt a standard defined layout for them this | |
723 | * time. | |
724 | * | |
725 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 726 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
727 | */ |
728 | ||
729 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
730 | { | |
731 | struct pci_dev *dev = hwif->pci_dev; | |
732 | void *addr = pci_get_drvdata(dev); | |
733 | u8 ch = hwif->channel; | |
734 | hw_regs_t hw; | |
735 | unsigned long base; | |
736 | ||
737 | /* | |
738 | * Fill in the basic HWIF bits | |
739 | */ | |
740 | ||
741 | default_hwif_mmiops(hwif); | |
742 | hwif->hwif_data = addr; | |
743 | ||
744 | /* | |
745 | * Now set up the hw. We have to do this ourselves as | |
59c51591 | 746 | * the MMIO layout isnt the same as the standard port |
1da177e4 LT |
747 | * based I/O |
748 | */ | |
749 | ||
750 | memset(&hw, 0, sizeof(hw_regs_t)); | |
751 | ||
752 | base = (unsigned long)addr; | |
753 | if (ch) | |
754 | base += 0xC0; | |
755 | else | |
756 | base += 0x80; | |
757 | ||
758 | /* | |
759 | * The buffered task file doesn't have status/control | |
760 | * so we can't currently use it sanely since we want to | |
761 | * use LBA48 mode. | |
762 | */ | |
1da177e4 LT |
763 | hw.io_ports[IDE_DATA_OFFSET] = base; |
764 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
765 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
766 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
767 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
768 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
769 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
770 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
771 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
772 | ||
773 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
774 | ||
775 | if (pdev_is_sata(dev)) { | |
776 | base = (unsigned long)addr; | |
777 | if (ch) | |
778 | base += 0x80; | |
779 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
780 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
781 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
782 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
783 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
784 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
785 | } | |
786 | ||
787 | hw.irq = hwif->pci_dev->irq; | |
788 | ||
789 | memcpy(&hwif->hw, &hw, sizeof(hw)); | |
790 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports)); | |
791 | ||
792 | hwif->irq = hw.irq; | |
793 | ||
794 | base = (unsigned long) addr; | |
795 | ||
1da177e4 | 796 | hwif->dma_base = base + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
797 | |
798 | hwif->mmio = 1; | |
1da177e4 LT |
799 | } |
800 | ||
801 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
802 | { | |
803 | const char *s = &drive->id->model[0]; | |
804 | unsigned len; | |
805 | ||
806 | if (!drive->present) | |
807 | return 0; | |
808 | ||
809 | len = strnlen(s, sizeof(drive->id->model)); | |
810 | ||
811 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
812 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
813 | (!memcmp(s + len - 3, "ASL", 3))) { | |
814 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
815 | "errata fix\n", drive->name); | |
816 | return 1; | |
817 | } | |
818 | } | |
819 | return 0; | |
820 | } | |
821 | ||
822 | /** | |
823 | * siimage_fixup - post probe fixups | |
824 | * @hwif: interface to fix up | |
825 | * | |
826 | * Called after drive probe we use this to decide whether the | |
827 | * Seagate fixup must be applied. This used to be in init_iops but | |
828 | * that can occur before we know what drives are present. | |
829 | */ | |
830 | ||
831 | static void __devinit siimage_fixup(ide_hwif_t *hwif) | |
832 | { | |
833 | /* Try and raise the rqsize */ | |
834 | if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0])) | |
835 | hwif->rqsize = 128; | |
836 | } | |
837 | ||
838 | /** | |
839 | * init_iops_siimage - set up iops | |
840 | * @hwif: interface to set up | |
841 | * | |
842 | * Do the basic setup for the SIIMAGE hardware interface | |
843 | * and then do the MMIO setup if we can. This is the first | |
844 | * look in we get for setting up the hwif so that we | |
845 | * can get the iops right before using them. | |
846 | */ | |
847 | ||
848 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
849 | { | |
850 | struct pci_dev *dev = hwif->pci_dev; | |
851 | u32 class_rev = 0; | |
852 | ||
853 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
854 | class_rev &= 0xff; | |
855 | ||
856 | hwif->hwif_data = NULL; | |
857 | ||
858 | /* Pessimal until we finish probing */ | |
859 | hwif->rqsize = 15; | |
860 | ||
861 | if (pci_get_drvdata(dev) == NULL) | |
862 | return; | |
863 | init_mmio_iops_siimage(hwif); | |
864 | } | |
865 | ||
866 | /** | |
867 | * ata66_siimage - check for 80 pin cable | |
868 | * @hwif: interface to check | |
869 | * | |
870 | * Check for the presence of an ATA66 capable cable on the | |
871 | * interface. | |
872 | */ | |
873 | ||
49521f97 | 874 | static u8 __devinit ata66_siimage(ide_hwif_t *hwif) |
1da177e4 LT |
875 | { |
876 | unsigned long addr = siimage_selreg(hwif, 0); | |
49521f97 BZ |
877 | u8 ata66 = 0; |
878 | ||
879 | if (pci_get_drvdata(hwif->pci_dev) == NULL) | |
1da177e4 | 880 | pci_read_config_byte(hwif->pci_dev, addr, &ata66); |
49521f97 BZ |
881 | else |
882 | ata66 = hwif->INB(addr); | |
1da177e4 | 883 | |
49521f97 | 884 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
885 | } |
886 | ||
887 | /** | |
888 | * init_hwif_siimage - set up hwif structs | |
889 | * @hwif: interface to set up | |
890 | * | |
891 | * We do the basic set up of the interface structure. The SIIMAGE | |
892 | * requires several custom handlers so we override the default | |
893 | * ide DMA handlers appropriately | |
894 | */ | |
895 | ||
896 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
897 | { | |
898 | hwif->autodma = 0; | |
899 | ||
900 | hwif->resetproc = &siimage_reset; | |
901 | hwif->speedproc = &siimage_tune_chipset; | |
328dcbb6 | 902 | hwif->tuneproc = &sil_tuneproc; |
1da177e4 LT |
903 | hwif->reset_poll = &siimage_reset_poll; |
904 | hwif->pre_reset = &siimage_pre_reset; | |
2d5eaa6d | 905 | hwif->udma_filter = &sil_udma_filter; |
1da177e4 | 906 | |
19c1ef5f AC |
907 | if(is_sata(hwif)) { |
908 | static int first = 1; | |
909 | ||
1da177e4 LT |
910 | hwif->busproc = &siimage_busproc; |
911 | ||
19c1ef5f AC |
912 | if (first) { |
913 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
914 | first = 0; | |
915 | } | |
916 | } | |
328dcbb6 BZ |
917 | |
918 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; | |
919 | ||
920 | if (hwif->dma_base == 0) | |
1da177e4 | 921 | return; |
1da177e4 LT |
922 | |
923 | hwif->ultra_mask = 0x7f; | |
924 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
925 | |
926 | if (!is_sata(hwif)) | |
927 | hwif->atapi_dma = 1; | |
928 | ||
929 | hwif->ide_dma_check = &siimage_config_drive_for_dma; | |
49521f97 BZ |
930 | |
931 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) | |
932 | hwif->cbl = ata66_siimage(hwif); | |
1da177e4 LT |
933 | |
934 | if (hwif->mmio) { | |
935 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
936 | } else { | |
937 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
938 | } | |
939 | ||
940 | /* | |
941 | * The BIOS often doesn't set up DMA on this controller | |
942 | * so we always do it. | |
943 | */ | |
944 | ||
945 | hwif->autodma = 1; | |
946 | hwif->drives[0].autodma = hwif->autodma; | |
947 | hwif->drives[1].autodma = hwif->autodma; | |
948 | } | |
949 | ||
950 | #define DECLARE_SII_DEV(name_str) \ | |
951 | { \ | |
952 | .name = name_str, \ | |
953 | .init_chipset = init_chipset_siimage, \ | |
954 | .init_iops = init_iops_siimage, \ | |
955 | .init_hwif = init_hwif_siimage, \ | |
956 | .fixup = siimage_fixup, \ | |
1da177e4 LT |
957 | .autodma = AUTODMA, \ |
958 | .bootable = ON_BOARD, \ | |
4099d143 | 959 | .pio_mask = ATA_PIO4, \ |
1da177e4 LT |
960 | } |
961 | ||
962 | static ide_pci_device_t siimage_chipsets[] __devinitdata = { | |
963 | /* 0 */ DECLARE_SII_DEV("SiI680"), | |
964 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
965 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
966 | }; | |
967 | ||
968 | /** | |
969 | * siimage_init_one - pci layer discovery entry | |
970 | * @dev: PCI device | |
971 | * @id: ident table entry | |
972 | * | |
973 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
974 | * We then use the IDE PCI generic helper to do most of the work. | |
975 | */ | |
976 | ||
977 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
978 | { | |
979 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
980 | } | |
981 | ||
982 | static struct pci_device_id siimage_pci_tbl[] = { | |
28a2a3f5 | 983 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 | 984 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
28a2a3f5 AC |
985 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
986 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
1da177e4 LT |
987 | #endif |
988 | { 0, }, | |
989 | }; | |
990 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
991 | ||
992 | static struct pci_driver driver = { | |
993 | .name = "SiI_IDE", | |
994 | .id_table = siimage_pci_tbl, | |
995 | .probe = siimage_init_one, | |
996 | }; | |
997 | ||
82ab1eec | 998 | static int __init siimage_ide_init(void) |
1da177e4 LT |
999 | { |
1000 | return ide_pci_register_driver(&driver); | |
1001 | } | |
1002 | ||
1003 | module_init(siimage_ide_init); | |
1004 | ||
1005 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
1006 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
1007 | MODULE_LICENSE("GPL"); |