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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003 | |
3 | * | |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
6 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
9 | * | |
10 | * Thanks : | |
11 | * | |
12 | * SiS Taiwan : for direct support and hardware. | |
13 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
14 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
15 | * for checking code correctness, providing patches. | |
16 | * | |
17 | * | |
18 | * Original tests and design on the SiS620 chipset. | |
19 | * ATA100 tests and design on the SiS735 chipset. | |
20 | * ATA16/33 support from specs | |
21 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
22 | * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz> | |
23 | * | |
24 | * Documentation: | |
25 | * SiS chipset documentation available under NDA to companies only | |
26 | * (not to individuals). | |
27 | */ | |
28 | ||
29 | /* | |
30 | * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original | |
31 | * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511 | |
32 | * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip. | |
33 | * | |
34 | * Later SiS chipsets integrated the 5513 functionality into the NorthBridge, | |
35 | * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We | |
36 | * can figure out that we have a more modern and more capable 5513 by looking | |
37 | * for the respective NorthBridge IDs. | |
38 | * | |
39 | * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513 | |
40 | * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI | |
41 | * ID, while the now ATA-133 capable 5513 still has the same PCI ID. | |
42 | * Fortunately the 5513 can be 'unmasked' by fiddling with some config space | |
43 | * bits, changing its device id to the true one - 5517 for 961 and 5518 for | |
44 | * 962/963. | |
45 | */ | |
46 | ||
47 | #include <linux/config.h> | |
48 | #include <linux/types.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/kernel.h> | |
51 | #include <linux/delay.h> | |
52 | #include <linux/timer.h> | |
53 | #include <linux/mm.h> | |
54 | #include <linux/ioport.h> | |
55 | #include <linux/blkdev.h> | |
56 | #include <linux/hdreg.h> | |
57 | ||
58 | #include <linux/interrupt.h> | |
59 | #include <linux/pci.h> | |
60 | #include <linux/init.h> | |
61 | #include <linux/ide.h> | |
62 | ||
63 | #include <asm/irq.h> | |
64 | ||
65 | #include "ide-timing.h" | |
66 | ||
67 | #define DISPLAY_SIS_TIMINGS | |
68 | ||
69 | /* registers layout and init values are chipset family dependant */ | |
70 | ||
71 | #define ATA_16 0x01 | |
72 | #define ATA_33 0x02 | |
73 | #define ATA_66 0x03 | |
74 | #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout | |
75 | #define ATA_100 0x05 | |
76 | #define ATA_133a 0x06 // SiS961b with 133 support | |
77 | #define ATA_133 0x07 // SiS962/963 | |
78 | ||
79 | static u8 chipset_family; | |
80 | ||
81 | /* | |
82 | * Devices supported | |
83 | */ | |
84 | static const struct { | |
85 | const char *name; | |
86 | u16 host_id; | |
87 | u8 chipset_family; | |
88 | u8 flags; | |
89 | } SiSHostChipInfo[] = { | |
90 | { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 }, | |
91 | { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 }, | |
92 | { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 }, | |
93 | { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 }, | |
94 | { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 }, | |
95 | ||
96 | { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a }, | |
97 | { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a }, | |
98 | ||
99 | { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 }, | |
100 | { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 }, | |
101 | { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 }, | |
102 | { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 }, | |
103 | { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 }, | |
104 | ||
105 | { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 }, | |
106 | { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 }, | |
107 | { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 }, | |
108 | { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 }, | |
109 | { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 }, | |
110 | { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 }, | |
111 | ||
112 | { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 }, | |
113 | { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 }, | |
114 | { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 }, | |
115 | }; | |
116 | ||
117 | /* Cycle time bits and values vary across chip dma capabilities | |
118 | These three arrays hold the register layout and the values to set. | |
119 | Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ | |
120 | ||
121 | /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ | |
122 | static u8 cycle_time_offset[] = {0,0,5,4,4,0,0}; | |
123 | static u8 cycle_time_range[] = {0,0,2,3,3,4,4}; | |
124 | static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
125 | {0,0,0,0,0,0,0}, /* no udma */ | |
126 | {0,0,0,0,0,0,0}, /* no udma */ | |
127 | {3,2,1,0,0,0,0}, /* ATA_33 */ | |
128 | {7,5,3,2,1,0,0}, /* ATA_66 */ | |
129 | {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */ | |
130 | {11,7,5,4,2,1,0}, /* ATA_100 */ | |
131 | {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */ | |
132 | {15,10,7,5,3,2,1}, /* ATA_133 */ | |
133 | }; | |
134 | /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 | |
135 | See SiS962 data sheet for more detail */ | |
136 | static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
137 | {0,0,0,0,0,0,0}, /* no udma */ | |
138 | {0,0,0,0,0,0,0}, /* no udma */ | |
139 | {2,1,1,0,0,0,0}, | |
140 | {4,3,2,1,0,0,0}, | |
141 | {4,3,2,1,0,0,0}, | |
142 | {6,4,3,1,1,1,0}, | |
143 | {9,6,4,2,2,2,2}, | |
144 | {9,6,4,2,2,2,2}, | |
145 | }; | |
146 | /* Initialize time, Active time, Recovery time vary across | |
147 | IDE clock settings. These 3 arrays hold the register value | |
148 | for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ | |
149 | static u8 ini_time_value[][8] = { | |
150 | {0,0,0,0,0,0,0,0}, | |
151 | {0,0,0,0,0,0,0,0}, | |
152 | {2,1,0,0,0,1,0,0}, | |
153 | {4,3,1,1,1,3,1,1}, | |
154 | {4,3,1,1,1,3,1,1}, | |
155 | {6,4,2,2,2,4,2,2}, | |
156 | {9,6,3,3,3,6,3,3}, | |
157 | {9,6,3,3,3,6,3,3}, | |
158 | }; | |
159 | static u8 act_time_value[][8] = { | |
160 | {0,0,0,0,0,0,0,0}, | |
161 | {0,0,0,0,0,0,0,0}, | |
162 | {9,9,9,2,2,7,2,2}, | |
163 | {19,19,19,5,4,14,5,4}, | |
164 | {19,19,19,5,4,14,5,4}, | |
165 | {28,28,28,7,6,21,7,6}, | |
166 | {38,38,38,10,9,28,10,9}, | |
167 | {38,38,38,10,9,28,10,9}, | |
168 | }; | |
169 | static u8 rco_time_value[][8] = { | |
170 | {0,0,0,0,0,0,0,0}, | |
171 | {0,0,0,0,0,0,0,0}, | |
172 | {9,2,0,2,0,7,1,1}, | |
173 | {19,5,1,5,2,16,3,2}, | |
174 | {19,5,1,5,2,16,3,2}, | |
175 | {30,9,3,9,4,25,6,4}, | |
176 | {40,12,4,12,5,34,12,5}, | |
177 | {40,12,4,12,5,34,12,5}, | |
178 | }; | |
179 | ||
180 | /* | |
181 | * Printing configuration | |
182 | */ | |
183 | /* Used for chipset type printing at boot time */ | |
184 | static char* chipset_capability[] = { | |
185 | "ATA", "ATA 16", | |
186 | "ATA 33", "ATA 66", | |
187 | "ATA 100 (1st gen)", "ATA 100 (2nd gen)", | |
188 | "ATA 133 (1st gen)", "ATA 133 (2nd gen)" | |
189 | }; | |
190 | ||
191 | #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) | |
192 | #include <linux/stat.h> | |
193 | #include <linux/proc_fs.h> | |
194 | ||
195 | static u8 sis_proc = 0; | |
196 | ||
197 | static struct pci_dev *bmide_dev; | |
198 | ||
199 | static char* cable_type[] = { | |
200 | "80 pins", | |
201 | "40 pins" | |
202 | }; | |
203 | ||
204 | static char* recovery_time[] ={ | |
205 | "12 PCICLK", "1 PCICLK", | |
206 | "2 PCICLK", "3 PCICLK", | |
207 | "4 PCICLK", "5 PCICLCK", | |
208 | "6 PCICLK", "7 PCICLCK", | |
209 | "8 PCICLK", "9 PCICLCK", | |
210 | "10 PCICLK", "11 PCICLK", | |
211 | "13 PCICLK", "14 PCICLK", | |
212 | "15 PCICLK", "15 PCICLK" | |
213 | }; | |
214 | ||
215 | static char* active_time[] = { | |
216 | "8 PCICLK", "1 PCICLCK", | |
217 | "2 PCICLK", "3 PCICLK", | |
218 | "4 PCICLK", "5 PCICLK", | |
219 | "6 PCICLK", "12 PCICLK" | |
220 | }; | |
221 | ||
222 | static char* cycle_time[] = { | |
223 | "Reserved", "2 CLK", | |
224 | "3 CLK", "4 CLK", | |
225 | "5 CLK", "6 CLK", | |
226 | "7 CLK", "8 CLK", | |
227 | "9 CLK", "10 CLK", | |
228 | "11 CLK", "12 CLK", | |
229 | "13 CLK", "14 CLK", | |
230 | "15 CLK", "16 CLK" | |
231 | }; | |
232 | ||
233 | /* Generic add master or slave info function */ | |
234 | static char* get_drives_info (char *buffer, u8 pos) | |
235 | { | |
236 | u8 reg00, reg01, reg10, reg11; /* timing registers */ | |
237 | u32 regdw0, regdw1; | |
238 | char* p = buffer; | |
239 | ||
240 | /* Postwrite/Prefetch */ | |
241 | if (chipset_family < ATA_133) { | |
242 | pci_read_config_byte(bmide_dev, 0x4b, ®00); | |
243 | p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n", | |
244 | pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled", | |
245 | (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled"); | |
246 | p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n", | |
247 | (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled", | |
248 | (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled"); | |
249 | pci_read_config_byte(bmide_dev, 0x40+2*pos, ®00); | |
250 | pci_read_config_byte(bmide_dev, 0x41+2*pos, ®01); | |
251 | pci_read_config_byte(bmide_dev, 0x44+2*pos, ®10); | |
252 | pci_read_config_byte(bmide_dev, 0x45+2*pos, ®11); | |
253 | } else { | |
254 | u32 reg54h; | |
255 | u8 drive_pci = 0x40; | |
256 | pci_read_config_dword(bmide_dev, 0x54, ®54h); | |
257 | if (reg54h & 0x40000000) { | |
258 | // Configuration space remapped to 0x70 | |
259 | drive_pci = 0x70; | |
260 | } | |
261 | pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, ®dw0); | |
262 | pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, ®dw1); | |
263 | ||
264 | p += sprintf(p, "Drive %d:\n", pos); | |
265 | } | |
266 | ||
267 | ||
268 | /* UDMA */ | |
269 | if (chipset_family >= ATA_133) { | |
270 | p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n", | |
271 | (regdw0 & 0x04) ? "Enabled" : "Disabled", | |
272 | (regdw1 & 0x04) ? "Enabled" : "Disabled"); | |
273 | p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n", | |
274 | cycle_time[(regdw0 & 0xF0) >> 4], | |
275 | cycle_time[(regdw1 & 0xF0) >> 4]); | |
276 | } else if (chipset_family >= ATA_33) { | |
277 | p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n", | |
278 | (reg01 & 0x80) ? "Enabled" : "Disabled", | |
279 | (reg11 & 0x80) ? "Enabled" : "Disabled"); | |
280 | ||
281 | p += sprintf(p, " UDMA Cycle Time "); | |
282 | switch(chipset_family) { | |
283 | case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break; | |
284 | case ATA_66: | |
285 | case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break; | |
286 | case ATA_100: | |
287 | case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break; | |
288 | default: p += sprintf(p, "?"); break; | |
289 | } | |
290 | p += sprintf(p, " \t UDMA Cycle Time "); | |
291 | switch(chipset_family) { | |
292 | case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break; | |
293 | case ATA_66: | |
294 | case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break; | |
295 | case ATA_100: | |
296 | case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break; | |
297 | default: p += sprintf(p, "?"); break; | |
298 | } | |
299 | p += sprintf(p, "\n"); | |
300 | } | |
301 | ||
302 | ||
303 | if (chipset_family < ATA_133) { /* else case TODO */ | |
304 | ||
305 | /* Data Active */ | |
306 | p += sprintf(p, " Data Active Time "); | |
307 | switch(chipset_family) { | |
308 | case ATA_16: /* confirmed */ | |
309 | case ATA_33: | |
310 | case ATA_66: | |
311 | case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break; | |
312 | case ATA_100: | |
313 | case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break; | |
314 | default: p += sprintf(p, "?"); break; | |
315 | } | |
316 | p += sprintf(p, " \t Data Active Time "); | |
317 | switch(chipset_family) { | |
318 | case ATA_16: | |
319 | case ATA_33: | |
320 | case ATA_66: | |
321 | case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break; | |
322 | case ATA_100: | |
323 | case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break; | |
324 | default: p += sprintf(p, "?"); break; | |
325 | } | |
326 | p += sprintf(p, "\n"); | |
327 | ||
328 | /* Data Recovery */ | |
329 | /* warning: may need (reg&0x07) for pre ATA66 chips */ | |
330 | p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n", | |
331 | recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]); | |
332 | } | |
333 | ||
334 | return p; | |
335 | } | |
336 | ||
337 | static char* get_masters_info(char* buffer) | |
338 | { | |
339 | return get_drives_info(buffer, 0); | |
340 | } | |
341 | ||
342 | static char* get_slaves_info(char* buffer) | |
343 | { | |
344 | return get_drives_info(buffer, 1); | |
345 | } | |
346 | ||
347 | /* Main get_info, called on /proc/ide/sis reads */ | |
348 | static int sis_get_info (char *buffer, char **addr, off_t offset, int count) | |
349 | { | |
350 | char *p = buffer; | |
351 | int len; | |
352 | u8 reg; | |
353 | u16 reg2, reg3; | |
354 | ||
355 | p += sprintf(p, "\nSiS 5513 "); | |
356 | switch(chipset_family) { | |
357 | case ATA_16: p += sprintf(p, "DMA 16"); break; | |
358 | case ATA_33: p += sprintf(p, "Ultra 33"); break; | |
359 | case ATA_66: p += sprintf(p, "Ultra 66"); break; | |
360 | case ATA_100a: | |
361 | case ATA_100: p += sprintf(p, "Ultra 100"); break; | |
362 | case ATA_133a: | |
363 | case ATA_133: p += sprintf(p, "Ultra 133"); break; | |
364 | default: p+= sprintf(p, "Unknown???"); break; | |
365 | } | |
366 | p += sprintf(p, " chipset\n"); | |
367 | p += sprintf(p, "--------------- Primary Channel " | |
368 | "---------------- Secondary Channel " | |
369 | "-------------\n"); | |
370 | ||
371 | /* Status */ | |
372 | pci_read_config_byte(bmide_dev, 0x4a, ®); | |
373 | if (chipset_family == ATA_133) { | |
374 | pci_read_config_word(bmide_dev, 0x50, ®2); | |
375 | pci_read_config_word(bmide_dev, 0x52, ®3); | |
376 | } | |
377 | p += sprintf(p, "Channel Status: "); | |
378 | if (chipset_family < ATA_66) { | |
379 | p += sprintf(p, "%s \t \t \t \t %s\n", | |
380 | (reg & 0x04) ? "On" : "Off", | |
381 | (reg & 0x02) ? "On" : "Off"); | |
382 | } else if (chipset_family < ATA_133) { | |
383 | p += sprintf(p, "%s \t \t \t \t %s \n", | |
384 | (reg & 0x02) ? "On" : "Off", | |
385 | (reg & 0x04) ? "On" : "Off"); | |
386 | } else { /* ATA_133 */ | |
387 | p += sprintf(p, "%s \t \t \t \t %s \n", | |
388 | (reg2 & 0x02) ? "On" : "Off", | |
389 | (reg3 & 0x02) ? "On" : "Off"); | |
390 | } | |
391 | ||
392 | /* Operation Mode */ | |
393 | pci_read_config_byte(bmide_dev, 0x09, ®); | |
394 | p += sprintf(p, "Operation Mode: %s \t \t \t %s \n", | |
395 | (reg & 0x01) ? "Native" : "Compatible", | |
396 | (reg & 0x04) ? "Native" : "Compatible"); | |
397 | ||
398 | /* 80-pin cable ? */ | |
399 | if (chipset_family >= ATA_133) { | |
400 | p += sprintf(p, "Cable Type: %s \t \t \t %s\n", | |
401 | (reg2 & 0x01) ? cable_type[1] : cable_type[0], | |
402 | (reg3 & 0x01) ? cable_type[1] : cable_type[0]); | |
403 | } else if (chipset_family > ATA_33) { | |
404 | pci_read_config_byte(bmide_dev, 0x48, ®); | |
405 | p += sprintf(p, "Cable Type: %s \t \t \t %s\n", | |
406 | (reg & 0x10) ? cable_type[1] : cable_type[0], | |
407 | (reg & 0x20) ? cable_type[1] : cable_type[0]); | |
408 | } | |
409 | ||
410 | /* Prefetch Count */ | |
411 | if (chipset_family < ATA_133) { | |
412 | pci_read_config_word(bmide_dev, 0x4c, ®2); | |
413 | pci_read_config_word(bmide_dev, 0x4e, ®3); | |
414 | p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n", | |
415 | reg2, reg3); | |
416 | } | |
417 | ||
418 | p = get_masters_info(p); | |
419 | p = get_slaves_info(p); | |
420 | ||
421 | len = (p - buffer) - offset; | |
422 | *addr = buffer + offset; | |
423 | ||
424 | return len > count ? count : len; | |
425 | } | |
426 | #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */ | |
427 | ||
428 | static u8 sis5513_ratemask (ide_drive_t *drive) | |
429 | { | |
430 | u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 }; | |
431 | u8 mode = rates[chipset_family]; | |
432 | ||
433 | if (!eighty_ninty_three(drive)) | |
434 | mode = min(mode, (u8)1); | |
435 | return mode; | |
436 | } | |
437 | ||
438 | /* | |
439 | * Configuration functions | |
440 | */ | |
441 | /* Enables per-drive prefetch and postwrite */ | |
442 | static void config_drive_art_rwp (ide_drive_t *drive) | |
443 | { | |
444 | ide_hwif_t *hwif = HWIF(drive); | |
445 | struct pci_dev *dev = hwif->pci_dev; | |
446 | ||
447 | u8 reg4bh = 0; | |
448 | u8 rw_prefetch = (0x11 << drive->dn); | |
449 | ||
450 | if (drive->media != ide_disk) | |
451 | return; | |
452 | pci_read_config_byte(dev, 0x4b, ®4bh); | |
453 | ||
454 | if ((reg4bh & rw_prefetch) != rw_prefetch) | |
455 | pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch); | |
456 | } | |
457 | ||
458 | ||
459 | /* Set per-drive active and recovery time */ | |
460 | static void config_art_rwp_pio (ide_drive_t *drive, u8 pio) | |
461 | { | |
462 | ide_hwif_t *hwif = HWIF(drive); | |
463 | struct pci_dev *dev = hwif->pci_dev; | |
464 | ||
465 | u8 timing, drive_pci, test1, test2; | |
466 | ||
467 | u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90}; | |
468 | u16 xfer_pio = drive->id->eide_pio_modes; | |
469 | ||
470 | config_drive_art_rwp(drive); | |
471 | pio = ide_get_best_pio_mode(drive, 255, pio, NULL); | |
472 | ||
473 | if (xfer_pio> 4) | |
474 | xfer_pio = 0; | |
475 | ||
476 | if (drive->id->eide_pio_iordy > 0) { | |
477 | for (xfer_pio = 5; | |
478 | (xfer_pio > 0) && | |
479 | (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]); | |
480 | xfer_pio--); | |
481 | } else { | |
482 | xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 : | |
483 | (drive->id->eide_pio_modes & 2) ? 0x04 : | |
484 | (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio; | |
485 | } | |
486 | ||
487 | timing = (xfer_pio >= pio) ? xfer_pio : pio; | |
488 | ||
489 | /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */ | |
490 | drive_pci = 0x40; | |
491 | /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */ | |
492 | if (chipset_family >= ATA_133) { | |
493 | u32 reg54h; | |
494 | pci_read_config_dword(dev, 0x54, ®54h); | |
495 | if (reg54h & 0x40000000) drive_pci = 0x70; | |
496 | drive_pci += ((drive->dn)*0x4); | |
497 | } else { | |
498 | drive_pci += ((drive->dn)*0x2); | |
499 | } | |
500 | ||
501 | /* register layout changed with newer ATA100 chips */ | |
502 | if (chipset_family < ATA_100) { | |
503 | pci_read_config_byte(dev, drive_pci, &test1); | |
504 | pci_read_config_byte(dev, drive_pci+1, &test2); | |
505 | ||
506 | /* Clear active and recovery timings */ | |
507 | test1 &= ~0x0F; | |
508 | test2 &= ~0x07; | |
509 | ||
510 | switch(timing) { | |
511 | case 4: test1 |= 0x01; test2 |= 0x03; break; | |
512 | case 3: test1 |= 0x03; test2 |= 0x03; break; | |
513 | case 2: test1 |= 0x04; test2 |= 0x04; break; | |
514 | case 1: test1 |= 0x07; test2 |= 0x06; break; | |
515 | default: break; | |
516 | } | |
517 | pci_write_config_byte(dev, drive_pci, test1); | |
518 | pci_write_config_byte(dev, drive_pci+1, test2); | |
519 | } else if (chipset_family < ATA_133) { | |
520 | switch(timing) { /* active recovery | |
521 | v v */ | |
522 | case 4: test1 = 0x30|0x01; break; | |
523 | case 3: test1 = 0x30|0x03; break; | |
524 | case 2: test1 = 0x40|0x04; break; | |
525 | case 1: test1 = 0x60|0x07; break; | |
526 | default: break; | |
527 | } | |
528 | pci_write_config_byte(dev, drive_pci, test1); | |
529 | } else { /* ATA_133 */ | |
530 | u32 test3; | |
531 | pci_read_config_dword(dev, drive_pci, &test3); | |
532 | test3 &= 0xc0c00fff; | |
533 | if (test3 & 0x08) { | |
534 | test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12; | |
535 | test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16; | |
536 | test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24; | |
537 | } else { | |
538 | test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12; | |
539 | test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16; | |
540 | test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24; | |
541 | } | |
542 | pci_write_config_dword(dev, drive_pci, test3); | |
543 | } | |
544 | } | |
545 | ||
546 | static int config_chipset_for_pio (ide_drive_t *drive, u8 pio) | |
547 | { | |
548 | if (pio == 255) | |
549 | pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0; | |
550 | config_art_rwp_pio(drive, pio); | |
551 | return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4)); | |
552 | } | |
553 | ||
554 | static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
555 | { | |
556 | ide_hwif_t *hwif = HWIF(drive); | |
557 | struct pci_dev *dev = hwif->pci_dev; | |
558 | ||
559 | u8 drive_pci, reg, speed; | |
560 | u32 regdw; | |
561 | ||
562 | speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed); | |
563 | ||
564 | /* See config_art_rwp_pio for drive pci config registers */ | |
565 | drive_pci = 0x40; | |
566 | if (chipset_family >= ATA_133) { | |
567 | u32 reg54h; | |
568 | pci_read_config_dword(dev, 0x54, ®54h); | |
569 | if (reg54h & 0x40000000) drive_pci = 0x70; | |
570 | drive_pci += ((drive->dn)*0x4); | |
571 | pci_read_config_dword(dev, (unsigned long)drive_pci, ®dw); | |
572 | /* Disable UDMA bit for non UDMA modes on UDMA chips */ | |
573 | if (speed < XFER_UDMA_0) { | |
574 | regdw &= 0xfffffffb; | |
575 | pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); | |
576 | } | |
577 | ||
578 | } else { | |
579 | drive_pci += ((drive->dn)*0x2); | |
580 | pci_read_config_byte(dev, drive_pci+1, ®); | |
581 | /* Disable UDMA bit for non UDMA modes on UDMA chips */ | |
582 | if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) { | |
583 | reg &= 0x7F; | |
584 | pci_write_config_byte(dev, drive_pci+1, reg); | |
585 | } | |
586 | } | |
587 | ||
588 | /* Config chip for mode */ | |
589 | switch(speed) { | |
590 | case XFER_UDMA_6: | |
591 | case XFER_UDMA_5: | |
592 | case XFER_UDMA_4: | |
593 | case XFER_UDMA_3: | |
594 | case XFER_UDMA_2: | |
595 | case XFER_UDMA_1: | |
596 | case XFER_UDMA_0: | |
597 | if (chipset_family >= ATA_133) { | |
598 | regdw |= 0x04; | |
599 | regdw &= 0xfffff00f; | |
600 | /* check if ATA133 enable */ | |
601 | if (regdw & 0x08) { | |
602 | regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4; | |
603 | regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8; | |
604 | } else { | |
605 | /* if ATA133 disable, we should not set speed above UDMA5 */ | |
606 | if (speed > XFER_UDMA_5) | |
607 | speed = XFER_UDMA_5; | |
608 | regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4; | |
609 | regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8; | |
610 | } | |
611 | pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); | |
612 | } else { | |
613 | /* Force the UDMA bit on if we want to use UDMA */ | |
614 | reg |= 0x80; | |
615 | /* clean reg cycle time bits */ | |
616 | reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family])) | |
617 | << cycle_time_offset[chipset_family]); | |
618 | /* set reg cycle time bits */ | |
619 | reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0] | |
620 | << cycle_time_offset[chipset_family]; | |
621 | pci_write_config_byte(dev, drive_pci+1, reg); | |
622 | } | |
623 | break; | |
624 | case XFER_MW_DMA_2: | |
625 | case XFER_MW_DMA_1: | |
626 | case XFER_MW_DMA_0: | |
627 | case XFER_SW_DMA_2: | |
628 | case XFER_SW_DMA_1: | |
629 | case XFER_SW_DMA_0: | |
630 | break; | |
631 | case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4)); | |
632 | case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3)); | |
633 | case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2)); | |
634 | case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1)); | |
635 | case XFER_PIO_0: | |
636 | default: return((int) config_chipset_for_pio(drive, 0)); | |
637 | } | |
638 | ||
639 | return ((int) ide_config_drive_speed(drive, speed)); | |
640 | } | |
641 | ||
642 | static void sis5513_tune_drive (ide_drive_t *drive, u8 pio) | |
643 | { | |
644 | (void) config_chipset_for_pio(drive, pio); | |
645 | } | |
646 | ||
647 | /* | |
648 | * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four)) | |
649 | */ | |
650 | static int config_chipset_for_dma (ide_drive_t *drive) | |
651 | { | |
652 | u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive)); | |
653 | ||
654 | #ifdef DEBUG | |
655 | printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n", | |
656 | drive->dn, drive->id->dma_ultra); | |
657 | #endif | |
658 | ||
659 | if (!(speed)) | |
660 | return 0; | |
661 | ||
662 | sis5513_tune_chipset(drive, speed); | |
663 | return ide_dma_enable(drive); | |
664 | } | |
665 | ||
666 | static int sis5513_config_drive_xfer_rate (ide_drive_t *drive) | |
667 | { | |
668 | ide_hwif_t *hwif = HWIF(drive); | |
669 | struct hd_driveid *id = drive->id; | |
670 | ||
671 | drive->init_speed = 0; | |
672 | ||
673 | if (id && (id->capability & 1) && drive->autodma) { | |
674 | ||
675 | if (ide_use_dma(drive)) { | |
676 | if (config_chipset_for_dma(drive)) | |
677 | return hwif->ide_dma_on(drive); | |
678 | } | |
679 | ||
680 | goto fast_ata_pio; | |
681 | ||
682 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
683 | fast_ata_pio: | |
684 | sis5513_tune_drive(drive, 5); | |
685 | return hwif->ide_dma_off_quietly(drive); | |
686 | } | |
687 | /* IORDY not supported */ | |
688 | return 0; | |
689 | } | |
690 | ||
691 | /* initiates/aborts (U)DMA read/write operations on a drive. */ | |
692 | static int sis5513_config_xfer_rate (ide_drive_t *drive) | |
693 | { | |
694 | config_drive_art_rwp(drive); | |
695 | config_art_rwp_pio(drive, 5); | |
696 | return sis5513_config_drive_xfer_rate(drive); | |
697 | } | |
698 | ||
699 | /* | |
700 | Future simpler config_xfer_rate : | |
701 | When ide_find_best_mode is made bad-drive aware | |
702 | - remove config_drive_xfer_rate and config_chipset_for_dma, | |
703 | - replace config_xfer_rate with the following | |
704 | ||
705 | static int sis5513_config_xfer_rate (ide_drive_t *drive) | |
706 | { | |
707 | u16 w80 = HWIF(drive)->udma_four; | |
708 | u16 speed; | |
709 | ||
710 | config_drive_art_rwp(drive); | |
711 | config_art_rwp_pio(drive, 5); | |
712 | ||
713 | speed = ide_find_best_mode(drive, | |
714 | XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA | | |
715 | (chipset_family >= ATA_33 ? XFER_UDMA : 0) | | |
716 | (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) | | |
717 | (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) | | |
718 | (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0)); | |
719 | ||
720 | sis5513_tune_chipset(drive, speed); | |
721 | ||
722 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) | |
723 | return HWIF(drive)->ide_dma_on(drive); | |
724 | return HWIF(drive)->ide_dma_off_quietly(drive); | |
725 | } | |
726 | */ | |
727 | ||
728 | /* Chip detection and general config */ | |
729 | static unsigned int __init init_chipset_sis5513 (struct pci_dev *dev, const char *name) | |
730 | { | |
731 | struct pci_dev *host; | |
732 | int i = 0; | |
733 | ||
734 | chipset_family = 0; | |
735 | ||
736 | for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) { | |
737 | ||
738 | host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL); | |
739 | ||
740 | if (!host) | |
741 | continue; | |
742 | ||
743 | chipset_family = SiSHostChipInfo[i].chipset_family; | |
744 | ||
745 | /* Special case for SiS630 : 630S/ET is ATA_100a */ | |
746 | if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) { | |
747 | u8 hostrev; | |
748 | pci_read_config_byte(host, PCI_REVISION_ID, &hostrev); | |
749 | if (hostrev >= 0x30) | |
750 | chipset_family = ATA_100a; | |
751 | } | |
752 | ||
753 | printk(KERN_INFO "SIS5513: %s %s controller\n", | |
754 | SiSHostChipInfo[i].name, chipset_capability[chipset_family]); | |
755 | } | |
756 | ||
757 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
758 | ||
759 | u32 idemisc; | |
760 | u16 trueid; | |
761 | ||
762 | /* Disable ID masking and register remapping */ | |
763 | pci_read_config_dword(dev, 0x54, &idemisc); | |
764 | pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff)); | |
765 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
766 | pci_write_config_dword(dev, 0x54, idemisc); | |
767 | ||
768 | if (trueid == 0x5518) { | |
769 | printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n"); | |
770 | chipset_family = ATA_133; | |
771 | ||
772 | /* Check for 5513 compability mapping | |
773 | * We must use this, else the port enabled code will fail, | |
774 | * as it expects the enablebits at 0x4a. | |
775 | */ | |
776 | if ((idemisc & 0x40000000) == 0) { | |
777 | pci_write_config_dword(dev, 0x54, idemisc | 0x40000000); | |
778 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
779 | } | |
780 | } | |
781 | } | |
782 | ||
783 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
784 | ||
785 | struct pci_dev *lpc_bridge; | |
786 | u16 trueid; | |
787 | u8 prefctl; | |
788 | u8 idecfg; | |
789 | u8 sbrev; | |
790 | ||
791 | pci_read_config_byte(dev, 0x4a, &idecfg); | |
792 | pci_write_config_byte(dev, 0x4a, idecfg | 0x10); | |
793 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
794 | pci_write_config_byte(dev, 0x4a, idecfg); | |
795 | ||
796 | if (trueid == 0x5517) { /* SiS 961/961B */ | |
797 | ||
798 | lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */ | |
799 | pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev); | |
800 | pci_read_config_byte(dev, 0x49, &prefctl); | |
801 | ||
802 | if (sbrev == 0x10 && (prefctl & 0x80)) { | |
803 | printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n"); | |
804 | chipset_family = ATA_133a; | |
805 | } else { | |
806 | printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n"); | |
807 | chipset_family = ATA_100; | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | if (!chipset_family) | |
813 | return -1; | |
814 | ||
815 | /* Make general config ops here | |
816 | 1/ tell IDE channels to operate in Compatibility mode only | |
817 | 2/ tell old chips to allow per drive IDE timings */ | |
818 | ||
819 | { | |
820 | u8 reg; | |
821 | u16 regw; | |
822 | ||
823 | switch(chipset_family) { | |
824 | case ATA_133: | |
825 | /* SiS962 operation mode */ | |
826 | pci_read_config_word(dev, 0x50, ®w); | |
827 | if (regw & 0x08) | |
828 | pci_write_config_word(dev, 0x50, regw&0xfff7); | |
829 | pci_read_config_word(dev, 0x52, ®w); | |
830 | if (regw & 0x08) | |
831 | pci_write_config_word(dev, 0x52, regw&0xfff7); | |
832 | break; | |
833 | case ATA_133a: | |
834 | case ATA_100: | |
835 | /* Fixup latency */ | |
836 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); | |
837 | /* Set compatibility bit */ | |
838 | pci_read_config_byte(dev, 0x49, ®); | |
839 | if (!(reg & 0x01)) { | |
840 | pci_write_config_byte(dev, 0x49, reg|0x01); | |
841 | } | |
842 | break; | |
843 | case ATA_100a: | |
844 | case ATA_66: | |
845 | /* Fixup latency */ | |
846 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10); | |
847 | ||
848 | /* On ATA_66 chips the bit was elsewhere */ | |
849 | pci_read_config_byte(dev, 0x52, ®); | |
850 | if (!(reg & 0x04)) { | |
851 | pci_write_config_byte(dev, 0x52, reg|0x04); | |
852 | } | |
853 | break; | |
854 | case ATA_33: | |
855 | /* On ATA_33 we didn't have a single bit to set */ | |
856 | pci_read_config_byte(dev, 0x09, ®); | |
857 | if ((reg & 0x0f) != 0x00) { | |
858 | pci_write_config_byte(dev, 0x09, reg&0xf0); | |
859 | } | |
860 | case ATA_16: | |
861 | /* force per drive recovery and active timings | |
862 | needed on ATA_33 and below chips */ | |
863 | pci_read_config_byte(dev, 0x52, ®); | |
864 | if (!(reg & 0x08)) { | |
865 | pci_write_config_byte(dev, 0x52, reg|0x08); | |
866 | } | |
867 | break; | |
868 | } | |
869 | ||
870 | #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) | |
871 | if (!sis_proc) { | |
872 | sis_proc = 1; | |
873 | bmide_dev = dev; | |
874 | ide_pci_create_host_proc("sis", sis_get_info); | |
875 | } | |
876 | #endif | |
877 | } | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | static unsigned int __init ata66_sis5513 (ide_hwif_t *hwif) | |
883 | { | |
884 | u8 ata66 = 0; | |
885 | ||
886 | if (chipset_family >= ATA_133) { | |
887 | u16 regw = 0; | |
888 | u16 reg_addr = hwif->channel ? 0x52: 0x50; | |
889 | pci_read_config_word(hwif->pci_dev, reg_addr, ®w); | |
890 | ata66 = (regw & 0x8000) ? 0 : 1; | |
891 | } else if (chipset_family >= ATA_66) { | |
892 | u8 reg48h = 0; | |
893 | u8 mask = hwif->channel ? 0x20 : 0x10; | |
894 | pci_read_config_byte(hwif->pci_dev, 0x48, ®48h); | |
895 | ata66 = (reg48h & mask) ? 0 : 1; | |
896 | } | |
897 | return ata66; | |
898 | } | |
899 | ||
900 | static void __init init_hwif_sis5513 (ide_hwif_t *hwif) | |
901 | { | |
902 | hwif->autodma = 0; | |
903 | ||
904 | if (!hwif->irq) | |
905 | hwif->irq = hwif->channel ? 15 : 14; | |
906 | ||
907 | hwif->tuneproc = &sis5513_tune_drive; | |
908 | hwif->speedproc = &sis5513_tune_chipset; | |
909 | ||
910 | if (!(hwif->dma_base)) { | |
911 | hwif->drives[0].autotune = 1; | |
912 | hwif->drives[1].autotune = 1; | |
913 | return; | |
914 | } | |
915 | ||
916 | hwif->atapi_dma = 1; | |
917 | hwif->ultra_mask = 0x7f; | |
918 | hwif->mwdma_mask = 0x07; | |
919 | hwif->swdma_mask = 0x07; | |
920 | ||
921 | if (!chipset_family) | |
922 | return; | |
923 | ||
924 | if (!(hwif->udma_four)) | |
925 | hwif->udma_four = ata66_sis5513(hwif); | |
926 | ||
927 | if (chipset_family > ATA_16) { | |
928 | hwif->ide_dma_check = &sis5513_config_xfer_rate; | |
929 | if (!noautodma) | |
930 | hwif->autodma = 1; | |
931 | } | |
932 | hwif->drives[0].autodma = hwif->autodma; | |
933 | hwif->drives[1].autodma = hwif->autodma; | |
934 | return; | |
935 | } | |
936 | ||
937 | static ide_pci_device_t sis5513_chipset __devinitdata = { | |
938 | .name = "SIS5513", | |
939 | .init_chipset = init_chipset_sis5513, | |
940 | .init_hwif = init_hwif_sis5513, | |
941 | .channels = 2, | |
942 | .autodma = NOAUTODMA, | |
943 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
944 | .bootable = ON_BOARD, | |
945 | }; | |
946 | ||
947 | static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
948 | { | |
949 | return ide_setup_pci_device(dev, &sis5513_chipset); | |
950 | } | |
951 | ||
952 | static struct pci_device_id sis5513_pci_tbl[] = { | |
953 | { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
954 | { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
955 | { 0, }, | |
956 | }; | |
957 | MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl); | |
958 | ||
959 | static struct pci_driver driver = { | |
960 | .name = "SIS_IDE", | |
961 | .id_table = sis5513_pci_tbl, | |
962 | .probe = sis5513_init_one, | |
963 | }; | |
964 | ||
965 | static int sis5513_ide_init(void) | |
966 | { | |
967 | return ide_pci_register_driver(&driver); | |
968 | } | |
969 | ||
970 | module_init(sis5513_ide_init); | |
971 | ||
972 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); | |
973 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); | |
974 | MODULE_LICENSE("GPL"); | |
975 | ||
976 | /* | |
977 | * TODO: | |
978 | * - CLEANUP | |
979 | * - Use drivers/ide/ide-timing.h ! | |
980 | * - More checks in the config registers (force values instead of | |
981 | * relying on the BIOS setting them correctly). | |
982 | * - Further optimisations ? | |
983 | * . for example ATA66+ regs 0x48 & 0x4A | |
984 | */ |