Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sl82c105.c | |
3 | * | |
4 | * SL82C105/Winbond 553 IDE driver | |
5 | * | |
6 | * Maintainer unknown. | |
7 | * | |
8 | * Drive tuning added from Rebel.com's kernel sources | |
9 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
10 | * | |
11 | * Merge in Russell's HW workarounds, fix various problems | |
12 | * with the timing registers setup. | |
13 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
14 | * |
15 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/blkdev.h> | |
26 | #include <linux/hdreg.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/ide.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/dma.h> | |
32 | ||
33 | #undef DEBUG | |
34 | ||
35 | #ifdef DEBUG | |
36 | #define DBG(arg) printk arg | |
37 | #else | |
38 | #define DBG(fmt,...) | |
39 | #endif | |
40 | /* | |
41 | * SL82C105 PCI config register 0x40 bits. | |
42 | */ | |
43 | #define CTRL_IDE_IRQB (1 << 30) | |
44 | #define CTRL_IDE_IRQA (1 << 28) | |
45 | #define CTRL_LEGIRQ (1 << 11) | |
46 | #define CTRL_P1F16 (1 << 5) | |
47 | #define CTRL_P1EN (1 << 4) | |
48 | #define CTRL_P0F16 (1 << 1) | |
49 | #define CTRL_P0EN (1 << 0) | |
50 | ||
51 | /* | |
e93df705 SS |
52 | * Convert a PIO mode and cycle time to the required on/off times |
53 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 54 | */ |
e93df705 | 55 | static unsigned int get_pio_timings(ide_pio_data_t *p) |
1da177e4 | 56 | { |
e93df705 | 57 | unsigned int cmd_on, cmd_off; |
1da177e4 | 58 | |
e93df705 | 59 | cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30; |
1da177e4 LT |
60 | cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30; |
61 | ||
1da177e4 LT |
62 | if (cmd_on == 0) |
63 | cmd_on = 1; | |
64 | ||
1da177e4 LT |
65 | if (cmd_off == 0) |
66 | cmd_off = 1; | |
67 | ||
68 | return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00); | |
69 | } | |
70 | ||
71 | /* | |
e93df705 | 72 | * Configure the chipset for PIO mode. |
1da177e4 | 73 | */ |
e93df705 | 74 | static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio) |
1da177e4 | 75 | { |
e93df705 SS |
76 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
77 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 78 | ide_pio_data_t p; |
e93df705 | 79 | u16 drv_ctrl; |
1da177e4 | 80 | |
e93df705 | 81 | DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 LT |
82 | |
83 | pio = ide_get_best_pio_mode(drive, pio, 5, &p); | |
84 | ||
e93df705 | 85 | drive->drive_data = drv_ctrl = get_pio_timings(&p); |
1da177e4 | 86 | |
e93df705 | 87 | if (!drive->using_dma) { |
1da177e4 LT |
88 | /* |
89 | * If we are actually using MW DMA, then we can not | |
90 | * reprogram the interface drive control register. | |
91 | */ | |
e93df705 SS |
92 | pci_write_config_word(dev, reg, drv_ctrl); |
93 | pci_read_config_word (dev, reg, &drv_ctrl); | |
1da177e4 | 94 | } |
e93df705 SS |
95 | |
96 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
97 | ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl); | |
98 | ||
99 | return pio; | |
1da177e4 LT |
100 | } |
101 | ||
102 | /* | |
688a87d1 SS |
103 | * Configure the drive for DMA. |
104 | * We'll program the chipset only when DMA is actually turned on. | |
1da177e4 | 105 | */ |
688a87d1 | 106 | static int config_for_dma(ide_drive_t *drive) |
1da177e4 | 107 | { |
1da177e4 LT |
108 | DBG(("config_for_dma(drive:%s)\n", drive->name)); |
109 | ||
1da177e4 | 110 | if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) |
688a87d1 | 111 | return 0; |
1da177e4 | 112 | |
688a87d1 | 113 | return ide_dma_enable(drive); |
1da177e4 LT |
114 | } |
115 | ||
116 | /* | |
688a87d1 | 117 | * Check to see if the drive and chipset are capable of DMA mode. |
1da177e4 | 118 | */ |
688a87d1 | 119 | static int sl82c105_ide_dma_check(ide_drive_t *drive) |
1da177e4 | 120 | { |
688a87d1 | 121 | DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name)); |
1da177e4 | 122 | |
688a87d1 SS |
123 | if (ide_use_dma(drive) && config_for_dma(drive)) |
124 | return 0; | |
1da177e4 | 125 | |
3608b5d7 | 126 | return -1; |
1da177e4 LT |
127 | } |
128 | ||
129 | /* | |
130 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
131 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
132 | * when the drive wants to report an error condition). | |
133 | * | |
134 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
135 | * state machine. We need to kick this to work around various bugs. | |
136 | */ | |
137 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
138 | { | |
139 | u16 val; | |
140 | ||
141 | pci_read_config_word(dev, 0x7e, &val); | |
142 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
143 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
144 | } | |
145 | ||
146 | /* | |
147 | * If we get an IRQ timeout, it might be that the DMA state machine | |
148 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
149 | * | |
150 | * This function is called when the IDE timer expires, the drive | |
151 | * indicates that it is READY, and we were waiting for DMA to complete. | |
152 | */ | |
688a87d1 | 153 | static int sl82c105_ide_dma_lostirq(ide_drive_t *drive) |
1da177e4 | 154 | { |
688a87d1 SS |
155 | ide_hwif_t *hwif = HWIF(drive); |
156 | struct pci_dev *dev = hwif->pci_dev; | |
157 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
158 | u8 dma_cmd; | |
1da177e4 | 159 | |
688a87d1 | 160 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
161 | |
162 | /* | |
163 | * Check the raw interrupt from the drive. | |
164 | */ | |
165 | pci_read_config_dword(dev, 0x40, &val); | |
166 | if (val & mask) | |
167 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
168 | ||
169 | /* | |
170 | * Was DMA enabled? If so, disable it - we're resetting the | |
171 | * host. The IDE layer will be handling the drive for us. | |
172 | */ | |
688a87d1 SS |
173 | dma_cmd = inb(hwif->dma_command); |
174 | if (dma_cmd & 1) { | |
175 | outb(dma_cmd & ~1, hwif->dma_command); | |
1da177e4 LT |
176 | printk("sl82c105: DMA was enabled\n"); |
177 | } | |
178 | ||
179 | sl82c105_reset_host(dev); | |
180 | ||
688a87d1 | 181 | /* __ide_dma_lostirq would return 1, so we do as well */ |
1da177e4 LT |
182 | return 1; |
183 | } | |
184 | ||
185 | /* | |
186 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
187 | * Winbond recommend that the DMA state machine is reset prior to | |
188 | * setting the bus master DMA enable bit. | |
189 | * | |
190 | * The generic IDE core will have disabled the BMEN bit before this | |
191 | * function is called. | |
192 | */ | |
688a87d1 | 193 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 194 | { |
688a87d1 SS |
195 | ide_hwif_t *hwif = HWIF(drive); |
196 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
197 | |
198 | sl82c105_reset_host(dev); | |
199 | ide_dma_start(drive); | |
200 | } | |
201 | ||
202 | static int sl82c105_ide_dma_timeout(ide_drive_t *drive) | |
203 | { | |
688a87d1 SS |
204 | ide_hwif_t *hwif = HWIF(drive); |
205 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
206 | |
207 | DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name)); | |
208 | ||
209 | sl82c105_reset_host(dev); | |
210 | return __ide_dma_timeout(drive); | |
211 | } | |
212 | ||
688a87d1 | 213 | static int sl82c105_ide_dma_on(ide_drive_t *drive) |
1da177e4 | 214 | { |
688a87d1 SS |
215 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
216 | int rc, reg = 0x44 + drive->dn * 4; | |
217 | ||
1da177e4 LT |
218 | DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name)); |
219 | ||
688a87d1 SS |
220 | rc = __ide_dma_on(drive); |
221 | if (rc == 0) { | |
222 | pci_write_config_word(dev, reg, 0x0200); | |
223 | ||
224 | printk(KERN_INFO "%s: DMA enabled\n", drive->name); | |
225 | } | |
226 | return rc; | |
1da177e4 LT |
227 | } |
228 | ||
7469aaf6 | 229 | static void sl82c105_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 230 | { |
e93df705 SS |
231 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
232 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 233 | |
7469aaf6 BZ |
234 | DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name)); |
235 | ||
e93df705 SS |
236 | pci_write_config_word(dev, reg, drive->drive_data); |
237 | ||
7469aaf6 | 238 | ide_dma_off_quietly(drive); |
1da177e4 LT |
239 | } |
240 | ||
241 | /* | |
242 | * Ok, that is nasty, but we must make sure the DMA timings | |
243 | * won't be used for a PIO access. The solution here is | |
244 | * to make sure the 16 bits mode is diabled on the channel | |
245 | * when DMA is enabled, thus causing the chip to use PIO0 | |
246 | * timings for those operations. | |
247 | */ | |
248 | static void sl82c105_selectproc(ide_drive_t *drive) | |
249 | { | |
688a87d1 SS |
250 | ide_hwif_t *hwif = HWIF(drive); |
251 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
252 | u32 val, old, mask; |
253 | ||
254 | //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); | |
255 | ||
256 | mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16; | |
dd607d23 | 257 | old = val = (u32)pci_get_drvdata(dev); |
1da177e4 LT |
258 | if (drive->using_dma) |
259 | val &= ~mask; | |
260 | else | |
261 | val |= mask; | |
262 | if (old != val) { | |
263 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 264 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
265 | } |
266 | } | |
267 | ||
268 | /* | |
269 | * ATA reset will clear the 16 bits mode in the control | |
270 | * register, we need to update our cache | |
271 | */ | |
272 | static void sl82c105_resetproc(ide_drive_t *drive) | |
273 | { | |
dd607d23 | 274 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
1da177e4 LT |
275 | u32 val; |
276 | ||
277 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
278 | ||
279 | pci_read_config_dword(dev, 0x40, &val); | |
dd607d23 | 280 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
281 | } |
282 | ||
283 | /* | |
284 | * We only deal with PIO mode here - DMA mode 'using_dma' is not | |
285 | * initialised at the point that this function is called. | |
286 | */ | |
e93df705 | 287 | static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio) |
1da177e4 | 288 | { |
e93df705 | 289 | DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio)); |
1da177e4 | 290 | |
e93df705 SS |
291 | pio = sl82c105_tune_pio(drive, pio); |
292 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
293 | } |
294 | ||
295 | /* | |
296 | * Return the revision of the Winbond bridge | |
297 | * which this function is part of. | |
298 | */ | |
299 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
300 | { | |
301 | struct pci_dev *bridge; | |
302 | u8 rev; | |
303 | ||
304 | /* | |
305 | * The bridge should be part of the same device, but function 0. | |
306 | */ | |
307 | bridge = pci_find_slot(dev->bus->number, | |
308 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
309 | if (!bridge) | |
310 | return -1; | |
311 | ||
312 | /* | |
313 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
314 | */ | |
315 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
316 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
317 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) | |
318 | return -1; | |
319 | ||
320 | /* | |
321 | * We need to find function 0's revision, not function 1 | |
322 | */ | |
323 | pci_read_config_byte(bridge, PCI_REVISION_ID, &rev); | |
324 | ||
325 | return rev; | |
326 | } | |
327 | ||
328 | /* | |
329 | * Enable the PCI device | |
330 | * | |
331 | * --BenH: It's arch fixup code that should enable channels that | |
332 | * have not been enabled by firmware. I decided we can still enable | |
333 | * channel 0 here at least, but channel 1 has to be enabled by | |
334 | * firmware or arch code. We still set both to 16 bits mode. | |
335 | */ | |
34a62246 | 336 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
337 | { |
338 | u32 val; | |
339 | ||
340 | DBG(("init_chipset_sl82c105()\n")); | |
341 | ||
342 | pci_read_config_dword(dev, 0x40, &val); | |
343 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
344 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 345 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
346 | |
347 | return dev->irq; | |
348 | } | |
349 | ||
1da177e4 | 350 | /* |
688a87d1 | 351 | * Initialise IDE channel |
1da177e4 | 352 | */ |
34a62246 | 353 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 354 | { |
9648f552 | 355 | unsigned int rev; |
dd607d23 | 356 | |
1da177e4 LT |
357 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
358 | ||
e93df705 SS |
359 | hwif->tuneproc = &sl82c105_tune_drive; |
360 | hwif->selectproc = &sl82c105_selectproc; | |
361 | hwif->resetproc = &sl82c105_resetproc; | |
362 | ||
363 | /* | |
364 | * We support 32-bit I/O on this interface, and | |
365 | * it doesn't have problems with interrupts. | |
366 | */ | |
367 | hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1; | |
368 | hwif->drives[0].unmask = hwif->drives[1].unmask = 1; | |
dd607d23 SS |
369 | |
370 | /* | |
dd607d23 SS |
371 | * We always autotune PIO, this is done before DMA is checked, |
372 | * so there's no risk of accidentally disabling DMA | |
373 | */ | |
e93df705 | 374 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1da177e4 | 375 | |
1da177e4 LT |
376 | if (!hwif->dma_base) |
377 | return; | |
378 | ||
9648f552 RK |
379 | rev = sl82c105_bridge_revision(hwif->pci_dev); |
380 | if (rev <= 5) { | |
381 | /* | |
382 | * Never ever EVER under any circumstances enable | |
383 | * DMA when the bridge is this old. | |
384 | */ | |
688a87d1 SS |
385 | printk(" %s: Winbond W83C553 bridge revision %d, " |
386 | "BM-DMA disabled\n", hwif->name, rev); | |
387 | return; | |
9648f552 | 388 | } |
688a87d1 SS |
389 | |
390 | hwif->atapi_dma = 1; | |
391 | hwif->mwdma_mask = 0x04; | |
392 | ||
393 | hwif->ide_dma_check = &sl82c105_ide_dma_check; | |
394 | hwif->ide_dma_on = &sl82c105_ide_dma_on; | |
395 | hwif->dma_off_quietly = &sl82c105_dma_off_quietly; | |
396 | hwif->ide_dma_lostirq = &sl82c105_ide_dma_lostirq; | |
397 | hwif->dma_start = &sl82c105_dma_start; | |
398 | hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout; | |
399 | ||
400 | if (!noautodma) | |
401 | hwif->autodma = 1; | |
402 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; | |
403 | ||
404 | if (hwif->mate) | |
405 | hwif->serialized = hwif->mate->serialized = 1; | |
1da177e4 LT |
406 | } |
407 | ||
408 | static ide_pci_device_t sl82c105_chipset __devinitdata = { | |
409 | .name = "W82C105", | |
410 | .init_chipset = init_chipset_sl82c105, | |
411 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 LT |
412 | .channels = 2, |
413 | .autodma = NOAUTODMA, | |
414 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, | |
415 | .bootable = ON_BOARD, | |
416 | }; | |
417 | ||
418 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
419 | { | |
420 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
421 | } | |
422 | ||
423 | static struct pci_device_id sl82c105_pci_tbl[] = { | |
f201f504 | 424 | { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0}, |
1da177e4 LT |
425 | { 0, }, |
426 | }; | |
427 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
428 | ||
429 | static struct pci_driver driver = { | |
430 | .name = "W82C105_IDE", | |
431 | .id_table = sl82c105_pci_tbl, | |
432 | .probe = sl82c105_init_one, | |
433 | }; | |
434 | ||
82ab1eec | 435 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
436 | { |
437 | return ide_pci_register_driver(&driver); | |
438 | } | |
439 | ||
440 | module_init(sl82c105_ide_init); | |
441 | ||
442 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
443 | MODULE_LICENSE("GPL"); |