Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/sl82c105.c | |
3 | * | |
4 | * SL82C105/Winbond 553 IDE driver | |
5 | * | |
6 | * Maintainer unknown. | |
7 | * | |
8 | * Drive tuning added from Rebel.com's kernel sources | |
9 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
10 | * | |
11 | * Merge in Russell's HW workarounds, fix various problems | |
12 | * with the timing registers setup. | |
13 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
14 | * |
15 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/blkdev.h> | |
26 | #include <linux/hdreg.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/ide.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/dma.h> | |
32 | ||
33 | #undef DEBUG | |
34 | ||
35 | #ifdef DEBUG | |
36 | #define DBG(arg) printk arg | |
37 | #else | |
38 | #define DBG(fmt,...) | |
39 | #endif | |
40 | /* | |
41 | * SL82C105 PCI config register 0x40 bits. | |
42 | */ | |
43 | #define CTRL_IDE_IRQB (1 << 30) | |
44 | #define CTRL_IDE_IRQA (1 << 28) | |
45 | #define CTRL_LEGIRQ (1 << 11) | |
46 | #define CTRL_P1F16 (1 << 5) | |
47 | #define CTRL_P1EN (1 << 4) | |
48 | #define CTRL_P0F16 (1 << 1) | |
49 | #define CTRL_P0EN (1 << 0) | |
50 | ||
51 | /* | |
e93df705 SS |
52 | * Convert a PIO mode and cycle time to the required on/off times |
53 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 54 | */ |
7dd00083 | 55 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 56 | { |
e93df705 | 57 | unsigned int cmd_on, cmd_off; |
2229833c | 58 | u8 iordy = 0; |
1da177e4 | 59 | |
7dd00083 BZ |
60 | cmd_on = (ide_pio_timings[pio].active_time + 29) / 30; |
61 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; | |
1da177e4 | 62 | |
1da177e4 LT |
63 | if (cmd_on == 0) |
64 | cmd_on = 1; | |
65 | ||
1da177e4 LT |
66 | if (cmd_off == 0) |
67 | cmd_off = 1; | |
68 | ||
7dd00083 | 69 | if (pio > 2 || ide_dev_has_iordy(drive->id)) |
2229833c BZ |
70 | iordy = 0x40; |
71 | ||
72 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
73 | } |
74 | ||
75 | /* | |
e93df705 | 76 | * Configure the chipset for PIO mode. |
1da177e4 | 77 | */ |
26bcb879 | 78 | static void sl82c105_tune_pio(ide_drive_t *drive, const u8 pio) |
1da177e4 | 79 | { |
e93df705 SS |
80 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
81 | int reg = 0x44 + drive->dn * 4; | |
e93df705 | 82 | u16 drv_ctrl; |
1da177e4 | 83 | |
7dd00083 | 84 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
85 | |
86 | /* | |
87 | * Store the PIO timings so that we can restore them | |
88 | * in case DMA will be turned off... | |
89 | */ | |
90 | drive->drive_data &= 0xffff0000; | |
91 | drive->drive_data |= drv_ctrl; | |
1da177e4 | 92 | |
e93df705 | 93 | if (!drive->using_dma) { |
1da177e4 LT |
94 | /* |
95 | * If we are actually using MW DMA, then we can not | |
96 | * reprogram the interface drive control register. | |
97 | */ | |
e93df705 SS |
98 | pci_write_config_word(dev, reg, drv_ctrl); |
99 | pci_read_config_word (dev, reg, &drv_ctrl); | |
1da177e4 | 100 | } |
e93df705 SS |
101 | |
102 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
103 | ide_xfer_verbose(pio + XFER_PIO_0), |
104 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
1da177e4 LT |
105 | } |
106 | ||
46cedc9b SS |
107 | /* |
108 | * Configure the drive and chipset for a new transfer speed. | |
109 | */ | |
f212ff28 | 110 | static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed) |
46cedc9b SS |
111 | { |
112 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
113 | u16 drv_ctrl; | |
114 | ||
115 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | |
116 | drive->name, ide_xfer_verbose(speed))); | |
117 | ||
46cedc9b SS |
118 | switch (speed) { |
119 | case XFER_MW_DMA_2: | |
120 | case XFER_MW_DMA_1: | |
121 | case XFER_MW_DMA_0: | |
122 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; | |
123 | ||
124 | /* | |
125 | * Store the DMA timings so that we can actually program | |
126 | * them when DMA will be turned on... | |
127 | */ | |
128 | drive->drive_data &= 0x0000ffff; | |
129 | drive->drive_data |= (unsigned long)drv_ctrl << 16; | |
130 | ||
131 | /* | |
132 | * If we are already using DMA, we just reprogram | |
133 | * the drive control register. | |
134 | */ | |
135 | if (drive->using_dma) { | |
136 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
137 | int reg = 0x44 + drive->dn * 4; | |
138 | ||
139 | pci_write_config_word(dev, reg, drv_ctrl); | |
140 | } | |
141 | break; | |
46cedc9b SS |
142 | default: |
143 | return -1; | |
144 | } | |
145 | ||
146 | return ide_config_drive_speed(drive, speed); | |
147 | } | |
148 | ||
1da177e4 | 149 | /* |
688a87d1 | 150 | * Check to see if the drive and chipset are capable of DMA mode. |
1da177e4 | 151 | */ |
688a87d1 | 152 | static int sl82c105_ide_dma_check(ide_drive_t *drive) |
1da177e4 | 153 | { |
688a87d1 | 154 | DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name)); |
1da177e4 | 155 | |
4728d546 | 156 | if (ide_tune_dma(drive)) |
688a87d1 | 157 | return 0; |
1da177e4 | 158 | |
3608b5d7 | 159 | return -1; |
1da177e4 LT |
160 | } |
161 | ||
162 | /* | |
163 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
164 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
165 | * when the drive wants to report an error condition). | |
166 | * | |
167 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
168 | * state machine. We need to kick this to work around various bugs. | |
169 | */ | |
170 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
171 | { | |
172 | u16 val; | |
173 | ||
174 | pci_read_config_word(dev, 0x7e, &val); | |
175 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
176 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
177 | } | |
178 | ||
179 | /* | |
180 | * If we get an IRQ timeout, it might be that the DMA state machine | |
181 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
182 | * | |
183 | * This function is called when the IDE timer expires, the drive | |
184 | * indicates that it is READY, and we were waiting for DMA to complete. | |
185 | */ | |
841d2a9b | 186 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 187 | { |
688a87d1 SS |
188 | ide_hwif_t *hwif = HWIF(drive); |
189 | struct pci_dev *dev = hwif->pci_dev; | |
190 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
191 | u8 dma_cmd; | |
1da177e4 | 192 | |
688a87d1 | 193 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
194 | |
195 | /* | |
196 | * Check the raw interrupt from the drive. | |
197 | */ | |
198 | pci_read_config_dword(dev, 0x40, &val); | |
199 | if (val & mask) | |
200 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
201 | ||
202 | /* | |
203 | * Was DMA enabled? If so, disable it - we're resetting the | |
204 | * host. The IDE layer will be handling the drive for us. | |
205 | */ | |
688a87d1 SS |
206 | dma_cmd = inb(hwif->dma_command); |
207 | if (dma_cmd & 1) { | |
208 | outb(dma_cmd & ~1, hwif->dma_command); | |
1da177e4 LT |
209 | printk("sl82c105: DMA was enabled\n"); |
210 | } | |
211 | ||
212 | sl82c105_reset_host(dev); | |
1da177e4 LT |
213 | } |
214 | ||
215 | /* | |
216 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
217 | * Winbond recommend that the DMA state machine is reset prior to | |
218 | * setting the bus master DMA enable bit. | |
219 | * | |
220 | * The generic IDE core will have disabled the BMEN bit before this | |
221 | * function is called. | |
222 | */ | |
688a87d1 | 223 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 224 | { |
688a87d1 SS |
225 | ide_hwif_t *hwif = HWIF(drive); |
226 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
227 | |
228 | sl82c105_reset_host(dev); | |
229 | ide_dma_start(drive); | |
230 | } | |
231 | ||
c283f5db | 232 | static void sl82c105_dma_timeout(ide_drive_t *drive) |
1da177e4 | 233 | { |
c283f5db | 234 | DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name)); |
1da177e4 | 235 | |
c283f5db SS |
236 | sl82c105_reset_host(HWIF(drive)->pci_dev); |
237 | ide_dma_timeout(drive); | |
1da177e4 LT |
238 | } |
239 | ||
688a87d1 | 240 | static int sl82c105_ide_dma_on(ide_drive_t *drive) |
1da177e4 | 241 | { |
688a87d1 SS |
242 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
243 | int rc, reg = 0x44 + drive->dn * 4; | |
244 | ||
1da177e4 LT |
245 | DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name)); |
246 | ||
688a87d1 SS |
247 | rc = __ide_dma_on(drive); |
248 | if (rc == 0) { | |
46cedc9b | 249 | pci_write_config_word(dev, reg, drive->drive_data >> 16); |
688a87d1 SS |
250 | |
251 | printk(KERN_INFO "%s: DMA enabled\n", drive->name); | |
252 | } | |
253 | return rc; | |
1da177e4 LT |
254 | } |
255 | ||
7469aaf6 | 256 | static void sl82c105_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 257 | { |
e93df705 SS |
258 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
259 | int reg = 0x44 + drive->dn * 4; | |
1da177e4 | 260 | |
7469aaf6 BZ |
261 | DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name)); |
262 | ||
e93df705 SS |
263 | pci_write_config_word(dev, reg, drive->drive_data); |
264 | ||
7469aaf6 | 265 | ide_dma_off_quietly(drive); |
1da177e4 LT |
266 | } |
267 | ||
268 | /* | |
269 | * Ok, that is nasty, but we must make sure the DMA timings | |
270 | * won't be used for a PIO access. The solution here is | |
271 | * to make sure the 16 bits mode is diabled on the channel | |
272 | * when DMA is enabled, thus causing the chip to use PIO0 | |
273 | * timings for those operations. | |
274 | */ | |
275 | static void sl82c105_selectproc(ide_drive_t *drive) | |
276 | { | |
688a87d1 SS |
277 | ide_hwif_t *hwif = HWIF(drive); |
278 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
279 | u32 val, old, mask; |
280 | ||
281 | //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name)); | |
282 | ||
283 | mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16; | |
dd607d23 | 284 | old = val = (u32)pci_get_drvdata(dev); |
1da177e4 LT |
285 | if (drive->using_dma) |
286 | val &= ~mask; | |
287 | else | |
288 | val |= mask; | |
289 | if (old != val) { | |
290 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 291 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
292 | } |
293 | } | |
294 | ||
295 | /* | |
296 | * ATA reset will clear the 16 bits mode in the control | |
297 | * register, we need to update our cache | |
298 | */ | |
299 | static void sl82c105_resetproc(ide_drive_t *drive) | |
300 | { | |
dd607d23 | 301 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
1da177e4 LT |
302 | u32 val; |
303 | ||
304 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
305 | ||
306 | pci_read_config_dword(dev, 0x40, &val); | |
dd607d23 | 307 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
308 | } |
309 | ||
310 | /* | |
311 | * We only deal with PIO mode here - DMA mode 'using_dma' is not | |
312 | * initialised at the point that this function is called. | |
313 | */ | |
26bcb879 | 314 | static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 315 | { |
26bcb879 | 316 | sl82c105_tune_pio(drive, pio); |
1da177e4 | 317 | |
e93df705 | 318 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
319 | } |
320 | ||
321 | /* | |
322 | * Return the revision of the Winbond bridge | |
323 | * which this function is part of. | |
324 | */ | |
325 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
326 | { | |
327 | struct pci_dev *bridge; | |
1da177e4 LT |
328 | |
329 | /* | |
330 | * The bridge should be part of the same device, but function 0. | |
331 | */ | |
640b31bf | 332 | bridge = pci_get_bus_and_slot(dev->bus->number, |
1da177e4 LT |
333 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
334 | if (!bridge) | |
335 | return -1; | |
336 | ||
337 | /* | |
338 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
339 | */ | |
340 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
341 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
342 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
343 | pci_dev_put(bridge); | |
1da177e4 | 344 | return -1; |
640b31bf | 345 | } |
1da177e4 LT |
346 | /* |
347 | * We need to find function 0's revision, not function 1 | |
348 | */ | |
640b31bf | 349 | pci_dev_put(bridge); |
1da177e4 | 350 | |
44c10138 | 351 | return bridge->revision; |
1da177e4 LT |
352 | } |
353 | ||
354 | /* | |
355 | * Enable the PCI device | |
356 | * | |
357 | * --BenH: It's arch fixup code that should enable channels that | |
358 | * have not been enabled by firmware. I decided we can still enable | |
359 | * channel 0 here at least, but channel 1 has to be enabled by | |
360 | * firmware or arch code. We still set both to 16 bits mode. | |
361 | */ | |
34a62246 | 362 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
363 | { |
364 | u32 val; | |
365 | ||
366 | DBG(("init_chipset_sl82c105()\n")); | |
367 | ||
368 | pci_read_config_dword(dev, 0x40, &val); | |
369 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
370 | pci_write_config_dword(dev, 0x40, val); | |
dd607d23 | 371 | pci_set_drvdata(dev, (void *)val); |
1da177e4 LT |
372 | |
373 | return dev->irq; | |
374 | } | |
375 | ||
1da177e4 | 376 | /* |
688a87d1 | 377 | * Initialise IDE channel |
1da177e4 | 378 | */ |
34a62246 | 379 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 380 | { |
9648f552 | 381 | unsigned int rev; |
dd607d23 | 382 | |
1da177e4 LT |
383 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
384 | ||
26bcb879 | 385 | hwif->set_pio_mode = &sl82c105_set_pio_mode; |
46cedc9b | 386 | hwif->speedproc = &sl82c105_tune_chipset; |
e93df705 SS |
387 | hwif->selectproc = &sl82c105_selectproc; |
388 | hwif->resetproc = &sl82c105_resetproc; | |
389 | ||
390 | /* | |
391 | * We support 32-bit I/O on this interface, and | |
392 | * it doesn't have problems with interrupts. | |
393 | */ | |
394 | hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1; | |
395 | hwif->drives[0].unmask = hwif->drives[1].unmask = 1; | |
dd607d23 SS |
396 | |
397 | /* | |
dd607d23 SS |
398 | * We always autotune PIO, this is done before DMA is checked, |
399 | * so there's no risk of accidentally disabling DMA | |
400 | */ | |
e93df705 | 401 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1da177e4 | 402 | |
1da177e4 LT |
403 | if (!hwif->dma_base) |
404 | return; | |
405 | ||
9648f552 RK |
406 | rev = sl82c105_bridge_revision(hwif->pci_dev); |
407 | if (rev <= 5) { | |
408 | /* | |
409 | * Never ever EVER under any circumstances enable | |
410 | * DMA when the bridge is this old. | |
411 | */ | |
688a87d1 SS |
412 | printk(" %s: Winbond W83C553 bridge revision %d, " |
413 | "BM-DMA disabled\n", hwif->name, rev); | |
414 | return; | |
9648f552 | 415 | } |
688a87d1 SS |
416 | |
417 | hwif->atapi_dma = 1; | |
46cedc9b | 418 | hwif->mwdma_mask = 0x07; |
688a87d1 SS |
419 | |
420 | hwif->ide_dma_check = &sl82c105_ide_dma_check; | |
421 | hwif->ide_dma_on = &sl82c105_ide_dma_on; | |
422 | hwif->dma_off_quietly = &sl82c105_dma_off_quietly; | |
841d2a9b | 423 | hwif->dma_lost_irq = &sl82c105_dma_lost_irq; |
688a87d1 | 424 | hwif->dma_start = &sl82c105_dma_start; |
c283f5db | 425 | hwif->dma_timeout = &sl82c105_dma_timeout; |
688a87d1 SS |
426 | |
427 | if (!noautodma) | |
428 | hwif->autodma = 1; | |
429 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; | |
430 | ||
431 | if (hwif->mate) | |
432 | hwif->serialized = hwif->mate->serialized = 1; | |
1da177e4 LT |
433 | } |
434 | ||
435 | static ide_pci_device_t sl82c105_chipset __devinitdata = { | |
436 | .name = "W82C105", | |
437 | .init_chipset = init_chipset_sl82c105, | |
438 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 LT |
439 | .autodma = NOAUTODMA, |
440 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, | |
441 | .bootable = ON_BOARD, | |
4099d143 | 442 | .pio_mask = ATA_PIO5, |
1da177e4 LT |
443 | }; |
444 | ||
445 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
446 | { | |
447 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
448 | } | |
449 | ||
450 | static struct pci_device_id sl82c105_pci_tbl[] = { | |
f201f504 | 451 | { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0}, |
1da177e4 LT |
452 | { 0, }, |
453 | }; | |
454 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
455 | ||
456 | static struct pci_driver driver = { | |
457 | .name = "W82C105_IDE", | |
458 | .id_table = sl82c105_pci_tbl, | |
459 | .probe = sl82c105_init_one, | |
460 | }; | |
461 | ||
82ab1eec | 462 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
463 | { |
464 | return ide_pci_register_driver(&driver); | |
465 | } | |
466 | ||
467 | module_init(sl82c105_ide_init); | |
468 | ||
469 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
470 | MODULE_LICENSE("GPL"); |