[deliverable/linux.git] / drivers / ide / pci / sl82c105.c

/*
 * linux/drivers/ide/pci/sl82c105.c
 *
 * SL82C105/Winbond 553 IDE driver
 *
 * Maintainer unknown.
 *
 * Drive tuning added from Rebel.com's kernel sources
 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
 * 
 * Merge in Russell's HW workarounds, fix various problems
 * with the timing registers setup.
 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
 *
 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/dma.h>

#undef DEBUG

#ifdef DEBUG
#define DBG(arg) printk arg
#else
#define DBG(fmt,...)
#endif
/*
 * SL82C105 PCI config register 0x40 bits.
 */
#define CTRL_IDE_IRQB   (1 << 30)
#define CTRL_IDE_IRQA   (1 << 28)
#define CTRL_LEGIRQ     (1 << 11)
#define CTRL_P1F16      (1 << 5)
#define CTRL_P1EN       (1 << 4)
#define CTRL_P0F16      (1 << 1)
#define CTRL_P0EN       (1 << 0)

/*
 * Convert a PIO mode and cycle time to the required on/off times
 * for the interface.  This has protection against runaway timings.
 */
static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
{
	unsigned int cmd_on, cmd_off;
	u8 iordy = 0;

	cmd_on  = (ide_pio_timings[pio].active_time + 29) / 30;
	cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;

	if (cmd_on == 0)
		cmd_on = 1;

	if (cmd_off == 0)
		cmd_off = 1;

	if (pio > 2 || ide_dev_has_iordy(drive->id))
		iordy = 0x40;

	return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
}

/*
 * Configure the chipset for PIO mode.
 */
static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int reg			= 0x44 + drive->dn * 4;
	u16 drv_ctrl;

	DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));

	pio = ide_get_best_pio_mode(drive, pio, 5);

	drv_ctrl = get_pio_timings(drive, pio);

	/*
	 * Store the PIO timings so that we can restore them
	 * in case DMA will be turned off...
	 */
	drive->drive_data &= 0xffff0000;
	drive->drive_data |= drv_ctrl;

	if (!drive->using_dma) {
		/*
		 * If we are actually using MW DMA, then we can not
		 * reprogram the interface drive control register.
		 */
		pci_write_config_word(dev, reg,  drv_ctrl);
		pci_read_config_word (dev, reg, &drv_ctrl);
	}

	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
			  ide_xfer_verbose(pio + XFER_PIO_0),
			  ide_pio_cycle_time(drive, pio), drv_ctrl);

	return pio;
}

/*
 * Configure the drive and chipset for a new transfer speed.
 */
static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
	u16 drv_ctrl;

 	DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
	     drive->name, ide_xfer_verbose(speed)));

	switch (speed) {
	case XFER_MW_DMA_2:
	case XFER_MW_DMA_1:
	case XFER_MW_DMA_0:
		drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];

		/*
		 * Store the DMA timings so that we can actually program
		 * them when DMA will be turned on...
		 */
		drive->drive_data &= 0x0000ffff;
		drive->drive_data |= (unsigned long)drv_ctrl << 16;

		/*
		 * If we are already using DMA, we just reprogram
		 * the drive control register.
		 */
		if (drive->using_dma) {
			struct pci_dev *dev	= HWIF(drive)->pci_dev;
			int reg 		= 0x44 + drive->dn * 4;

			pci_write_config_word(dev, reg, drv_ctrl);
		}
		break;
	case XFER_PIO_5:
	case XFER_PIO_4:
	case XFER_PIO_3:
	case XFER_PIO_2:
	case XFER_PIO_1:
	case XFER_PIO_0:
		(void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
		break;
	default:
		return -1;
	}

	return ide_config_drive_speed(drive, speed);
}

/*
 * Check to see if the drive and chipset are capable of DMA mode.
 */
static int sl82c105_ide_dma_check(ide_drive_t *drive)
{
	DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));

	if (ide_tune_dma(drive))
		return 0;

	return -1;
}

/*
 * The SL82C105 holds off all IDE interrupts while in DMA mode until
 * all DMA activity is completed.  Sometimes this causes problems (eg,
 * when the drive wants to report an error condition).
 *
 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 * state machine.  We need to kick this to work around various bugs.
 */
static inline void sl82c105_reset_host(struct pci_dev *dev)
{
	u16 val;

	pci_read_config_word(dev, 0x7e, &val);
	pci_write_config_word(dev, 0x7e, val | (1 << 2));
	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
}

/*
 * If we get an IRQ timeout, it might be that the DMA state machine
 * got confused.  Fix from Todd Inglett.  Details from Winbond.
 *
 * This function is called when the IDE timer expires, the drive
 * indicates that it is READY, and we were waiting for DMA to complete.
 */
static void sl82c105_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	u8 dma_cmd;

	printk("sl82c105: lost IRQ, resetting host\n");

	/*
	 * Check the raw interrupt from the drive.
	 */
	pci_read_config_dword(dev, 0x40, &val);
	if (val & mask)
		printk("sl82c105: drive was requesting IRQ, but host lost it\n");

	/*
	 * Was DMA enabled?  If so, disable it - we're resetting the
	 * host.  The IDE layer will be handling the drive for us.
	 */
	dma_cmd = inb(hwif->dma_command);
	if (dma_cmd & 1) {
		outb(dma_cmd & ~1, hwif->dma_command);
		printk("sl82c105: DMA was enabled\n");
	}

	sl82c105_reset_host(dev);
}

/*
 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 * Winbond recommend that the DMA state machine is reset prior to
 * setting the bus master DMA enable bit.
 *
 * The generic IDE core will have disabled the BMEN bit before this
 * function is called.
 */
static void sl82c105_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;

	sl82c105_reset_host(dev);
	ide_dma_start(drive);
}

static void sl82c105_dma_timeout(ide_drive_t *drive)
{
	DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));

	sl82c105_reset_host(HWIF(drive)->pci_dev);
	ide_dma_timeout(drive);
}

static int sl82c105_ide_dma_on(ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int rc, reg 		= 0x44 + drive->dn * 4;

	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));

	rc = __ide_dma_on(drive);
	if (rc == 0) {
		pci_write_config_word(dev, reg, drive->drive_data >> 16);

		printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	}
	return rc;
}

static void sl82c105_dma_off_quietly(ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int reg 		= 0x44 + drive->dn * 4;

	DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));

	pci_write_config_word(dev, reg, drive->drive_data);

	ide_dma_off_quietly(drive);
}

/*
 * Ok, that is nasty, but we must make sure the DMA timings
 * won't be used for a PIO access. The solution here is
 * to make sure the 16 bits mode is diabled on the channel
 * when DMA is enabled, thus causing the chip to use PIO0
 * timings for those operations.
 */
static void sl82c105_selectproc(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u32 val, old, mask;

	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));

	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
	old = val = (u32)pci_get_drvdata(dev);
	if (drive->using_dma)
		val &= ~mask;
	else
		val |= mask;
	if (old != val) {
		pci_write_config_dword(dev, 0x40, val);	
		pci_set_drvdata(dev, (void *)val);
	}
}

/*
 * ATA reset will clear the 16 bits mode in the control
 * register, we need to update our cache
 */
static void sl82c105_resetproc(ide_drive_t *drive)
{
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u32 val;

	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));

	pci_read_config_dword(dev, 0x40, &val);
	pci_set_drvdata(dev, (void *)val);
}
	
/*
 * We only deal with PIO mode here - DMA mode 'using_dma' is not
 * initialised at the point that this function is called.
 */
static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
{
	DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));

	pio = sl82c105_tune_pio(drive, pio);
	(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}

/*
 * Return the revision of the Winbond bridge
 * which this function is part of.
 */
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
{
	struct pci_dev *bridge;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_get_bus_and_slot(dev->bus->number,
			       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	    	pci_dev_put(bridge);
		return -1;
	}
	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_dev_put(bridge);

	return bridge->revision;
}

/*
 * Enable the PCI device
 * 
 * --BenH: It's arch fixup code that should enable channels that
 * have not been enabled by firmware. I decided we can still enable
 * channel 0 here at least, but channel 1 has to be enabled by
 * firmware or arch code. We still set both to 16 bits mode.
 */
static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
{
	u32 val;

	DBG(("init_chipset_sl82c105()\n"));

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);
	pci_set_drvdata(dev, (void *)val);

	return dev->irq;
}

/*
 * Initialise IDE channel
 */
static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
{
	unsigned int rev;

	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));

	hwif->tuneproc		= &sl82c105_tune_drive;
	hwif->speedproc 	= &sl82c105_tune_chipset;
	hwif->selectproc	= &sl82c105_selectproc;
	hwif->resetproc 	= &sl82c105_resetproc;

	/*
	 * We support 32-bit I/O on this interface, and
	 * it doesn't have problems with interrupts.
	 */
	hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
	hwif->drives[0].unmask   = hwif->drives[1].unmask   = 1;

	/*
	 * We always autotune PIO,  this is done before DMA is checked,
	 * so there's no risk of accidentally disabling DMA
	 */
	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	rev = sl82c105_bridge_revision(hwif->pci_dev);
	if (rev <= 5) {
		/*
		 * Never ever EVER under any circumstances enable
		 * DMA when the bridge is this old.
		 */
		printk("    %s: Winbond W83C553 bridge revision %d, "
		       "BM-DMA disabled\n", hwif->name, rev);
		return;
	}

	hwif->atapi_dma  = 1;
	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check		= &sl82c105_ide_dma_check;
	hwif->ide_dma_on		= &sl82c105_ide_dma_on;
	hwif->dma_off_quietly		= &sl82c105_dma_off_quietly;
	hwif->dma_lost_irq		= &sl82c105_dma_lost_irq;
	hwif->dma_start			= &sl82c105_dma_start;
	hwif->dma_timeout		= &sl82c105_dma_timeout;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;

	if (hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;
}

static ide_pci_device_t sl82c105_chipset __devinitdata = {
	.name		= "W82C105",
	.init_chipset	= init_chipset_sl82c105,
	.init_hwif	= init_hwif_sl82c105,
	.autodma	= NOAUTODMA,
	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	.bootable	= ON_BOARD,
	.pio_mask	= ATA_PIO5,
};

static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sl82c105_chipset);
}

static struct pci_device_id sl82c105_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);

static struct pci_driver driver = {
	.name		= "W82C105_IDE",
	.id_table	= sl82c105_pci_tbl,
	.probe		= sl82c105_init_one,
};

static int __init sl82c105_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sl82c105_ide_init);

MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/sl82c105.c
	3	*
	4	* SL82C105/Winbond 553 IDE driver
	5	*
	6	* Maintainer unknown.
	7	*
	8	* Drive tuning added from Rebel.com's kernel sources
	9	* -- Russell King (15/11/98) linux@arm.linux.org.uk
	10	*
	11	* Merge in Russell's HW workarounds, fix various problems
	12	* with the timing registers setup.
	13	* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
e93df705 SS	14	*
e93df705 SS	15	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	16	*/
1da177e4 LT	17
1da177e4 LT	18	#include <linux/types.h>
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/timer.h>
	22	#include <linux/mm.h>
	23	#include <linux/ioport.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/pci.h>
	28	#include <linux/ide.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/dma.h>
	32
	33	#undef DEBUG
	34
	35	#ifdef DEBUG
	36	#define DBG(arg) printk arg
	37	#else
	38	#define DBG(fmt,...)
	39	#endif
	40	/*
	41	* SL82C105 PCI config register 0x40 bits.
	42	*/
	43	#define CTRL_IDE_IRQB (1 << 30)
	44	#define CTRL_IDE_IRQA (1 << 28)
	45	#define CTRL_LEGIRQ (1 << 11)
	46	#define CTRL_P1F16 (1 << 5)
	47	#define CTRL_P1EN (1 << 4)
	48	#define CTRL_P0F16 (1 << 1)
	49	#define CTRL_P0EN (1 << 0)
	50
	51	/*
e93df705 SS	52	* Convert a PIO mode and cycle time to the required on/off times
e93df705 SS	53	* for the interface. This has protection against runaway timings.
1da177e4	54	*/
7dd00083	55	static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
1da177e4	56	{
e93df705	57	unsigned int cmd_on, cmd_off;
2229833c	58	u8 iordy = 0;
1da177e4	59
7dd00083 BZ	60	cmd_on = (ide_pio_timings[pio].active_time + 29) / 30;
7dd00083 BZ	61	cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
1da177e4	62
1da177e4 LT	63	if (cmd_on == 0)
	64	cmd_on = 1;
	65
1da177e4 LT	66	if (cmd_off == 0)
	67	cmd_off = 1;
	68
7dd00083	69	if (pio > 2 \|\| ide_dev_has_iordy(drive->id))
2229833c BZ	70	iordy = 0x40;
	71
	72	return (cmd_on - 1) << 8 \| (cmd_off - 1) \| iordy;
1da177e4 LT	73	}
	74
	75	/*
e93df705	76	* Configure the chipset for PIO mode.
1da177e4	77	*/
e93df705	78	static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
1da177e4	79	{
e93df705 SS	80	struct pci_dev *dev = HWIF(drive)->pci_dev;
e93df705 SS	81	int reg = 0x44 + drive->dn * 4;
e93df705	82	u16 drv_ctrl;
1da177e4	83
e93df705	84	DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
1da177e4	85
2134758d	86	pio = ide_get_best_pio_mode(drive, pio, 5);
1da177e4	87
7dd00083	88	drv_ctrl = get_pio_timings(drive, pio);
46cedc9b SS	89
	90	/*
	91	* Store the PIO timings so that we can restore them
	92	* in case DMA will be turned off...
	93	*/
	94	drive->drive_data &= 0xffff0000;
	95	drive->drive_data \|= drv_ctrl;
1da177e4	96
e93df705	97	if (!drive->using_dma) {
1da177e4 LT	98	/*
	99	* If we are actually using MW DMA, then we can not
	100	* reprogram the interface drive control register.
	101	*/
e93df705 SS	102	pci_write_config_word(dev, reg, drv_ctrl);
e93df705 SS	103	pci_read_config_word (dev, reg, &drv_ctrl);
1da177e4	104	}
e93df705 SS	105
e93df705 SS	106	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
7dd00083 BZ	107	ide_xfer_verbose(pio + XFER_PIO_0),
7dd00083 BZ	108	ide_pio_cycle_time(drive, pio), drv_ctrl);
e93df705 SS	109
e93df705 SS	110	return pio;
1da177e4 LT	111	}
1da177e4 LT	112
46cedc9b SS	113	/*
	114	* Configure the drive and chipset for a new transfer speed.
	115	*/
f212ff28	116	static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
46cedc9b SS	117	{
	118	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
	119	u16 drv_ctrl;
	120
	121	DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
	122	drive->name, ide_xfer_verbose(speed)));
	123
46cedc9b SS	124	switch (speed) {
	125	case XFER_MW_DMA_2:
	126	case XFER_MW_DMA_1:
	127	case XFER_MW_DMA_0:
	128	drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
	129
	130	/*
	131	* Store the DMA timings so that we can actually program
	132	* them when DMA will be turned on...
	133	*/
	134	drive->drive_data &= 0x0000ffff;
	135	drive->drive_data \|= (unsigned long)drv_ctrl << 16;
	136
	137	/*
	138	* If we are already using DMA, we just reprogram
	139	* the drive control register.
	140	*/
	141	if (drive->using_dma) {
	142	struct pci_dev *dev = HWIF(drive)->pci_dev;
	143	int reg = 0x44 + drive->dn * 4;
	144
	145	pci_write_config_word(dev, reg, drv_ctrl);
	146	}
	147	break;
	148	case XFER_PIO_5:
	149	case XFER_PIO_4:
	150	case XFER_PIO_3:
	151	case XFER_PIO_2:
	152	case XFER_PIO_1:
	153	case XFER_PIO_0:
	154	(void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
	155	break;
	156	default:
	157	return -1;
	158	}
	159
	160	return ide_config_drive_speed(drive, speed);
	161	}
	162
1da177e4	163	/*
688a87d1	164	* Check to see if the drive and chipset are capable of DMA mode.
1da177e4	165	*/
688a87d1	166	static int sl82c105_ide_dma_check(ide_drive_t *drive)
1da177e4	167	{
688a87d1	168	DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
1da177e4	169
4728d546	170	if (ide_tune_dma(drive))
688a87d1	171	return 0;
1da177e4	172
3608b5d7	173	return -1;
1da177e4 LT	174	}
	175
	176	/*
	177	* The SL82C105 holds off all IDE interrupts while in DMA mode until
	178	* all DMA activity is completed. Sometimes this causes problems (eg,
	179	* when the drive wants to report an error condition).
	180	*
	181	* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
	182	* state machine. We need to kick this to work around various bugs.
	183	*/
	184	static inline void sl82c105_reset_host(struct pci_dev *dev)
	185	{
	186	u16 val;
	187
	188	pci_read_config_word(dev, 0x7e, &val);
	189	pci_write_config_word(dev, 0x7e, val \| (1 << 2));
	190	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
	191	}
	192
	193	/*
	194	* If we get an IRQ timeout, it might be that the DMA state machine
	195	* got confused. Fix from Todd Inglett. Details from Winbond.
	196	*
	197	* This function is called when the IDE timer expires, the drive
	198	* indicates that it is READY, and we were waiting for DMA to complete.
	199	*/
841d2a9b	200	static void sl82c105_dma_lost_irq(ide_drive_t *drive)
1da177e4	201	{
688a87d1 SS	202	ide_hwif_t *hwif = HWIF(drive);
	203	struct pci_dev *dev = hwif->pci_dev;
	204	u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	205	u8 dma_cmd;
1da177e4	206
688a87d1	207	printk("sl82c105: lost IRQ, resetting host\n");
1da177e4 LT	208
	209	/*
	210	* Check the raw interrupt from the drive.
	211	*/
	212	pci_read_config_dword(dev, 0x40, &val);
	213	if (val & mask)
	214	printk("sl82c105: drive was requesting IRQ, but host lost it\n");
	215
	216	/*
	217	* Was DMA enabled? If so, disable it - we're resetting the
	218	* host. The IDE layer will be handling the drive for us.
	219	*/
688a87d1 SS	220	dma_cmd = inb(hwif->dma_command);
	221	if (dma_cmd & 1) {
	222	outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 LT	223	printk("sl82c105: DMA was enabled\n");
	224	}
	225
	226	sl82c105_reset_host(dev);
1da177e4 LT	227	}
	228
	229	/*
	230	* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
	231	* Winbond recommend that the DMA state machine is reset prior to
	232	* setting the bus master DMA enable bit.
	233	*
	234	* The generic IDE core will have disabled the BMEN bit before this
	235	* function is called.
	236	*/
688a87d1	237	static void sl82c105_dma_start(ide_drive_t *drive)
1da177e4	238	{
688a87d1 SS	239	ide_hwif_t *hwif = HWIF(drive);
688a87d1 SS	240	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	241
	242	sl82c105_reset_host(dev);
	243	ide_dma_start(drive);
	244	}
	245
c283f5db	246	static void sl82c105_dma_timeout(ide_drive_t *drive)
1da177e4	247	{
c283f5db	248	DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
1da177e4	249
c283f5db SS	250	sl82c105_reset_host(HWIF(drive)->pci_dev);
c283f5db SS	251	ide_dma_timeout(drive);
1da177e4 LT	252	}
1da177e4 LT	253
688a87d1	254	static int sl82c105_ide_dma_on(ide_drive_t *drive)
1da177e4	255	{
688a87d1 SS	256	struct pci_dev *dev = HWIF(drive)->pci_dev;
	257	int rc, reg = 0x44 + drive->dn * 4;
	258
1da177e4 LT	259	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
1da177e4 LT	260
688a87d1 SS	261	rc = __ide_dma_on(drive);
688a87d1 SS	262	if (rc == 0) {
46cedc9b	263	pci_write_config_word(dev, reg, drive->drive_data >> 16);
688a87d1 SS	264
	265	printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	266	}
	267	return rc;
1da177e4 LT	268	}
1da177e4 LT	269
7469aaf6	270	static void sl82c105_dma_off_quietly(ide_drive_t *drive)
1da177e4	271	{
e93df705 SS	272	struct pci_dev *dev = HWIF(drive)->pci_dev;
e93df705 SS	273	int reg = 0x44 + drive->dn * 4;
1da177e4	274
7469aaf6 BZ	275	DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
7469aaf6 BZ	276
e93df705 SS	277	pci_write_config_word(dev, reg, drive->drive_data);
e93df705 SS	278
7469aaf6	279	ide_dma_off_quietly(drive);
1da177e4 LT	280	}
	281
	282	/*
	283	* Ok, that is nasty, but we must make sure the DMA timings
	284	* won't be used for a PIO access. The solution here is
	285	* to make sure the 16 bits mode is diabled on the channel
	286	* when DMA is enabled, thus causing the chip to use PIO0
	287	* timings for those operations.
	288	*/
	289	static void sl82c105_selectproc(ide_drive_t *drive)
	290	{
688a87d1 SS	291	ide_hwif_t *hwif = HWIF(drive);
688a87d1 SS	292	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	293	u32 val, old, mask;
	294
	295	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
	296
	297	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
dd607d23	298	old = val = (u32)pci_get_drvdata(dev);
1da177e4 LT	299	if (drive->using_dma)
	300	val &= ~mask;
	301	else
	302	val \|= mask;
	303	if (old != val) {
	304	pci_write_config_dword(dev, 0x40, val);
dd607d23	305	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	306	}
	307	}
	308
	309	/*
	310	* ATA reset will clear the 16 bits mode in the control
	311	* register, we need to update our cache
	312	*/
	313	static void sl82c105_resetproc(ide_drive_t *drive)
	314	{
dd607d23	315	struct pci_dev *dev = HWIF(drive)->pci_dev;
1da177e4 LT	316	u32 val;
	317
	318	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
	319
	320	pci_read_config_dword(dev, 0x40, &val);
dd607d23	321	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	322	}
	323
	324	/*
	325	* We only deal with PIO mode here - DMA mode 'using_dma' is not
	326	* initialised at the point that this function is called.
	327	*/
e93df705	328	static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4	329	{
e93df705	330	DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
1da177e4	331
e93df705 SS	332	pio = sl82c105_tune_pio(drive, pio);
e93df705 SS	333	(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4 LT	334	}
	335
	336	/*
	337	* Return the revision of the Winbond bridge
	338	* which this function is part of.
	339	*/
	340	static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
	341	{
	342	struct pci_dev *bridge;
1da177e4 LT	343
	344	/*
	345	* The bridge should be part of the same device, but function 0.
	346	*/
640b31bf	347	bridge = pci_get_bus_and_slot(dev->bus->number,
1da177e4 LT	348	PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	349	if (!bridge)
	350	return -1;
	351
	352	/*
	353	* Make sure it is a Winbond 553 and is an ISA bridge.
	354	*/
	355	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	356	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
640b31bf AC	357	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
640b31bf AC	358	pci_dev_put(bridge);
1da177e4	359	return -1;
640b31bf	360	}
1da177e4 LT	361	/*
	362	* We need to find function 0's revision, not function 1
	363	*/
640b31bf	364	pci_dev_put(bridge);
1da177e4	365
44c10138	366	return bridge->revision;
1da177e4 LT	367	}
	368
	369	/*
	370	* Enable the PCI device
	371	*
	372	* --BenH: It's arch fixup code that should enable channels that
	373	* have not been enabled by firmware. I decided we can still enable
	374	* channel 0 here at least, but channel 1 has to be enabled by
	375	* firmware or arch code. We still set both to 16 bits mode.
	376	*/
34a62246	377	static unsigned int __devinit init_chipset_sl82c105(struct pci_dev dev, const char msg)
1da177e4 LT	378	{
	379	u32 val;
	380
	381	DBG(("init_chipset_sl82c105()\n"));
	382
	383	pci_read_config_dword(dev, 0x40, &val);
	384	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	385	pci_write_config_dword(dev, 0x40, val);
dd607d23	386	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	387
	388	return dev->irq;
	389	}
	390
1da177e4	391	/*
688a87d1	392	* Initialise IDE channel
1da177e4	393	*/
34a62246	394	static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
1da177e4	395	{
9648f552	396	unsigned int rev;
dd607d23	397
1da177e4 LT	398	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
1da177e4 LT	399
e93df705	400	hwif->tuneproc = &sl82c105_tune_drive;
46cedc9b	401	hwif->speedproc = &sl82c105_tune_chipset;
e93df705 SS	402	hwif->selectproc = &sl82c105_selectproc;
	403	hwif->resetproc = &sl82c105_resetproc;
	404
	405	/*
	406	* We support 32-bit I/O on this interface, and
	407	* it doesn't have problems with interrupts.
	408	*/
	409	hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
	410	hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
dd607d23 SS	411
dd607d23 SS	412	/*
dd607d23 SS	413	* We always autotune PIO, this is done before DMA is checked,
	414	* so there's no risk of accidentally disabling DMA
	415	*/
e93df705	416	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4	417
1da177e4 LT	418	if (!hwif->dma_base)
	419	return;
	420
9648f552 RK	421	rev = sl82c105_bridge_revision(hwif->pci_dev);
	422	if (rev <= 5) {
	423	/*
	424	* Never ever EVER under any circumstances enable
	425	* DMA when the bridge is this old.
	426	*/
688a87d1 SS	427	printk(" %s: Winbond W83C553 bridge revision %d, "
	428	"BM-DMA disabled\n", hwif->name, rev);
	429	return;
9648f552	430	}
688a87d1 SS	431
688a87d1 SS	432	hwif->atapi_dma = 1;
46cedc9b	433	hwif->mwdma_mask = 0x07;
688a87d1 SS	434
	435	hwif->ide_dma_check = &sl82c105_ide_dma_check;
	436	hwif->ide_dma_on = &sl82c105_ide_dma_on;
	437	hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
841d2a9b	438	hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
688a87d1	439	hwif->dma_start = &sl82c105_dma_start;
c283f5db	440	hwif->dma_timeout = &sl82c105_dma_timeout;
688a87d1 SS	441
	442	if (!noautodma)
	443	hwif->autodma = 1;
	444	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
	445
	446	if (hwif->mate)
	447	hwif->serialized = hwif->mate->serialized = 1;
1da177e4 LT	448	}
	449
	450	static ide_pci_device_t sl82c105_chipset __devinitdata = {
	451	.name = "W82C105",
	452	.init_chipset = init_chipset_sl82c105,
	453	.init_hwif = init_hwif_sl82c105,
1da177e4 LT	454	.autodma = NOAUTODMA,
	455	.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	456	.bootable = ON_BOARD,
4099d143	457	.pio_mask = ATA_PIO5,
1da177e4 LT	458	};
	459
	460	static int __devinit sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
	461	{
	462	return ide_setup_pci_device(dev, &sl82c105_chipset);
	463	}
	464
	465	static struct pci_device_id sl82c105_pci_tbl[] = {
f201f504	466	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
1da177e4 LT	467	{ 0, },
	468	};
	469	MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
	470
	471	static struct pci_driver driver = {
	472	.name = "W82C105_IDE",
	473	.id_table = sl82c105_pci_tbl,
	474	.probe = sl82c105_init_one,
	475	};
	476
82ab1eec	477	static int __init sl82c105_ide_init(void)
1da177e4 LT	478	{
	479	return ide_pci_register_driver(&driver);
	480	}
	481
	482	module_init(sl82c105_ide_init);
	483
	484	MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
	485	MODULE_LICENSE("GPL");