[deliverable/linux.git] / drivers / ide / pci / slc90e66.c

/*
 *  linux/drivers/ide/pci/slc90e66.c	Version 0.17	Aug 2, 2007
 *
 *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
 * but this keeps the ISA-Bridge and slots alive.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
 	int control = 0;
				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	spin_lock_irqsave(&ide_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&ide_lock, flags);
}

static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int sitre = 0, a_speed	= 7 << (drive->dn * 4);
	int u_speed = 0, u_flag = 1 << drive->dn;
	u16			reg4042, reg44, reg48, reg4a;
	u8			pio;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_word(dev, 0x44, &reg44);
	pci_read_config_word(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);

	switch(speed) {
		case XFER_UDMA_4:	u_speed = 4 << (drive->dn * 4); break;
		case XFER_UDMA_3:	u_speed = 3 << (drive->dn * 4); break;
		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_SW_DMA_2:	break;
		default:		return;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_word(dev, 0x48, reg48|u_flag);
		/* FIXME: (reg4a & a_speed) ? */
		if ((reg4a & u_speed) != u_speed) {
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
			pci_read_config_word(dev, 0x4a, &reg4a);
			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
		}

		pio = 4;
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };

		if (reg48 & u_flag)
			pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);

		if (speed >= XFER_MW_DMA_0)
			pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
		else
			pio = 2; /* only SWDMA2 is allowed */
	}

	slc90e66_set_pio_mode(drive, pio);
}

static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		ide_set_max_pio(drive);

	return -1;
}

static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
{
	u8 reg47 = 0;
	u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */

	hwif->autodma = 0;

	if (!hwif->irq)
		hwif->irq = hwif->channel ? 15 : 14;

	hwif->set_pio_mode = &slc90e66_set_pio_mode;
	hwif->set_dma_mode = &slc90e66_set_dma_mode;

	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x1f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		/* bit[0(1)]: 0:80, 1:40 */
		hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;

	hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t slc90e66_chipset __devinitdata = {
	.name		= "SLC90E66",
	.init_hwif	= init_hwif_slc90e66,
	.autodma	= AUTODMA,
	.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
	.bootable	= ON_BOARD,
	.pio_mask	= ATA_PIO4,
};

static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &slc90e66_chipset);
}

static struct pci_device_id slc90e66_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);

static struct pci_driver driver = {
	.name		= "SLC90e66_IDE",
	.id_table	= slc90e66_pci_tbl,
	.probe		= slc90e66_init_one,
};

static int __init slc90e66_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(slc90e66_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
a7b888b2	2	* linux/drivers/ide/pci/slc90e66.c Version 0.17 Aug 2, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
07af4276	5	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4	6	*
44854add	7	* This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
1da177e4 LT	8	* but this keeps the ISA-Bridge and slots alive.
	9	*
	10	*/
	11
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/ioport.h>
	16	#include <linux/pci.h>
	17	#include <linux/hdreg.h>
	18	#include <linux/ide.h>
	19	#include <linux/delay.h>
	20	#include <linux/init.h>
	21
	22	#include <asm/io.h>
	23
88b2b32b	24	static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	25	{
	26	ide_hwif_t *hwif = HWIF(drive);
	27	struct pci_dev *dev = hwif->pci_dev;
24e6458d	28	int is_slave = drive->dn & 1;
1da177e4 LT	29	int master_port = hwif->channel ? 0x42 : 0x40;
	30	int slave_port = 0x44;
	31	unsigned long flags;
	32	u16 master_data;
	33	u8 slave_data;
24e6458d SS	34	int control = 0;
24e6458d SS	35	/* ISP RTC */
f201f504	36	static const u8 timings[][2]= {
24e6458d SS	37	{ 0, 0 },
	38	{ 0, 0 },
	39	{ 1, 0 },
	40	{ 2, 1 },
	41	{ 2, 3 }, };
1da177e4	42
1da177e4 LT	43	spin_lock_irqsave(&ide_lock, flags);
1da177e4 LT	44	pci_read_config_word(dev, master_port, &master_data);
24e6458d SS	45
	46	if (pio > 1)
	47	control \|= 1; /* Programmable timing on */
	48	if (drive->media == ide_disk)
	49	control \|= 4; /* Prefetch, post write */
	50	if (pio > 2)
	51	control \|= 2; /* IORDY */
1da177e4	52	if (is_slave) {
24e6458d SS	53	master_data \|= 0x4000;
	54	master_data &= ~0x0070;
	55	if (pio > 1) {
07af4276 SS	56	/* Set PPE, IE and TIME */
07af4276 SS	57	master_data \|= control << 4;
24e6458d	58	}
1da177e4	59	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	60	slave_data &= hwif->channel ? 0x0f : 0xf0;
	61	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	62	(hwif->channel ? 4 : 0);
1da177e4	63	} else {
24e6458d SS	64	master_data &= ~0x3307;
24e6458d SS	65	if (pio > 1) {
1da177e4	66	/* enable PPE, IE and TIME */
07af4276	67	master_data \|= control;
24e6458d	68	}
07af4276	69	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	70	}
	71	pci_write_config_word(dev, master_port, master_data);
	72	if (is_slave)
	73	pci_write_config_byte(dev, slave_port, slave_data);
	74	spin_unlock_irqrestore(&ide_lock, flags);
	75	}
	76
88b2b32b	77	static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	78	{
	79	ide_hwif_t *hwif = HWIF(drive);
	80	struct pci_dev *dev = hwif->pci_dev;
	81	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	82	int sitre = 0, a_speed = 7 << (drive->dn * 4);
	83	int u_speed = 0, u_flag = 1 << drive->dn;
	84	u16 reg4042, reg44, reg48, reg4a;
8c91abf8	85	u8 pio;
1da177e4 LT	86
	87	pci_read_config_word(dev, maslave, &reg4042);
	88	sitre = (reg4042 & 0x4000) ? 1 : 0;
	89	pci_read_config_word(dev, 0x44, &reg44);
	90	pci_read_config_word(dev, 0x48, &reg48);
	91	pci_read_config_word(dev, 0x4a, &reg4a);
	92
	93	switch(speed) {
1da177e4 LT	94	case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
	95	case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
	96	case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
	97	case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
	98	case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
	99	case XFER_MW_DMA_2:
	100	case XFER_MW_DMA_1:
	101	case XFER_SW_DMA_2: break;
88b2b32b	102	default: return;
1da177e4 LT	103	}
	104
	105	if (speed >= XFER_UDMA_0) {
	106	if (!(reg48 & u_flag))
	107	pci_write_config_word(dev, 0x48, reg48\|u_flag);
	108	/* FIXME: (reg4a & a_speed) ? */
	109	if ((reg4a & u_speed) != u_speed) {
	110	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	111	pci_read_config_word(dev, 0x4a, &reg4a);
	112	pci_write_config_word(dev, 0x4a, reg4a\|u_speed);
	113	}
8c91abf8 BZ	114
8c91abf8 BZ	115	pio = 4;
1da177e4	116	} else {
8c91abf8 BZ	117	const u8 mwdma_to_pio[] = { 0, 3, 4 };
8c91abf8 BZ	118
1da177e4 LT	119	if (reg48 & u_flag)
	120	pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
	121	if (reg4a & a_speed)
	122	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
8c91abf8 BZ	123
	124	if (speed >= XFER_MW_DMA_0)
	125	pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
	126	else
	127	pio = 2; /* only SWDMA2 is allowed */
1da177e4 LT	128	}
1da177e4 LT	129
8c91abf8	130	slc90e66_set_pio_mode(drive, pio);
1da177e4 LT	131	}
1da177e4 LT	132
1da177e4 LT	133	static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
1da177e4 LT	134	{
1da177e4 LT	135	drive->init_speed = 0;
1da177e4 LT	136
29e744d0	137	if (ide_tune_dma(drive))
3608b5d7	138	return 0;
1da177e4	139
d8f4469d	140	if (ide_use_fast_pio(drive))
26bcb879	141	ide_set_max_pio(drive);
d8f4469d	142
3608b5d7	143	return -1;
1da177e4	144	}
1da177e4	145
97319630	146	static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
1da177e4 LT	147	{
	148	u8 reg47 = 0;
	149	u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
	150
	151	hwif->autodma = 0;
	152
	153	if (!hwif->irq)
	154	hwif->irq = hwif->channel ? 15 : 14;
	155
26bcb879	156	hwif->set_pio_mode = &slc90e66_set_pio_mode;
88b2b32b	157	hwif->set_dma_mode = &slc90e66_set_dma_mode;
1da177e4 LT	158
	159	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
	160
a7b888b2 BZ	161	hwif->drives[0].autotune = 1;
	162	hwif->drives[1].autotune = 1;
	163
	164	if (hwif->dma_base == 0)
1da177e4	165	return;
1da177e4 LT	166
	167	hwif->atapi_dma = 1;
	168	hwif->ultra_mask = 0x1f;
24e6458d SS	169	hwif->mwdma_mask = 0x06;
24e6458d SS	170	hwif->swdma_mask = 0x04;
1da177e4	171
49521f97	172	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1da177e4	173	/* bit[0(1)]: 0:80, 1:40 */
49521f97	174	hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	175
1da177e4 LT	176	hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
24e6458d	177
1da177e4 LT	178	if (!noautodma)
	179	hwif->autodma = 1;
	180	hwif->drives[0].autodma = hwif->autodma;
	181	hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	182	}
	183
	184	static ide_pci_device_t slc90e66_chipset __devinitdata = {
	185	.name = "SLC90E66",
	186	.init_hwif = init_hwif_slc90e66,
1da177e4 LT	187	.autodma = AUTODMA,
	188	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
	189	.bootable = ON_BOARD,
4099d143	190	.pio_mask = ATA_PIO4,
1da177e4 LT	191	};
	192
	193	static int __devinit slc90e66_init_one(struct pci_dev dev, const struct pci_device_id id)
	194	{
	195	return ide_setup_pci_device(dev, &slc90e66_chipset);
	196	}
	197
	198	static struct pci_device_id slc90e66_pci_tbl[] = {
f201f504	199	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
1da177e4 LT	200	{ 0, },
	201	};
	202	MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
	203
	204	static struct pci_driver driver = {
	205	.name = "SLC90e66_IDE",
	206	.id_table = slc90e66_pci_tbl,
	207	.probe = slc90e66_init_one,
	208	};
	209
82ab1eec	210	static int __init slc90e66_ide_init(void)
1da177e4 LT	211	{
	212	return ide_pci_register_driver(&driver);
	213	}
	214
	215	module_init(slc90e66_ide_init);
	216
	217	MODULE_AUTHOR("Andre Hedrick");
	218	MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
	219	MODULE_LICENSE("GPL");