[deliverable/linux.git] / drivers / ide / pci / slc90e66.c

/*
 *  linux/drivers/ide/pci/slc90e66.c	Version 0.17	Aug 2, 2007
 *
 *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
 * but this keeps the ISA-Bridge and slots alive.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
	switch(xfer_rate) {
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:
			return 4;
		case XFER_MW_DMA_1:
			return 3;
		case XFER_SW_DMA_2:
			return 2;
		case XFER_MW_DMA_0:
		case XFER_SW_DMA_1:
		case XFER_SW_DMA_0:
		default:
			return 0;
	}
}

static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
 	int control = 0;
				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	spin_lock_irqsave(&ide_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&ide_lock, flags);
}

static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int sitre = 0, a_speed	= 7 << (drive->dn * 4);
	int u_speed = 0, u_flag = 1 << drive->dn;
	u16			reg4042, reg44, reg48, reg4a;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_word(dev, 0x44, &reg44);
	pci_read_config_word(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);

	switch(speed) {
		case XFER_UDMA_4:	u_speed = 4 << (drive->dn * 4); break;
		case XFER_UDMA_3:	u_speed = 3 << (drive->dn * 4); break;
		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_SW_DMA_2:	break;
		default:		return;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_word(dev, 0x48, reg48|u_flag);
		/* FIXME: (reg4a & a_speed) ? */
		if ((reg4a & u_speed) != u_speed) {
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
			pci_read_config_word(dev, 0x4a, &reg4a);
			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
		}
	} else {
		if (reg48 & u_flag)
			pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	}

	slc90e66_set_pio_mode(drive, slc90e66_dma_2_pio(speed));
}

static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		ide_set_max_pio(drive);

	return -1;
}

static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
{
	u8 reg47 = 0;
	u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */

	hwif->autodma = 0;

	if (!hwif->irq)
		hwif->irq = hwif->channel ? 15 : 14;

	hwif->set_pio_mode = &slc90e66_set_pio_mode;
	hwif->set_dma_mode = &slc90e66_set_dma_mode;

	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x1f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		/* bit[0(1)]: 0:80, 1:40 */
		hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;

	hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t slc90e66_chipset __devinitdata = {
	.name		= "SLC90E66",
	.init_hwif	= init_hwif_slc90e66,
	.autodma	= AUTODMA,
	.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
	.bootable	= ON_BOARD,
	.pio_mask	= ATA_PIO4,
};

static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &slc90e66_chipset);
}

static struct pci_device_id slc90e66_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);

static struct pci_driver driver = {
	.name		= "SLC90e66_IDE",
	.id_table	= slc90e66_pci_tbl,
	.probe		= slc90e66_init_one,
};

static int __init slc90e66_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(slc90e66_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
a7b888b2	2	* linux/drivers/ide/pci/slc90e66.c Version 0.17 Aug 2, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
07af4276	5	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4	6	*
44854add	7	* This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
1da177e4 LT	8	* but this keeps the ISA-Bridge and slots alive.
	9	*
	10	*/
	11
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/ioport.h>
	16	#include <linux/pci.h>
	17	#include <linux/hdreg.h>
	18	#include <linux/ide.h>
	19	#include <linux/delay.h>
	20	#include <linux/init.h>
	21
	22	#include <asm/io.h>
	23
1da177e4 LT	24	static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
	25	switch(xfer_rate) {
	26	case XFER_UDMA_4:
	27	case XFER_UDMA_3:
	28	case XFER_UDMA_2:
	29	case XFER_UDMA_1:
	30	case XFER_UDMA_0:
	31	case XFER_MW_DMA_2:
1da177e4 LT	32	return 4;
1da177e4 LT	33	case XFER_MW_DMA_1:
1da177e4 LT	34	return 3;
1da177e4 LT	35	case XFER_SW_DMA_2:
1da177e4 LT	36	return 2;
	37	case XFER_MW_DMA_0:
	38	case XFER_SW_DMA_1:
	39	case XFER_SW_DMA_0:
1da177e4 LT	40	default:
	41	return 0;
	42	}
	43	}
	44
88b2b32b	45	static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	46	{
	47	ide_hwif_t *hwif = HWIF(drive);
	48	struct pci_dev *dev = hwif->pci_dev;
24e6458d	49	int is_slave = drive->dn & 1;
1da177e4 LT	50	int master_port = hwif->channel ? 0x42 : 0x40;
	51	int slave_port = 0x44;
	52	unsigned long flags;
	53	u16 master_data;
	54	u8 slave_data;
24e6458d SS	55	int control = 0;
24e6458d SS	56	/* ISP RTC */
f201f504	57	static const u8 timings[][2]= {
24e6458d SS	58	{ 0, 0 },
	59	{ 0, 0 },
	60	{ 1, 0 },
	61	{ 2, 1 },
	62	{ 2, 3 }, };
1da177e4	63
1da177e4 LT	64	spin_lock_irqsave(&ide_lock, flags);
1da177e4 LT	65	pci_read_config_word(dev, master_port, &master_data);
24e6458d SS	66
	67	if (pio > 1)
	68	control \|= 1; /* Programmable timing on */
	69	if (drive->media == ide_disk)
	70	control \|= 4; /* Prefetch, post write */
	71	if (pio > 2)
	72	control \|= 2; /* IORDY */
1da177e4	73	if (is_slave) {
24e6458d SS	74	master_data \|= 0x4000;
	75	master_data &= ~0x0070;
	76	if (pio > 1) {
07af4276 SS	77	/* Set PPE, IE and TIME */
07af4276 SS	78	master_data \|= control << 4;
24e6458d	79	}
1da177e4	80	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	81	slave_data &= hwif->channel ? 0x0f : 0xf0;
	82	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	83	(hwif->channel ? 4 : 0);
1da177e4	84	} else {
24e6458d SS	85	master_data &= ~0x3307;
24e6458d SS	86	if (pio > 1) {
1da177e4	87	/* enable PPE, IE and TIME */
07af4276	88	master_data \|= control;
24e6458d	89	}
07af4276	90	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	91	}
	92	pci_write_config_word(dev, master_port, master_data);
	93	if (is_slave)
	94	pci_write_config_byte(dev, slave_port, slave_data);
	95	spin_unlock_irqrestore(&ide_lock, flags);
	96	}
	97
88b2b32b	98	static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	99	{
	100	ide_hwif_t *hwif = HWIF(drive);
	101	struct pci_dev *dev = hwif->pci_dev;
	102	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	103	int sitre = 0, a_speed = 7 << (drive->dn * 4);
	104	int u_speed = 0, u_flag = 1 << drive->dn;
	105	u16 reg4042, reg44, reg48, reg4a;
	106
	107	pci_read_config_word(dev, maslave, &reg4042);
	108	sitre = (reg4042 & 0x4000) ? 1 : 0;
	109	pci_read_config_word(dev, 0x44, &reg44);
	110	pci_read_config_word(dev, 0x48, &reg48);
	111	pci_read_config_word(dev, 0x4a, &reg4a);
	112
	113	switch(speed) {
1da177e4 LT	114	case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
	115	case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
	116	case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
	117	case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
	118	case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
	119	case XFER_MW_DMA_2:
	120	case XFER_MW_DMA_1:
	121	case XFER_SW_DMA_2: break;
88b2b32b	122	default: return;
1da177e4 LT	123	}
	124
	125	if (speed >= XFER_UDMA_0) {
	126	if (!(reg48 & u_flag))
	127	pci_write_config_word(dev, 0x48, reg48\|u_flag);
	128	/* FIXME: (reg4a & a_speed) ? */
	129	if ((reg4a & u_speed) != u_speed) {
	130	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	131	pci_read_config_word(dev, 0x4a, &reg4a);
	132	pci_write_config_word(dev, 0x4a, reg4a\|u_speed);
	133	}
	134	} else {
	135	if (reg48 & u_flag)
	136	pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
	137	if (reg4a & a_speed)
	138	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	139	}
	140
88b2b32b	141	slc90e66_set_pio_mode(drive, slc90e66_dma_2_pio(speed));
1da177e4 LT	142	}
1da177e4 LT	143
1da177e4 LT	144	static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
1da177e4 LT	145	{
1da177e4 LT	146	drive->init_speed = 0;
1da177e4 LT	147
29e744d0	148	if (ide_tune_dma(drive))
3608b5d7	149	return 0;
1da177e4	150
d8f4469d	151	if (ide_use_fast_pio(drive))
26bcb879	152	ide_set_max_pio(drive);
d8f4469d	153
3608b5d7	154	return -1;
1da177e4	155	}
1da177e4	156
97319630	157	static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
1da177e4 LT	158	{
	159	u8 reg47 = 0;
	160	u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
	161
	162	hwif->autodma = 0;
	163
	164	if (!hwif->irq)
	165	hwif->irq = hwif->channel ? 15 : 14;
	166
26bcb879	167	hwif->set_pio_mode = &slc90e66_set_pio_mode;
88b2b32b	168	hwif->set_dma_mode = &slc90e66_set_dma_mode;
1da177e4 LT	169
	170	pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
	171
a7b888b2 BZ	172	hwif->drives[0].autotune = 1;
	173	hwif->drives[1].autotune = 1;
	174
	175	if (hwif->dma_base == 0)
1da177e4	176	return;
1da177e4 LT	177
	178	hwif->atapi_dma = 1;
	179	hwif->ultra_mask = 0x1f;
24e6458d SS	180	hwif->mwdma_mask = 0x06;
24e6458d SS	181	hwif->swdma_mask = 0x04;
1da177e4	182
49521f97	183	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1da177e4	184	/* bit[0(1)]: 0:80, 1:40 */
49521f97	185	hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	186
1da177e4 LT	187	hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
24e6458d	188
1da177e4 LT	189	if (!noautodma)
	190	hwif->autodma = 1;
	191	hwif->drives[0].autodma = hwif->autodma;
	192	hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	193	}
	194
	195	static ide_pci_device_t slc90e66_chipset __devinitdata = {
	196	.name = "SLC90E66",
	197	.init_hwif = init_hwif_slc90e66,
1da177e4 LT	198	.autodma = AUTODMA,
	199	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
	200	.bootable = ON_BOARD,
4099d143	201	.pio_mask = ATA_PIO4,
1da177e4 LT	202	};
	203
	204	static int __devinit slc90e66_init_one(struct pci_dev dev, const struct pci_device_id id)
	205	{
	206	return ide_setup_pci_device(dev, &slc90e66_chipset);
	207	}
	208
	209	static struct pci_device_id slc90e66_pci_tbl[] = {
f201f504	210	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
1da177e4 LT	211	{ 0, },
	212	};
	213	MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
	214
	215	static struct pci_driver driver = {
	216	.name = "SLC90e66_IDE",
	217	.id_table = slc90e66_pci_tbl,
	218	.probe = slc90e66_init_one,
	219	};
	220
82ab1eec	221	static int __init slc90e66_ide_init(void)
1da177e4 LT	222	{
	223	return ide_pci_register_driver(&driver);
	224	}
	225
	226	module_init(slc90e66_ide_init);
	227
	228	MODULE_AUTHOR("Andre Hedrick");
	229	MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
	230	MODULE_LICENSE("GPL");