[deliverable/linux.git] / drivers / ide / pci / tc86c001.c

/*
 * drivers/ide/pci/tc86c001.c	Version 1.01	Sep 5, 2007
 *
 * Copyright (C) 2002 Toshiba Corporation
 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>

static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long scr_port	= hwif->config_data + (drive->dn ? 0x02 : 0x00);
	u16 mode, scr		= inw(scr_port);

	switch (speed) {
		case XFER_UDMA_4:	mode = 0x00c0; break;
		case XFER_UDMA_3:	mode = 0x00b0; break;
		case XFER_UDMA_2:	mode = 0x00a0; break;
		case XFER_UDMA_1:	mode = 0x0090; break;
		case XFER_UDMA_0:	mode = 0x0080; break;
		case XFER_MW_DMA_2:	mode = 0x0070; break;
		case XFER_MW_DMA_1:	mode = 0x0060; break;
		case XFER_MW_DMA_0:	mode = 0x0050; break;
		case XFER_PIO_4:	mode = 0x0400; break;
		case XFER_PIO_3:	mode = 0x0300; break;
		case XFER_PIO_2:	mode = 0x0200; break;
		case XFER_PIO_1:	mode = 0x0100; break;
		case XFER_PIO_0:
		default:		mode = 0x0000; break;
	}

	scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
	scr |= mode;
	outw(scr, scr_port);
}

static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	tc86c001_set_mode(drive, XFER_PIO_0 + pio);
}

/*
 * HACKITY HACK
 *
 * This is a workaround for the limitation 5 of the TC86C001 IDE controller:
 * if a DMA transfer terminates prematurely, the controller leaves the device's
 * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
 * set the interrupt bit in the DMA status register), thus no PCI interrupt
 * will occur until a DMA transfer has been successfully completed.
 *
 * We work around this by initiating dummy, zero-length DMA transfer on
 * a DMA timeout expiration. I found no better way to do this with the current
 * IDE core than to temporarily replace a higher level driver's timer expiry
 * handler with our own backing up to that handler in case our recovery fails.
 */
static int tc86c001_timer_expiry(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_expiry_t *expiry	= ide_get_hwifdata(hwif);
	ide_hwgroup_t *hwgroup	= HWGROUP(drive);
	u8 dma_stat		= inb(hwif->dma_status);

	/* Restore a higher level driver's expiry handler first. */
	hwgroup->expiry	= expiry;

	if ((dma_stat & 5) == 1) {	/* DMA active and no interrupt */
		unsigned long sc_base	= hwif->config_data;
		unsigned long twcr_port	= sc_base + (drive->dn ? 0x06 : 0x04);
		u8 dma_cmd		= inb(hwif->dma_command);

		printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
		       "attempting recovery...\n", drive->name);

		/* Stop DMA */
		outb(dma_cmd & ~0x01, hwif->dma_command);

		/* Setup the dummy DMA transfer */
		outw(0, sc_base + 0x0a);	/* Sector Count */
		outw(0, twcr_port);	/* Transfer Word Count 1 or 2 */

		/* Start the dummy DMA transfer */
		outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
		outb(0x01, hwif->dma_command); /* set START_STOPBM */

		/*
		 * If an interrupt was pending, it should come thru shortly.
		 * If not, a higher level driver's expiry handler should
		 * eventually cause some kind of recovery from the DMA stall.
		 */
		return WAIT_MIN_SLEEP;
	}

	/* Chain to the restored expiry handler if DMA wasn't active. */
	if (likely(expiry != NULL))
		return expiry(drive);

	/* If there was no handler, "emulate" that for ide_timer_expiry()... */
	return -1;
}

static void tc86c001_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwgroup_t *hwgroup	= HWGROUP(drive);
	unsigned long sc_base	= hwif->config_data;
	unsigned long twcr_port	= sc_base + (drive->dn ? 0x06 : 0x04);
	unsigned long nsectors	= hwgroup->rq->nr_sectors;

	/*
	 * We have to manually load the sector count and size into
	 * the appropriate system control registers for DMA to work
	 * with LBA48 and ATAPI devices...
	 */
	outw(nsectors, sc_base + 0x0a);	/* Sector Count */
	outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */

	/* Install our timeout expiry hook, saving the current handler... */
	ide_set_hwifdata(hwif, hwgroup->expiry);
	hwgroup->expiry = &tc86c001_timer_expiry;

	ide_dma_start(drive);
}

static int tc86c001_busproc(ide_drive_t *drive, int state)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long sc_base	= hwif->config_data;
	u16 scr1;

	/* System Control 1 Register bit 11 (ATA Hard Reset) read */
	scr1 = inw(sc_base + 0x00);

	switch (state) {
		case BUSSTATE_ON:
			if (!(scr1 & 0x0800))
				return 0;
			scr1 &= ~0x0800;

			hwif->drives[0].failures = hwif->drives[1].failures = 0;
			break;
		case BUSSTATE_OFF:
			if (scr1 & 0x0800)
				return 0;
			scr1 |= 0x0800;

			hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
			hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
			break;
		default:
			return -EINVAL;
	}

	/* System Control 1 Register bit 11 (ATA Hard Reset) write */
	outw(scr1, sc_base + 0x00);
	return 0;
}

static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long sc_base	= pci_resource_start(dev, 5);
	u16 scr1		= inw(sc_base + 0x00);

	/* System Control 1 Register bit 15 (Soft Reset) set */
	outw(scr1 |  0x8000, sc_base + 0x00);

	/* System Control 1 Register bit 14 (FIFO Reset) set */
	outw(scr1 |  0x4000, sc_base + 0x00);

	/* System Control 1 Register: reset clear */
	outw(scr1 & ~0xc000, sc_base + 0x00);

	/* Store the system control register base for convenience... */
	hwif->config_data = sc_base;

	hwif->set_pio_mode = &tc86c001_set_pio_mode;
	hwif->set_dma_mode = &tc86c001_set_mode;

	hwif->busproc	= &tc86c001_busproc;

	if (!hwif->dma_base)
		return;

	/*
	 * Sector Count Control Register bits 0 and 1 set:
	 * software sets Sector Count Register for master and slave device
	 */
	outw(0x0003, sc_base + 0x0c);

	/* Sector Count Register limit */
	hwif->rqsize	 = 0xffff;

	hwif->dma_start 	= &tc86c001_dma_start;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		/*
		 * System Control  1 Register bit 13 (PDIAGN):
		 * 0=80-pin cable, 1=40-pin cable
		 */
		scr1 = inw(sc_base + 0x00);
		hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	}
}

static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
							const char *name)
{
	int err = pci_request_region(dev, 5, name);

	if (err)
		printk(KERN_ERR "%s: system control regs already in use", name);
	return err;
}

static const struct ide_port_info tc86c001_chipset __devinitdata = {
	.name		= "TC86C001",
	.init_chipset	= init_chipset_tc86c001,
	.init_hwif	= init_hwif_tc86c001,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD |
			  IDE_HFLAG_ABUSE_SET_DMA_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA4,
};

static int __devinit tc86c001_init_one(struct pci_dev *dev,
				       const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &tc86c001_chipset);
}

static const struct pci_device_id tc86c001_pci_tbl[] = {
	{ PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE), 0 },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);

static struct pci_driver driver = {
	.name		= "TC86C001",
	.id_table	= tc86c001_pci_tbl,
	.probe		= tc86c001_init_one
};

static int __init tc86c001_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}
module_init(tc86c001_ide_init);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
33dced2e	1	/*
31e8a465	2	* drivers/ide/pci/tc86c001.c Version 1.01 Sep 5, 2007
33dced2e SS	3	*
	4	* Copyright (C) 2002 Toshiba Corporation
	5	* Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/pci.h>
	14	#include <linux/ide.h>
	15
88b2b32b	16	static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
33dced2e SS	17	{
	18	ide_hwif_t *hwif = HWIF(drive);
	19	unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
31e8a465	20	u16 mode, scr = inw(scr_port);
33dced2e	21
33dced2e SS	22	switch (speed) {
	23	case XFER_UDMA_4: mode = 0x00c0; break;
	24	case XFER_UDMA_3: mode = 0x00b0; break;
	25	case XFER_UDMA_2: mode = 0x00a0; break;
	26	case XFER_UDMA_1: mode = 0x0090; break;
	27	case XFER_UDMA_0: mode = 0x0080; break;
	28	case XFER_MW_DMA_2: mode = 0x0070; break;
	29	case XFER_MW_DMA_1: mode = 0x0060; break;
	30	case XFER_MW_DMA_0: mode = 0x0050; break;
	31	case XFER_PIO_4: mode = 0x0400; break;
	32	case XFER_PIO_3: mode = 0x0300; break;
	33	case XFER_PIO_2: mode = 0x0200; break;
	34	case XFER_PIO_1: mode = 0x0100; break;
	35	case XFER_PIO_0:
	36	default: mode = 0x0000; break;
	37	}
	38
	39	scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
	40	scr \|= mode;
0ecdca26	41	outw(scr, scr_port);
33dced2e SS	42	}
33dced2e SS	43
26bcb879	44	static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio)
33dced2e	45	{
88b2b32b	46	tc86c001_set_mode(drive, XFER_PIO_0 + pio);
33dced2e SS	47	}
	48
	49	/*
	50	* HACKITY HACK
	51	*
	52	* This is a workaround for the limitation 5 of the TC86C001 IDE controller:
	53	* if a DMA transfer terminates prematurely, the controller leaves the device's
	54	* interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
	55	* set the interrupt bit in the DMA status register), thus no PCI interrupt
	56	* will occur until a DMA transfer has been successfully completed.
	57	*
	58	* We work around this by initiating dummy, zero-length DMA transfer on
	59	* a DMA timeout expiration. I found no better way to do this with the current
	60	* IDE core than to temporarily replace a higher level driver's timer expiry
	61	* handler with our own backing up to that handler in case our recovery fails.
	62	*/
	63	static int tc86c001_timer_expiry(ide_drive_t *drive)
	64	{
	65	ide_hwif_t *hwif = HWIF(drive);
	66	ide_expiry_t *expiry = ide_get_hwifdata(hwif);
	67	ide_hwgroup_t *hwgroup = HWGROUP(drive);
31e8a465	68	u8 dma_stat = inb(hwif->dma_status);
33dced2e SS	69
	70	/* Restore a higher level driver's expiry handler first. */
	71	hwgroup->expiry = expiry;
	72
	73	if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */
	74	unsigned long sc_base = hwif->config_data;
	75	unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
31e8a465	76	u8 dma_cmd = inb(hwif->dma_command);
33dced2e SS	77
	78	printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
	79	"attempting recovery...\n", drive->name);
	80
	81	/* Stop DMA */
0ecdca26	82	outb(dma_cmd & ~0x01, hwif->dma_command);
33dced2e SS	83
33dced2e SS	84	/* Setup the dummy DMA transfer */
0ecdca26 BZ	85	outw(0, sc_base + 0x0a); /* Sector Count */
0ecdca26 BZ	86	outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
33dced2e SS	87
33dced2e SS	88	/* Start the dummy DMA transfer */
0ecdca26 BZ	89	outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
0ecdca26 BZ	90	outb(0x01, hwif->dma_command); /* set START_STOPBM */
33dced2e SS	91
	92	/*
	93	* If an interrupt was pending, it should come thru shortly.
	94	* If not, a higher level driver's expiry handler should
	95	* eventually cause some kind of recovery from the DMA stall.
	96	*/
	97	return WAIT_MIN_SLEEP;
	98	}
	99
	100	/* Chain to the restored expiry handler if DMA wasn't active. */
	101	if (likely(expiry != NULL))
	102	return expiry(drive);
	103
	104	/* If there was no handler, "emulate" that for ide_timer_expiry()... */
	105	return -1;
	106	}
	107
	108	static void tc86c001_dma_start(ide_drive_t *drive)
	109	{
	110	ide_hwif_t *hwif = HWIF(drive);
	111	ide_hwgroup_t *hwgroup = HWGROUP(drive);
	112	unsigned long sc_base = hwif->config_data;
	113	unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
	114	unsigned long nsectors = hwgroup->rq->nr_sectors;
	115
	116	/*
	117	* We have to manually load the sector count and size into
	118	* the appropriate system control registers for DMA to work
	119	* with LBA48 and ATAPI devices...
	120	*/
0ecdca26 BZ	121	outw(nsectors, sc_base + 0x0a); /* Sector Count */
0ecdca26 BZ	122	outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
33dced2e SS	123
	124	/* Install our timeout expiry hook, saving the current handler... */
	125	ide_set_hwifdata(hwif, hwgroup->expiry);
	126	hwgroup->expiry = &tc86c001_timer_expiry;
	127
	128	ide_dma_start(drive);
	129	}
	130
	131	static int tc86c001_busproc(ide_drive_t *drive, int state)
	132	{
	133	ide_hwif_t *hwif = HWIF(drive);
	134	unsigned long sc_base = hwif->config_data;
	135	u16 scr1;
	136
	137	/* System Control 1 Register bit 11 (ATA Hard Reset) read */
31e8a465	138	scr1 = inw(sc_base + 0x00);
33dced2e SS	139
	140	switch (state) {
	141	case BUSSTATE_ON:
	142	if (!(scr1 & 0x0800))
	143	return 0;
	144	scr1 &= ~0x0800;
	145
	146	hwif->drives[0].failures = hwif->drives[1].failures = 0;
	147	break;
	148	case BUSSTATE_OFF:
	149	if (scr1 & 0x0800)
	150	return 0;
	151	scr1 \|= 0x0800;
	152
	153	hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
	154	hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
	155	break;
	156	default:
	157	return -EINVAL;
	158	}
	159
	160	/* System Control 1 Register bit 11 (ATA Hard Reset) write */
0ecdca26	161	outw(scr1, sc_base + 0x00);
33dced2e SS	162	return 0;
	163	}
	164
e8ab7f53	165	static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
33dced2e	166	{
36501650 BZ	167	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	168	unsigned long sc_base = pci_resource_start(dev, 5);
31e8a465	169	u16 scr1 = inw(sc_base + 0x00);
33dced2e SS	170
33dced2e SS	171	/* System Control 1 Register bit 15 (Soft Reset) set */
0ecdca26	172	outw(scr1 \| 0x8000, sc_base + 0x00);
33dced2e SS	173
33dced2e SS	174	/* System Control 1 Register bit 14 (FIFO Reset) set */
0ecdca26	175	outw(scr1 \| 0x4000, sc_base + 0x00);
33dced2e SS	176
33dced2e SS	177	/* System Control 1 Register: reset clear */
0ecdca26	178	outw(scr1 & ~0xc000, sc_base + 0x00);
33dced2e SS	179
	180	/* Store the system control register base for convenience... */
	181	hwif->config_data = sc_base;
	182
26bcb879	183	hwif->set_pio_mode = &tc86c001_set_pio_mode;
88b2b32b BZ	184	hwif->set_dma_mode = &tc86c001_set_mode;
88b2b32b BZ	185
33dced2e SS	186	hwif->busproc = &tc86c001_busproc;
33dced2e SS	187
33dced2e SS	188	if (!hwif->dma_base)
	189	return;
	190
	191	/*
	192	* Sector Count Control Register bits 0 and 1 set:
	193	* software sets Sector Count Register for master and slave device
	194	*/
0ecdca26	195	outw(0x0003, sc_base + 0x0c);
33dced2e SS	196
	197	/* Sector Count Register limit */
	198	hwif->rqsize = 0xffff;
	199
33dced2e SS	200	hwif->dma_start = &tc86c001_dma_start;
33dced2e SS	201
49521f97	202	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
33dced2e SS	203	/*
	204	* System Control 1 Register bit 13 (PDIAGN):
	205	* 0=80-pin cable, 1=40-pin cable
	206	*/
31e8a465	207	scr1 = inw(sc_base + 0x00);
49521f97	208	hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
33dced2e	209	}
33dced2e SS	210	}
33dced2e SS	211
ba59c4b8 AM	212	static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
ba59c4b8 AM	213	const char *name)
33dced2e SS	214	{
	215	int err = pci_request_region(dev, 5, name);
	216
	217	if (err)
	218	printk(KERN_ERR "%s: system control regs already in use", name);
	219	return err;
	220	}
	221
85620436	222	static const struct ide_port_info tc86c001_chipset __devinitdata = {
33dced2e SS	223	.name = "TC86C001",
	224	.init_chipset = init_chipset_tc86c001,
	225	.init_hwif = init_hwif_tc86c001,
4db90a14 BZ	226	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_OFF_BOARD \|
4db90a14 BZ	227	IDE_HFLAG_ABUSE_SET_DMA_MODE,
4099d143	228	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	229	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	230	.udma_mask = ATA_UDMA4,
33dced2e SS	231	};
	232
	233	static int __devinit tc86c001_init_one(struct pci_dev *dev,
	234	const struct pci_device_id *id)
	235	{
	236	return ide_setup_pci_device(dev, &tc86c001_chipset);
	237	}
	238
9cbcc5e3 BZ	239	static const struct pci_device_id tc86c001_pci_tbl[] = {
9cbcc5e3 BZ	240	{ PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE), 0 },
33dced2e SS	241	{ 0, }
	242	};
	243	MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);
	244
	245	static struct pci_driver driver = {
	246	.name = "TC86C001",
	247	.id_table = tc86c001_pci_tbl,
	248	.probe = tc86c001_init_one
	249	};
	250
a534b68d	251	static int __init tc86c001_ide_init(void)
33dced2e SS	252	{
	253	return ide_pci_register_driver(&driver);
	254	}
	255	module_init(tc86c001_ide_init);
	256
	257	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	258	MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
	259	MODULE_LICENSE("GPL");