[deliverable/linux.git] / drivers / ide / pci / trm290.c

/*
 *  linux/drivers/ide/pci/trm290.c		Version 1.05	Dec. 30, 2007
 *
 *  Copyright (c) 1997-1998  Mark Lord
 *  Copyright (c) 2007       MontaVista Software, Inc. <source@mvista.com>
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  June 22, 2004 - get rid of check_region
 *                   - Jesper Juhl
 *
 */

/*
 * This module provides support for the bus-master IDE DMA function
 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
 * including a "Precision Instruments" board.  The TRM290 pre-dates
 * the sff-8038 standard (ide-dma.c) by a few months, and differs
 * significantly enough to warrant separate routines for some functions,
 * while re-using others from ide-dma.c.
 *
 * EXPERIMENTAL!  It works for me (a sample of one).
 *
 * Works reliably for me in DMA mode (READs only),
 * DMA WRITEs are disabled by default (see #define below);
 *
 * DMA is not enabled automatically for this chipset,
 * but can be turned on manually (with "hdparm -d1") at run time.
 *
 * I need volunteers with "spare" drives for further testing
 * and development, and maybe to help figure out the peculiarities.
 * Even knowing the registers (below), some things behave strangely.
 */

#define TRM290_NO_DMA_WRITES	/* DMA writes seem unreliable sometimes */

/*
 * TRM-290 PCI-IDE2 Bus Master Chip
 * ================================
 * The configuration registers are addressed in normal I/O port space
 * and are used as follows:
 *
 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
 *
 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
 *	bit7 must always be written as "1"
 *	bits6-2 undefined
 *	bit1 1=legacy_compatible_mode, 0=native_pci_mode
 *	bit0 1=test_mode, 0=normal(default)
 *
 * trm290_base+2 when READ: status register (byte, read-only)
 *	bits7-2 undefined
 *	bit1 channel0 busmaster interrupt status 0=none, 1=asserted
 *	bit0 channel0 interrupt status 0=none, 1=asserted
 *
 * trm290_base+3 Interrupt mask register
 *	bits7-5 undefined
 *	bit4 legacy_header: 1=present, 0=absent
 *	bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
 *	bit2 channel1 interrupt status 0=none, 1=asserted (read only)
 *	bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
 *	bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
 *
 * trm290_base+1 "CPR" Config Pointer Register (byte)
 *	bit7 1=autoincrement CPR bits 2-0 after each access of CDR
 *	bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
 *	bit5 0=enabled master burst access (default), 1=disable  (write only)
 *	bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
 *	bit3 0=primary IDE channel, 1=secondary IDE channel
 *	bits2-0 register index for accesses through CDR port
 *
 * trm290_base+0 "CDR" Config Data Register (word)
 *	two sets of seven config registers,
 *	selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
 *	each index defined below:
 *
 * Index-0 Base address register for command block (word)
 *	defaults: 0x1f0 for primary, 0x170 for secondary
 *
 * Index-1 general config register (byte)
 *	bit7 1=DMA enable, 0=DMA disable
 *	bit6 1=activate IDE_RESET, 0=no action (default)
 *	bit5 1=enable IORDY, 0=disable IORDY (default)
 *	bit4 0=16-bit data port(default), 1=8-bit (XT) data port
 *	bit3 interrupt polarity: 1=active_low, 0=active_high(default)
 *	bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
 *	bit1 bus_master_mode(?): 1=enable, 0=disable(default)
 *	bit0 enable_io_ports: 1=enable(default), 0=disable
 *
 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
 *	bits7-0 bits7-0 of readahead count
 *
 * Index-3 read-ahead config register (byte, write only)
 *	bit7 1=enable_readahead, 0=disable_readahead(default)
 *	bit6 1=clear_FIFO, 0=no_action
 *	bit5 undefined
 *	bit4 mode4 timing control: 1=enable, 0=disable(default)
 *	bit3 undefined
 *	bit2 undefined
 *	bits1-0 bits9-8 of read-ahead count
 *
 * Index-4 base address register for control block (word)
 *	defaults: 0x3f6 for primary, 0x376 for secondary
 *
 * Index-5 data port timings (shared by both drives) (byte)
 *	standard PCI "clk" (clock) counts, default value = 0xf5
 *
 *	bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
 *	bits5-3 hold time:	000=1clk, 001=2clk, 010=3clk,
 *				011=4clk, 100=5clk, 101=6clk,
 *				110=8clk, 111=12clk
 *	bits2-0 active time:	000=2clk, 001=3clk, 010=4clk,
 *				011=5clk, 100=6clk, 101=8clk,
 *				110=12clk, 111=16clk
 *
 * Index-6 command/control port timings (shared by both drives) (byte)
 *	same layout as Index-5, default value = 0xde
 *
 * Suggested CDR programming for PIO mode0 (600ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde	; secondary
 *
 * Suggested CDR programming for PIO mode3 (180ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0x09,0xde	; secondary
 *
 * Suggested CDR programming for PIO mode4 (120ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0x00,0xde	; secondary
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/init.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>

#include <asm/io.h>

static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	u16 reg = 0;
	unsigned long flags;

	/* select PIO or DMA */
	reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);

	local_irq_save(flags);

	if (reg != hwif->select_data) {
		hwif->select_data = reg;
		/* set PIO/DMA */
		outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
		outw(reg & 0xff, hwif->config_data);
	}

	/* enable IRQ if not probing */
	if (drive->present) {
		reg = inw(hwif->config_data + 3);
		reg &= 0x13;
		reg &= ~(1 << hwif->channel);
		outw(reg, hwif->config_data + 3);
	}

	local_irq_restore(flags);
}

static void trm290_selectproc (ide_drive_t *drive)
{
	trm290_prepare_drive(drive, drive->using_dma);
}

static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command)
{
	BUG_ON(HWGROUP(drive)->handler != NULL);	/* paranoia check */
	ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
	/* issue cmd to drive */
	outb(command, IDE_COMMAND_REG);
}

static int trm290_dma_setup(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct request *rq = hwif->hwgroup->rq;
	unsigned int count, rw;

	if (rq_data_dir(rq)) {
#ifdef TRM290_NO_DMA_WRITES
		/* always use PIO for writes */
		trm290_prepare_drive(drive, 0);	/* select PIO xfer */
		return 1;
#endif
		rw = 1;
	} else
		rw = 2;

	if (!(count = ide_build_dmatable(drive, rq))) {
		/* try PIO instead of DMA */
		trm290_prepare_drive(drive, 0); /* select PIO xfer */
		return 1;
	}
	/* select DMA xfer */
	trm290_prepare_drive(drive, 1);
	outl(hwif->dmatable_dma | rw, hwif->dma_base);
	drive->waiting_for_dma = 1;
	/* start DMA */
	outw(count * 2 - 1, hwif->dma_base + 2);
	return 0;
}

static void trm290_dma_start(ide_drive_t *drive)
{
}

static int trm290_ide_dma_end (ide_drive_t *drive)
{
	u16 status;

	drive->waiting_for_dma = 0;
	/* purge DMA mappings */
	ide_destroy_dmatable(drive);
	status = inw(HWIF(drive)->dma_base + 2);
	return status != 0x00ff;
}

static int trm290_ide_dma_test_irq (ide_drive_t *drive)
{
	u16 status;

	status = inw(HWIF(drive)->dma_base + 2);
	return status == 0x00ff;
}

static void trm290_dma_host_set(ide_drive_t *drive, int on)
{
}

static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned int  cfg_base	= pci_resource_start(dev, 4);
	unsigned long flags;
	u8 reg = 0;

	if ((dev->class & 5) && cfg_base)
		printk(KERN_INFO "TRM290: chip");
	else {
		cfg_base = 0x3df0;
		printk(KERN_INFO "TRM290: using default");
	}
	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
	hwif->config_data = cfg_base;
	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);

	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx",
	       hwif->name, hwif->dma_base, hwif->dma_base + 3);

	if (!request_region(hwif->dma_base, 4, hwif->name)) {
		printk(KERN_CONT " -- Error, ports in use.\n");
		return;
	}

	hwif->dmatable_cpu = pci_alloc_consistent(dev, PRD_ENTRIES * PRD_BYTES,
						  &hwif->dmatable_dma);
	if (!hwif->dmatable_cpu) {
		printk(KERN_CONT " -- Error, unable to allocate DMA table.\n");
		release_region(hwif->dma_base, 4);
		return;
	}
	printk(KERN_CONT "\n");

	local_irq_save(flags);
	/* put config reg into first byte of hwif->select_data */
	outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
	/* select PIO as default */
	hwif->select_data = 0x21;
	outb(hwif->select_data, hwif->config_data);
	/* get IRQ info */
	reg = inb(hwif->config_data + 3);
	/* mask IRQs for both ports */
	reg = (reg & 0x10) | 0x03;
	outb(reg, hwif->config_data + 3);
	local_irq_restore(flags);

	if (reg & 0x10)
		/* legacy mode */
		hwif->irq = hwif->channel ? 15 : 14;
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		/* sharing IRQ with mate */
		hwif->irq = hwif->mate->irq;

	hwif->dma_host_set	= &trm290_dma_host_set;
	hwif->dma_setup 	= &trm290_dma_setup;
	hwif->dma_exec_cmd	= &trm290_dma_exec_cmd;
	hwif->dma_start 	= &trm290_dma_start;
	hwif->ide_dma_end	= &trm290_ide_dma_end;
	hwif->ide_dma_test_irq	= &trm290_ide_dma_test_irq;

	hwif->selectproc = &trm290_selectproc;
#if 1
	{
	/*
	 * My trm290-based card doesn't seem to work with all possible values
	 * for the control basereg, so this kludge ensures that we use only
	 * values that are known to work.  Ugh.		-ml
	 */
		u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
		static u16 next_offset = 0;
		u8 old_mask;

		outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
		old = inw(hwif->config_data);
		old &= ~1;
		old_mask = inb(old + 2);
		if (old != compat && old_mask == 0xff) {
			/* leave lower 10 bits untouched */
			compat += (next_offset += 0x400);
			hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
			outw(compat | 1, hwif->config_data);
			new = inw(hwif->config_data);
			printk(KERN_INFO "%s: control basereg workaround: "
				"old=0x%04x, new=0x%04x\n",
				hwif->name, old, new & ~1);
		}
	}
#endif
}

static const struct ide_port_info trm290_chipset __devinitdata = {
	.name		= "TRM290",
	.init_hwif	= init_hwif_trm290,
	.chipset	= ide_trm290,
	.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
#if 0 /* play it safe for now */
			  IDE_HFLAG_TRUST_BIOS_FOR_DMA |
#endif
			  IDE_HFLAG_NO_AUTODMA |
			  IDE_HFLAG_BOOTABLE |
			  IDE_HFLAG_NO_LBA48,
};

static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &trm290_chipset);
}

static const struct pci_device_id trm290_pci_tbl[] = {
	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);

static struct pci_driver driver = {
	.name		= "TRM290_IDE",
	.id_table	= trm290_pci_tbl,
	.probe		= trm290_init_one,
};

static int __init trm290_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(trm290_ide_init);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
4e5a68ae	2	* linux/drivers/ide/pci/trm290.c Version 1.05 Dec. 30, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (c) 1997-1998 Mark Lord
93c0b560	5	* Copyright (c) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	* May be copied or modified under the terms of the GNU General Public License
	7	*
	8	* June 22, 2004 - get rid of check_region
59904159	9	* - Jesper Juhl
1da177e4 LT	10	*
	11	*/
	12
	13	/*
	14	* This module provides support for the bus-master IDE DMA function
	15	* of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
	16	* including a "Precision Instruments" board. The TRM290 pre-dates
	17	* the sff-8038 standard (ide-dma.c) by a few months, and differs
	18	* significantly enough to warrant separate routines for some functions,
	19	* while re-using others from ide-dma.c.
	20	*
	21	* EXPERIMENTAL! It works for me (a sample of one).
	22	*
	23	* Works reliably for me in DMA mode (READs only),
	24	* DMA WRITEs are disabled by default (see #define below);
	25	*
	26	* DMA is not enabled automatically for this chipset,
	27	* but can be turned on manually (with "hdparm -d1") at run time.
	28	*
	29	* I need volunteers with "spare" drives for further testing
	30	* and development, and maybe to help figure out the peculiarities.
	31	* Even knowing the registers (below), some things behave strangely.
	32	*/
	33
	34	#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
	35
	36	/*
	37	* TRM-290 PCI-IDE2 Bus Master Chip
	38	* ================================
	39	* The configuration registers are addressed in normal I/O port space
	40	* and are used as follows:
	41	*
	42	* trm290_base depends on jumper settings, and is probed for by ide-dma.c
	43	*
	44	* trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
	45	* bit7 must always be written as "1"
	46	* bits6-2 undefined
	47	* bit1 1=legacy_compatible_mode, 0=native_pci_mode
	48	* bit0 1=test_mode, 0=normal(default)
	49	*
	50	* trm290_base+2 when READ: status register (byte, read-only)
	51	* bits7-2 undefined
	52	* bit1 channel0 busmaster interrupt status 0=none, 1=asserted
	53	* bit0 channel0 interrupt status 0=none, 1=asserted
	54	*
	55	* trm290_base+3 Interrupt mask register
	56	* bits7-5 undefined
	57	* bit4 legacy_header: 1=present, 0=absent
	58	* bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
	59	* bit2 channel1 interrupt status 0=none, 1=asserted (read only)
	60	* bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
	61	* bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
	62	*
	63	* trm290_base+1 "CPR" Config Pointer Register (byte)
	64	* bit7 1=autoincrement CPR bits 2-0 after each access of CDR
	65	* bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
	66	* bit5 0=enabled master burst access (default), 1=disable (write only)
	67	* bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
	68	* bit3 0=primary IDE channel, 1=secondary IDE channel
	69	* bits2-0 register index for accesses through CDR port
	70	*
	71	* trm290_base+0 "CDR" Config Data Register (word)
	72	* two sets of seven config registers,
	73	* selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
74	* each index defined below:
75	*
76	* Index-0 Base address register for command block (word)
77	* defaults: 0x1f0 for primary, 0x170 for secondary
78	*
79	* Index-1 general config register (byte)
80	* bit7 1=DMA enable, 0=DMA disable
81	* bit6 1=activate IDE_RESET, 0=no action (default)
82	* bit5 1=enable IORDY, 0=disable IORDY (default)
83	* bit4 0=16-bit data port(default), 1=8-bit (XT) data port
84	* bit3 interrupt polarity: 1=active_low, 0=active_high(default)
85	* bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
86	* bit1 bus_master_mode(?): 1=enable, 0=disable(default)
87	* bit0 enable_io_ports: 1=enable(default), 0=disable
88	*
89	* Index-2 read-ahead counter preload bits 0-7 (byte, write only)
90	* bits7-0 bits7-0 of readahead count
91	*
92	* Index-3 read-ahead config register (byte, write only)
93	* bit7 1=enable_readahead, 0=disable_readahead(default)
94	* bit6 1=clear_FIFO, 0=no_action
95	* bit5 undefined
96	* bit4 mode4 timing control: 1=enable, 0=disable(default)
97	* bit3 undefined
98	* bit2 undefined
99	* bits1-0 bits9-8 of read-ahead count
100	*
101	* Index-4 base address register for control block (word)
102	* defaults: 0x3f6 for primary, 0x376 for secondary
103	*
104	* Index-5 data port timings (shared by both drives) (byte)
105	* standard PCI "clk" (clock) counts, default value = 0xf5
106	*
107	* bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
108	* bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
109	* 011=4clk, 100=5clk, 101=6clk,
110	* 110=8clk, 111=12clk
111	* bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
112	* 011=5clk, 100=6clk, 101=8clk,
113	* 110=12clk, 111=16clk
114	*
115	* Index-6 command/control port timings (shared by both drives) (byte)
116	* same layout as Index-5, default value = 0xde
117	*
118	* Suggested CDR programming for PIO mode0 (600ns):
119	* 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
120	* 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
121	*
122	* Suggested CDR programming for PIO mode3 (180ns):
123	* 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
124	* 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
125	*
126	* Suggested CDR programming for PIO mode4 (120ns):
127	* 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
128	* 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
129	*
130	*/
131
1da177e4 LT	132	#include <linux/types.h>
	133	#include <linux/module.h>
	134	#include <linux/kernel.h>
	135	#include <linux/mm.h>
	136	#include <linux/ioport.h>
	137	#include <linux/interrupt.h>
	138	#include <linux/blkdev.h>
	139	#include <linux/init.h>
	140	#include <linux/hdreg.h>
	141	#include <linux/pci.h>
	142	#include <linux/delay.h>
	143	#include <linux/ide.h>
	144
	145	#include <asm/io.h>
	146
	147	static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	148	{
	149	ide_hwif_t *hwif = HWIF(drive);
	150	u16 reg = 0;
	151	unsigned long flags;
	152
	153	/* select PIO or DMA */
	154	reg = use_dma ? (0x21 \| 0x82) : (0x21 & ~0x82);
	155
	156	local_irq_save(flags);
	157
	158	if (reg != hwif->select_data) {
	159	hwif->select_data = reg;
	160	/* set PIO/DMA */
0ecdca26 BZ	161	outb(0x51 \| (hwif->channel << 3), hwif->config_data + 1);
0ecdca26 BZ	162	outw(reg & 0xff, hwif->config_data);
1da177e4 LT	163	}
	164
	165	/* enable IRQ if not probing */
	166	if (drive->present) {
0ecdca26	167	reg = inw(hwif->config_data + 3);
1da177e4 LT	168	reg &= 0x13;
1da177e4 LT	169	reg &= ~(1 << hwif->channel);
0ecdca26	170	outw(reg, hwif->config_data + 3);
1da177e4 LT	171	}
	172
	173	local_irq_restore(flags);
	174	}
	175
	176	static void trm290_selectproc (ide_drive_t *drive)
	177	{
	178	trm290_prepare_drive(drive, drive->using_dma);
	179	}
	180
93c0b560	181	static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command)
1da177e4	182	{
125e1874	183	BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */
1da177e4 LT	184	ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
1da177e4 LT	185	/* issue cmd to drive */
0ecdca26	186	outb(command, IDE_COMMAND_REG);
1da177e4 LT	187	}
1da177e4 LT	188
93c0b560	189	static int trm290_dma_setup(ide_drive_t *drive)
1da177e4 LT	190	{
	191	ide_hwif_t *hwif = drive->hwif;
	192	struct request *rq = hwif->hwgroup->rq;
	193	unsigned int count, rw;
	194
	195	if (rq_data_dir(rq)) {
	196	#ifdef TRM290_NO_DMA_WRITES
	197	/* always use PIO for writes */
	198	trm290_prepare_drive(drive, 0); /* select PIO xfer */
	199	return 1;
	200	#endif
	201	rw = 1;
	202	} else
	203	rw = 2;
	204
	205	if (!(count = ide_build_dmatable(drive, rq))) {
	206	/* try PIO instead of DMA */
	207	trm290_prepare_drive(drive, 0); /* select PIO xfer */
	208	return 1;
	209	}
	210	/* select DMA xfer */
	211	trm290_prepare_drive(drive, 1);
4e5a68ae	212	outl(hwif->dmatable_dma \| rw, hwif->dma_base);
1da177e4 LT	213	drive->waiting_for_dma = 1;
1da177e4 LT	214	/* start DMA */
4e5a68ae	215	outw(count * 2 - 1, hwif->dma_base + 2);
1da177e4 LT	216	return 0;
	217	}
	218
93c0b560	219	static void trm290_dma_start(ide_drive_t *drive)
1da177e4 LT	220	{
	221	}
	222
	223	static int trm290_ide_dma_end (ide_drive_t *drive)
	224	{
4e5a68ae	225	u16 status;
1da177e4 LT	226
	227	drive->waiting_for_dma = 0;
	228	/* purge DMA mappings */
	229	ide_destroy_dmatable(drive);
4e5a68ae SS	230	status = inw(HWIF(drive)->dma_base + 2);
4e5a68ae SS	231	return status != 0x00ff;
1da177e4 LT	232	}
	233
	234	static int trm290_ide_dma_test_irq (ide_drive_t *drive)
	235	{
4e5a68ae	236	u16 status;
1da177e4	237
4e5a68ae SS	238	status = inw(HWIF(drive)->dma_base + 2);
4e5a68ae SS	239	return status == 0x00ff;
1da177e4	240	}
1da177e4	241
15ce926a	242	static void trm290_dma_host_set(ide_drive_t *drive, int on)
93c0b560 SS	243	{
	244	}
	245
1da177e4 LT	246	static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
1da177e4 LT	247	{
36501650	248	struct pci_dev *dev = to_pci_dev(hwif->dev);
4e5a68ae	249	unsigned int cfg_base = pci_resource_start(dev, 4);
1da177e4 LT	250	unsigned long flags;
1da177e4 LT	251	u8 reg = 0;
1da177e4	252
4e5a68ae SS	253	if ((dev->class & 5) && cfg_base)
	254	printk(KERN_INFO "TRM290: chip");
	255	else {
	256	cfg_base = 0x3df0;
	257	printk(KERN_INFO "TRM290: using default");
	258	}
	259	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
	260	hwif->config_data = cfg_base;
	261	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);
	262
	263	printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
	264	hwif->name, hwif->dma_base, hwif->dma_base + 3);
	265
	266	if (!request_region(hwif->dma_base, 4, hwif->name)) {
	267	printk(KERN_CONT " -- Error, ports in use.\n");
	268	return;
	269	}
	270
	271	hwif->dmatable_cpu = pci_alloc_consistent(dev, PRD_ENTRIES * PRD_BYTES,
	272	&hwif->dmatable_dma);
	273	if (!hwif->dmatable_cpu) {
	274	printk(KERN_CONT " -- Error, unable to allocate DMA table.\n");
	275	release_region(hwif->dma_base, 4);
	276	return;
1da177e4	277	}
4e5a68ae	278	printk(KERN_CONT "\n");
1da177e4 LT	279
	280	local_irq_save(flags);
	281	/* put config reg into first byte of hwif->select_data */
0ecdca26	282	outb(0x51 \| (hwif->channel << 3), hwif->config_data + 1);
1da177e4 LT	283	/* select PIO as default */
1da177e4 LT	284	hwif->select_data = 0x21;
0ecdca26	285	outb(hwif->select_data, hwif->config_data);
1da177e4	286	/* get IRQ info */
0ecdca26	287	reg = inb(hwif->config_data + 3);
1da177e4 LT	288	/* mask IRQs for both ports */
1da177e4 LT	289	reg = (reg & 0x10) \| 0x03;
0ecdca26	290	outb(reg, hwif->config_data + 3);
1da177e4 LT	291	local_irq_restore(flags);
1da177e4 LT	292
4e5a68ae	293	if (reg & 0x10)
1da177e4 LT	294	/* legacy mode */
	295	hwif->irq = hwif->channel ? 15 : 14;
	296	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	297	/* sharing IRQ with mate */
	298	hwif->irq = hwif->mate->irq;
	299
15ce926a	300	hwif->dma_host_set = &trm290_dma_host_set;
93c0b560 SS	301	hwif->dma_setup = &trm290_dma_setup;
	302	hwif->dma_exec_cmd = &trm290_dma_exec_cmd;
	303	hwif->dma_start = &trm290_dma_start;
	304	hwif->ide_dma_end = &trm290_ide_dma_end;
	305	hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
1da177e4 LT	306
1da177e4 LT	307	hwif->selectproc = &trm290_selectproc;
1da177e4 LT	308	#if 1
	309	{
	310	/*
	311	* My trm290-based card doesn't seem to work with all possible values
	312	* for the control basereg, so this kludge ensures that we use only
	313	* values that are known to work. Ugh. -ml
	314	*/
	315	u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
	316	static u16 next_offset = 0;
	317	u8 old_mask;
	318
0ecdca26 BZ	319	outb(0x54 \| (hwif->channel << 3), hwif->config_data + 1);
0ecdca26 BZ	320	old = inw(hwif->config_data);
1da177e4	321	old &= ~1;
0ecdca26	322	old_mask = inb(old + 2);
1da177e4 LT	323	if (old != compat && old_mask == 0xff) {
	324	/* leave lower 10 bits untouched */
	325	compat += (next_offset += 0x400);
	326	hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
0ecdca26 BZ	327	outw(compat \| 1, hwif->config_data);
0ecdca26 BZ	328	new = inw(hwif->config_data);
1da177e4 LT	329	printk(KERN_INFO "%s: control basereg workaround: "
	330	"old=0x%04x, new=0x%04x\n",
	331	hwif->name, old, new & ~1);
	332	}
	333	}
	334	#endif
	335	}
	336
85620436	337	static const struct ide_port_info trm290_chipset __devinitdata = {
1da177e4 LT	338	.name = "TRM290",
1da177e4 LT	339	.init_hwif = init_hwif_trm290,
528a572d	340	.chipset = ide_trm290,
7cab14a7	341	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
9ff6f72f	342	#if 0 /* play it safe for now */
7cab14a7	343	IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
9ff6f72f	344	#endif
47b68788	345	IDE_HFLAG_NO_AUTODMA \|
238e4f14 BZ	346	IDE_HFLAG_BOOTABLE \|
238e4f14 BZ	347	IDE_HFLAG_NO_LBA48,
1da177e4 LT	348	};
	349
	350	static int __devinit trm290_init_one(struct pci_dev dev, const struct pci_device_id id)
	351	{
	352	return ide_setup_pci_device(dev, &trm290_chipset);
	353	}
	354
9cbcc5e3 BZ	355	static const struct pci_device_id trm290_pci_tbl[] = {
9cbcc5e3 BZ	356	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
1da177e4 LT	357	{ 0, },
	358	};
	359	MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
	360
	361	static struct pci_driver driver = {
	362	.name = "TRM290_IDE",
	363	.id_table = trm290_pci_tbl,
	364	.probe = trm290_init_one,
	365	};
	366
82ab1eec	367	static int __init trm290_ide_init(void)
1da177e4 LT	368	{
	369	return ide_pci_register_driver(&driver);
	370	}
	371
	372	module_init(trm290_ide_init);
	373
	374	MODULE_AUTHOR("Mark Lord");
	375	MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
	376	MODULE_LICENSE("GPL");