Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
6157332e | 3 | * Version 3.50 |
1da177e4 LT |
4 | * |
5 | * VIA IDE driver for Linux. Supported southbridges: | |
6 | * | |
7 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
8 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 9 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
10 | * |
11 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
75b1d975 | 12 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
13 | * |
14 | * Based on the work of: | |
15 | * Michel Aubry | |
16 | * Jeff Garzik | |
17 | * Andre Hedrick | |
18 | * | |
19 | * Documentation: | |
20 | * Obsolete device documentation publically available from via.com.tw | |
21 | * Current device documentation available under NDA only | |
22 | */ | |
23 | ||
24 | /* | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License version 2 as published by | |
27 | * the Free Software Foundation. | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/blkdev.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ide.h> | |
bdab00b7 BZ |
37 | #include <linux/dmi.h> |
38 | ||
1da177e4 LT |
39 | #include <asm/io.h> |
40 | ||
74a9d5f1 | 41 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
42 | #include <asm/processor.h> |
43 | #endif | |
44 | ||
45 | #include "ide-timing.h" | |
46 | ||
1da177e4 LT |
47 | #define VIA_IDE_ENABLE 0x40 |
48 | #define VIA_IDE_CONFIG 0x41 | |
49 | #define VIA_FIFO_CONFIG 0x43 | |
50 | #define VIA_MISC_1 0x44 | |
51 | #define VIA_MISC_2 0x45 | |
52 | #define VIA_MISC_3 0x46 | |
53 | #define VIA_DRIVE_TIMING 0x48 | |
54 | #define VIA_8BIT_TIMING 0x4e | |
55 | #define VIA_ADDRESS_SETUP 0x4c | |
56 | #define VIA_UDMA_TIMING 0x50 | |
57 | ||
75b1d975 BZ |
58 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
59 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
60 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
61 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
62 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
63 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
1da177e4 LT |
64 | |
65 | /* | |
66 | * VIA SouthBridge chips. | |
67 | */ | |
68 | ||
69 | static struct via_isa_bridge { | |
70 | char *name; | |
71 | u16 id; | |
72 | u8 rev_min; | |
73 | u8 rev_max; | |
75b1d975 BZ |
74 | u8 udma_mask; |
75 | u8 flags; | |
1da177e4 | 76 | } via_isa_bridges[] = { |
b311ec4a | 77 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
78 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
79 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
80 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
81 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
82 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
83 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
84 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
85 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
86 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
87 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
88 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
89 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
90 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
91 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
92 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
93 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
94 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
95 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
96 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
97 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
98 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
99 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
100 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
1da177e4 LT |
101 | { NULL } |
102 | }; | |
103 | ||
1da177e4 | 104 | static unsigned int via_clock; |
75b1d975 | 105 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 106 | |
7462cbff DD |
107 | struct via82cxxx_dev |
108 | { | |
109 | struct via_isa_bridge *via_config; | |
110 | unsigned int via_80w; | |
111 | }; | |
112 | ||
1da177e4 LT |
113 | /** |
114 | * via_set_speed - write timing registers | |
115 | * @dev: PCI device | |
116 | * @dn: device | |
117 | * @timing: IDE timing data to use | |
118 | * | |
119 | * via_set_speed writes timing values to the chipset registers | |
120 | */ | |
121 | ||
7462cbff | 122 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 123 | { |
36501650 BZ |
124 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
125 | struct via82cxxx_dev *vdev = pci_get_drvdata(dev); | |
1da177e4 LT |
126 | u8 t; |
127 | ||
7462cbff | 128 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 LT |
129 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
130 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
131 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); | |
132 | } | |
133 | ||
134 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
135 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
136 | ||
137 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
138 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
139 | ||
75b1d975 BZ |
140 | switch (vdev->via_config->udma_mask) { |
141 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | |
142 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
143 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
144 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
145 | default: return; | |
1da177e4 LT |
146 | } |
147 | ||
148 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
149 | } | |
150 | ||
151 | /** | |
152 | * via_set_drive - configure transfer mode | |
153 | * @drive: Drive to set up | |
154 | * @speed: desired speed | |
155 | * | |
88b2b32b BZ |
156 | * via_set_drive() computes timing values configures the chipset to |
157 | * a desired transfer mode. It also can be called by upper layers. | |
1da177e4 LT |
158 | */ |
159 | ||
88b2b32b | 160 | static void via_set_drive(ide_drive_t *drive, const u8 speed) |
1da177e4 | 161 | { |
36501650 BZ |
162 | ide_hwif_t *hwif = drive->hwif; |
163 | ide_drive_t *peer = hwif->drives + (~drive->dn & 1); | |
164 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
165 | struct via82cxxx_dev *vdev = pci_get_drvdata(dev); | |
1da177e4 LT |
166 | struct ide_timing t, p; |
167 | unsigned int T, UT; | |
168 | ||
1da177e4 LT |
169 | T = 1000000000 / via_clock; |
170 | ||
75b1d975 BZ |
171 | switch (vdev->via_config->udma_mask) { |
172 | case ATA_UDMA2: UT = T; break; | |
173 | case ATA_UDMA4: UT = T/2; break; | |
174 | case ATA_UDMA5: UT = T/3; break; | |
175 | case ATA_UDMA6: UT = T/4; break; | |
176 | default: UT = T; | |
1da177e4 LT |
177 | } |
178 | ||
179 | ide_timing_compute(drive, speed, &t, T, UT); | |
180 | ||
181 | if (peer->present) { | |
182 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
183 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
184 | } | |
185 | ||
7462cbff | 186 | via_set_speed(HWIF(drive), drive->dn, &t); |
1da177e4 LT |
187 | } |
188 | ||
189 | /** | |
88b2b32b | 190 | * via_set_pio_mode - set host controller for PIO mode |
26bcb879 BZ |
191 | * @drive: drive |
192 | * @pio: PIO mode number | |
1da177e4 LT |
193 | * |
194 | * A callback from the upper layers for PIO-only tuning. | |
195 | */ | |
196 | ||
26bcb879 | 197 | static void via_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 198 | { |
26bcb879 | 199 | via_set_drive(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
200 | } |
201 | ||
7462cbff DD |
202 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) |
203 | { | |
204 | struct via_isa_bridge *via_config; | |
7462cbff DD |
205 | |
206 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 207 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
208 | !!(via_config->flags & VIA_BAD_ID), |
209 | via_config->id, NULL))) { | |
210 | ||
44c10138 AK |
211 | if ((*isa)->revision >= via_config->rev_min && |
212 | (*isa)->revision <= via_config->rev_max) | |
7462cbff | 213 | break; |
652aa162 | 214 | pci_dev_put(*isa); |
7462cbff DD |
215 | } |
216 | ||
217 | return via_config; | |
1da177e4 LT |
218 | } |
219 | ||
cd36beec BZ |
220 | /* |
221 | * Check and handle 80-wire cable presence | |
222 | */ | |
223 | static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u) | |
224 | { | |
225 | int i; | |
226 | ||
75b1d975 BZ |
227 | switch (vdev->via_config->udma_mask) { |
228 | case ATA_UDMA4: | |
cd36beec BZ |
229 | for (i = 24; i >= 0; i -= 8) |
230 | if (((u >> (i & 16)) & 8) && | |
231 | ((u >> i) & 0x20) && | |
232 | (((u >> i) & 7) < 2)) { | |
233 | /* | |
234 | * 2x PCI clock and | |
235 | * UDMA w/ < 3T/cycle | |
236 | */ | |
237 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
238 | } | |
239 | break; | |
240 | ||
75b1d975 | 241 | case ATA_UDMA5: |
cd36beec BZ |
242 | for (i = 24; i >= 0; i -= 8) |
243 | if (((u >> i) & 0x10) || | |
244 | (((u >> i) & 0x20) && | |
245 | (((u >> i) & 7) < 4))) { | |
246 | /* BIOS 80-wire bit or | |
247 | * UDMA w/ < 60ns/cycle | |
248 | */ | |
249 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
250 | } | |
251 | break; | |
252 | ||
75b1d975 | 253 | case ATA_UDMA6: |
cd36beec BZ |
254 | for (i = 24; i >= 0; i -= 8) |
255 | if (((u >> i) & 0x10) || | |
256 | (((u >> i) & 0x20) && | |
257 | (((u >> i) & 7) < 6))) { | |
258 | /* BIOS 80-wire bit or | |
259 | * UDMA w/ < 60ns/cycle | |
260 | */ | |
261 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
262 | } | |
263 | break; | |
264 | } | |
265 | } | |
266 | ||
1da177e4 LT |
267 | /** |
268 | * init_chipset_via82cxxx - initialization handler | |
269 | * @dev: PCI device | |
270 | * @name: Name of interface | |
271 | * | |
272 | * The initialization callback. Here we determine the IDE chip type | |
273 | * and initialize its drive independent registers. | |
274 | */ | |
275 | ||
f3718d3e | 276 | static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name) |
1da177e4 LT |
277 | { |
278 | struct pci_dev *isa = NULL; | |
cd36beec | 279 | struct via82cxxx_dev *vdev; |
7462cbff | 280 | struct via_isa_bridge *via_config; |
1da177e4 | 281 | u8 t, v; |
cd36beec BZ |
282 | u32 u; |
283 | ||
284 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); | |
285 | if (!vdev) { | |
286 | printk(KERN_ERR "VP_IDE: out of memory :(\n"); | |
287 | return -ENOMEM; | |
288 | } | |
289 | pci_set_drvdata(dev, vdev); | |
1da177e4 LT |
290 | |
291 | /* | |
292 | * Find the ISA bridge to see how good the IDE is. | |
293 | */ | |
cd36beec | 294 | vdev->via_config = via_config = via_config_find(&isa); |
23a1b2a7 AC |
295 | |
296 | /* We checked this earlier so if it fails here deeep badness | |
297 | is involved */ | |
298 | ||
299 | BUG_ON(!via_config->id); | |
1da177e4 LT |
300 | |
301 | /* | |
cd36beec | 302 | * Detect cable and configure Clk66 |
1da177e4 | 303 | */ |
cd36beec BZ |
304 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
305 | ||
306 | via_cable_detect(vdev, u); | |
1da177e4 | 307 | |
75b1d975 | 308 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 309 | /* Enable Clk66 */ |
7462cbff DD |
310 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
311 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 312 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
313 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
314 | } | |
315 | ||
316 | /* | |
317 | * Check whether interfaces are enabled. | |
318 | */ | |
319 | ||
320 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
321 | ||
322 | /* | |
323 | * Set up FIFO sizes and thresholds. | |
324 | */ | |
325 | ||
326 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
327 | ||
328 | /* Disable PREQ# till DDACK# */ | |
329 | if (via_config->flags & VIA_BAD_PREQ) { | |
330 | /* Would crash on 586b rev 41 */ | |
331 | t &= 0x7f; | |
332 | } | |
333 | ||
334 | /* Fix FIFO split between channels */ | |
335 | if (via_config->flags & VIA_SET_FIFO) { | |
336 | t &= (t & 0x9f); | |
337 | switch (v & 3) { | |
338 | case 2: t |= 0x00; break; /* 16 on primary */ | |
339 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
340 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
341 | } | |
342 | } | |
343 | ||
344 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
345 | ||
346 | /* | |
347 | * Determine system bus clock. | |
348 | */ | |
349 | ||
350 | via_clock = system_bus_clock() * 1000; | |
351 | ||
352 | switch (via_clock) { | |
353 | case 33000: via_clock = 33333; break; | |
354 | case 37000: via_clock = 37500; break; | |
355 | case 41000: via_clock = 41666; break; | |
356 | } | |
357 | ||
358 | if (via_clock < 20000 || via_clock > 50000) { | |
359 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
360 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
361 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
362 | "to assume 80-wire cable.\n"); | |
363 | via_clock = 33333; | |
364 | } | |
365 | ||
366 | /* | |
367 | * Print the boot message. | |
368 | */ | |
369 | ||
75b1d975 | 370 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s " |
1da177e4 | 371 | "controller on pci%s\n", |
44c10138 | 372 | via_config->name, isa->revision, |
75b1d975 BZ |
373 | via_config->udma_mask ? "U" : "MW", |
374 | via_dma[via_config->udma_mask ? | |
375 | (fls(via_config->udma_mask) - 1) : 0], | |
1da177e4 LT |
376 | pci_name(dev)); |
377 | ||
652aa162 | 378 | pci_dev_put(isa); |
1da177e4 LT |
379 | return 0; |
380 | } | |
381 | ||
bdab00b7 BZ |
382 | /* |
383 | * Cable special cases | |
384 | */ | |
385 | ||
1855256c | 386 | static const struct dmi_system_id cable_dmi_table[] = { |
bdab00b7 BZ |
387 | { |
388 | .ident = "Acer Ferrari 3400", | |
389 | .matches = { | |
390 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
391 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
392 | }, | |
393 | }, | |
394 | { } | |
395 | }; | |
396 | ||
58e47bb1 | 397 | static int via_cable_override(struct pci_dev *pdev) |
bdab00b7 BZ |
398 | { |
399 | /* Systems by DMI */ | |
400 | if (dmi_check_system(cable_dmi_table)) | |
401 | return 1; | |
58e47bb1 BZ |
402 | |
403 | /* Arima W730-K8/Targa Visionary 811/... */ | |
404 | if (pdev->subsystem_vendor == 0x161F && | |
405 | pdev->subsystem_device == 0x2032) | |
406 | return 1; | |
407 | ||
bdab00b7 BZ |
408 | return 0; |
409 | } | |
410 | ||
411 | static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif) | |
412 | { | |
36501650 | 413 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
58e47bb1 | 414 | struct via82cxxx_dev *vdev = pci_get_drvdata(pdev); |
bdab00b7 | 415 | |
58e47bb1 | 416 | if (via_cable_override(pdev)) |
bdab00b7 BZ |
417 | return ATA_CBL_PATA40_SHORT; |
418 | ||
419 | if ((vdev->via_80w >> hwif->channel) & 1) | |
420 | return ATA_CBL_PATA80; | |
421 | else | |
422 | return ATA_CBL_PATA40; | |
423 | } | |
424 | ||
f3718d3e | 425 | static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif) |
1da177e4 | 426 | { |
26bcb879 | 427 | hwif->set_pio_mode = &via_set_pio_mode; |
88b2b32b | 428 | hwif->set_dma_mode = &via_set_drive; |
1da177e4 | 429 | |
1da177e4 LT |
430 | if (!hwif->dma_base) |
431 | return; | |
432 | ||
bdab00b7 BZ |
433 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
434 | hwif->cbl = via82cxxx_cable_detect(hwif); | |
1da177e4 LT |
435 | } |
436 | ||
85620436 | 437 | static const struct ide_port_info via82cxxx_chipset __devinitdata = { |
6157332e BZ |
438 | .name = "VP_IDE", |
439 | .init_chipset = init_chipset_via82cxxx, | |
440 | .init_hwif = init_hwif_via82cxxx, | |
441 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, | |
442 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | | |
443 | IDE_HFLAG_PIO_NO_DOWNGRADE | | |
4db90a14 | 444 | IDE_HFLAG_ABUSE_SET_DMA_MODE | |
6157332e BZ |
445 | IDE_HFLAG_POST_SET_MODE | |
446 | IDE_HFLAG_IO_32BIT | | |
447 | IDE_HFLAG_BOOTABLE, | |
448 | .pio_mask = ATA_PIO5, | |
449 | .swdma_mask = ATA_SWDMA2, | |
450 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
451 | }; |
452 | ||
453 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
454 | { | |
23a1b2a7 AC |
455 | struct pci_dev *isa = NULL; |
456 | struct via_isa_bridge *via_config; | |
6157332e | 457 | u8 idx = id->driver_data; |
039788e1 | 458 | struct ide_port_info d; |
6157332e BZ |
459 | |
460 | d = via82cxxx_chipset; | |
8acf28c0 | 461 | |
23a1b2a7 AC |
462 | /* |
463 | * Find the ISA bridge and check we know what it is. | |
464 | */ | |
465 | via_config = via_config_find(&isa); | |
466 | pci_dev_put(isa); | |
467 | if (!via_config->id) { | |
468 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
469 | return -ENODEV; | |
470 | } | |
8acf28c0 | 471 | |
6157332e BZ |
472 | if (idx == 0) |
473 | d.host_flags |= IDE_HFLAG_NO_AUTODMA; | |
caea7602 | 474 | else |
6157332e BZ |
475 | d.enablebits[1].reg = d.enablebits[0].reg = 0; |
476 | ||
477 | if ((via_config->flags & VIA_NO_UNMASK) == 0) | |
478 | d.host_flags |= IDE_HFLAG_UNMASK_IRQS; | |
caea7602 | 479 | |
8acf28c0 BZ |
480 | #ifdef CONFIG_PPC_CHRP |
481 | if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos) | |
6157332e | 482 | d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS; |
8acf28c0 BZ |
483 | #endif |
484 | ||
6157332e | 485 | d.udma_mask = via_config->udma_mask; |
8acf28c0 | 486 | |
6157332e | 487 | return ide_setup_pci_device(dev, &d); |
1da177e4 LT |
488 | } |
489 | ||
9cbcc5e3 BZ |
490 | static const struct pci_device_id via_pci_tbl[] = { |
491 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, | |
492 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, | |
493 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, | |
494 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, | |
1da177e4 LT |
495 | { 0, }, |
496 | }; | |
497 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
498 | ||
499 | static struct pci_driver driver = { | |
500 | .name = "VIA_IDE", | |
501 | .id_table = via_pci_tbl, | |
502 | .probe = via_init_one, | |
503 | }; | |
504 | ||
82ab1eec | 505 | static int __init via_ide_init(void) |
1da177e4 LT |
506 | { |
507 | return ide_pci_register_driver(&driver); | |
508 | } | |
509 | ||
510 | module_init(via_ide_init); | |
511 | ||
512 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
513 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
514 | MODULE_LICENSE("GPL"); |