[deliverable/linux.git] / drivers / ide / pci / via82cxxx.c

/*
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#include <asm/io.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the chipset to
 *	a desired transfer mode.  It also can be called by upper layers.
 */

static void via_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
	struct ide_timing t, p;
	unsigned int T, UT;

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);
}

/**
 *	via_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	via_set_drive(drive, XFER_PIO_0 + pio);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			if ((*isa)->revision >= via_config->rev_min &&
			    (*isa)->revision <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via82cxxx_dev *vdev;
	struct via_isa_bridge *via_config;
	u8 t, v;
	u32 u;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return -ENOMEM;
	}
	pci_set_drvdata(dev, vdev);

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	vdev->via_config = via_config = via_config_find(&isa);

	/* We checked this earlier so if it fails here deeep badness
	   is involved */

	BUG_ON(!via_config->id);

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
		"controller on pci%s\n",
		via_config->name, isa->revision,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0],
		pci_name(dev));

	pci_dev_put(isa);
	return 0;
}

/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;

	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F &&
	    pdev->subsystem_device == 0x2032)
		return 1;

	return 0;
}

static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	struct via82cxxx_dev *vdev = pci_get_drvdata(pdev);

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &via_set_pio_mode;
	hwif->set_dma_mode = &via_set_drive;

	if (!hwif->dma_base)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = via82cxxx_cable_detect(hwif);
}

static const struct ide_port_info via82cxxx_chipset __devinitdata = {
	.name		= "VP_IDE",
	.init_chipset	= init_chipset_via82cxxx,
	.init_hwif	= init_hwif_via82cxxx,
	.enablebits	= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST |
			  IDE_HFLAG_PIO_NO_DOWNGRADE |
			  IDE_HFLAG_ABUSE_SET_DMA_MODE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_IO_32BIT |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO5,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	u8 idx = id->driver_data;
	struct ide_port_info d;

	d = via82cxxx_chipset;

	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);
	pci_dev_put(isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}

	if (idx == 0)
		d.host_flags |= IDE_HFLAG_NO_AUTODMA;
	else
		d.enablebits[1].reg = d.enablebits[0].reg = 0;

	if ((via_config->flags & VIA_NO_UNMASK) == 0)
		d.host_flags |= IDE_HFLAG_UNMASK_IRQS;

#ifdef CONFIG_PPC_CHRP
	if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
		d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS;
#endif

	d.udma_mask = via_config->udma_mask;

	return ide_setup_pci_device(dev, &d);
}

static const struct pci_device_id via_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* VIA IDE driver for Linux. Supported southbridges:
	3	*
	4	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	5	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	6	* vt8235, vt8237, vt8237a
1da177e4 LT	7	*
1da177e4 LT	8	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	9	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	10	*
	11	* Based on the work of:
	12	* Michel Aubry
	13	* Jeff Garzik
	14	* Andre Hedrick
	15	*
	16	* Documentation:
	17	* Obsolete device documentation publically available from via.com.tw
	18	* Current device documentation available under NDA only
	19	*/
	20
	21	/*
	22	* This program is free software; you can redistribute it and/or modify it
	23	* under the terms of the GNU General Public License version 2 as published by
	24	* the Free Software Foundation.
	25	*/
	26
1da177e4 LT	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/ioport.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/pci.h>
	32	#include <linux/init.h>
	33	#include <linux/ide.h>
bdab00b7 BZ	34	#include <linux/dmi.h>
bdab00b7 BZ	35
1da177e4 LT	36	#include <asm/io.h>
1da177e4 LT	37
74a9d5f1	38	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	39	#include <asm/processor.h>
	40	#endif
	41
	42	#include "ide-timing.h"
	43
1da177e4 LT	44	#define VIA_IDE_ENABLE 0x40
	45	#define VIA_IDE_CONFIG 0x41
	46	#define VIA_FIFO_CONFIG 0x43
	47	#define VIA_MISC_1 0x44
	48	#define VIA_MISC_2 0x45
	49	#define VIA_MISC_3 0x46
	50	#define VIA_DRIVE_TIMING 0x48
	51	#define VIA_8BIT_TIMING 0x4e
	52	#define VIA_ADDRESS_SETUP 0x4c
	53	#define VIA_UDMA_TIMING 0x50
	54
75b1d975 BZ	55	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	56	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	57	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	58	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	59	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	60	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
1da177e4 LT	61
	62	/*
	63	* VIA SouthBridge chips.
	64	*/
	65
	66	static struct via_isa_bridge {
	67	char *name;
	68	u16 id;
	69	u8 rev_min;
	70	u8 rev_max;
75b1d975 BZ	71	u8 udma_mask;
75b1d975 BZ	72	u8 flags;
1da177e4	73	} via_isa_bridges[] = {
b311ec4a	74	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	75	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	76	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	77	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	78	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	79	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	80	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	81	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	82	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	84	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	85	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	86	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	87	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	88	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	89	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	90	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	91	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	92	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	93	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	94	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	95	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	96	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	97	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
1da177e4 LT	98	{ NULL }
	99	};
	100
1da177e4	101	static unsigned int via_clock;
75b1d975	102	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	103
7462cbff DD	104	struct via82cxxx_dev
	105	{
	106	struct via_isa_bridge *via_config;
	107	unsigned int via_80w;
	108	};
	109
1da177e4 LT	110	/**
	111	* via_set_speed - write timing registers
	112	* @dev: PCI device
	113	* @dn: device
	114	* @timing: IDE timing data to use
	115	*
	116	* via_set_speed writes timing values to the chipset registers
	117	*/
	118
7462cbff	119	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	120	{
36501650 BZ	121	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	122	struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
1da177e4 LT	123	u8 t;
1da177e4 LT	124
7462cbff	125	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	126	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	127	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	128	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	129	}
	130
	131	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	132	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	133
	134	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	135	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	136
75b1d975 BZ	137	switch (vdev->via_config->udma_mask) {
	138	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	139	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	140	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	141	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	142	default: return;
1da177e4 LT	143	}
	144
	145	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	146	}
	147
	148	/**
	149	* via_set_drive - configure transfer mode
	150	* @drive: Drive to set up
	151	* @speed: desired speed
	152	*
88b2b32b BZ	153	* via_set_drive() computes timing values configures the chipset to
88b2b32b BZ	154	* a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	155	*/
1da177e4 LT	156
88b2b32b	157	static void via_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4	158	{
36501650 BZ	159	ide_hwif_t *hwif = drive->hwif;
	160	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
	161	struct pci_dev *dev = to_pci_dev(hwif->dev);
	162	struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
1da177e4 LT	163	struct ide_timing t, p;
	164	unsigned int T, UT;
	165
1da177e4 LT	166	T = 1000000000 / via_clock;
1da177e4 LT	167
75b1d975 BZ	168	switch (vdev->via_config->udma_mask) {
	169	case ATA_UDMA2: UT = T; break;
	170	case ATA_UDMA4: UT = T/2; break;
	171	case ATA_UDMA5: UT = T/3; break;
	172	case ATA_UDMA6: UT = T/4; break;
	173	default: UT = T;
1da177e4 LT	174	}
	175
	176	ide_timing_compute(drive, speed, &t, T, UT);
	177
	178	if (peer->present) {
	179	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	180	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	181	}
	182
7462cbff	183	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	184	}
	185
	186	/**
88b2b32b	187	* via_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	188	* @drive: drive
26bcb879 BZ	189	* @pio: PIO mode number
1da177e4 LT	190	*
	191	* A callback from the upper layers for PIO-only tuning.
	192	*/
	193
26bcb879	194	static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	195	{
26bcb879	196	via_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	197	}
1da177e4 LT	198
7462cbff DD	199	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	200	{
	201	struct via_isa_bridge *via_config;
7462cbff DD	202
7462cbff DD	203	for (via_config = via_isa_bridges; via_config->id; via_config++)
652aa162	204	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	205	!!(via_config->flags & VIA_BAD_ID),
	206	via_config->id, NULL))) {
	207
44c10138 AK	208	if ((*isa)->revision >= via_config->rev_min &&
44c10138 AK	209	(*isa)->revision <= via_config->rev_max)
7462cbff	210	break;
652aa162	211	pci_dev_put(*isa);
7462cbff DD	212	}
	213
	214	return via_config;
1da177e4 LT	215	}
1da177e4 LT	216
cd36beec BZ	217	/*
	218	* Check and handle 80-wire cable presence
	219	*/
	220	static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
	221	{
	222	int i;
	223
75b1d975 BZ	224	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	225	case ATA_UDMA4:
cd36beec BZ	226	for (i = 24; i >= 0; i -= 8)
	227	if (((u >> (i & 16)) & 8) &&
	228	((u >> i) & 0x20) &&
	229	(((u >> i) & 7) < 2)) {
	230	/*
	231	* 2x PCI clock and
	232	* UDMA w/ < 3T/cycle
	233	*/
	234	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	235	}
	236	break;
	237
75b1d975	238	case ATA_UDMA5:
cd36beec BZ	239	for (i = 24; i >= 0; i -= 8)
	240	if (((u >> i) & 0x10) \|\|
	241	(((u >> i) & 0x20) &&
	242	(((u >> i) & 7) < 4))) {
	243	/* BIOS 80-wire bit or
	244	* UDMA w/ < 60ns/cycle
	245	*/
	246	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	247	}
	248	break;
	249
75b1d975	250	case ATA_UDMA6:
cd36beec BZ	251	for (i = 24; i >= 0; i -= 8)
	252	if (((u >> i) & 0x10) \|\|
	253	(((u >> i) & 0x20) &&
	254	(((u >> i) & 7) < 6))) {
	255	/* BIOS 80-wire bit or
	256	* UDMA w/ < 60ns/cycle
	257	*/
	258	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	259	}
	260	break;
	261	}
	262	}
	263
1da177e4 LT	264	/**
	265	* init_chipset_via82cxxx - initialization handler
	266	* @dev: PCI device
	267	* @name: Name of interface
	268	*
	269	* The initialization callback. Here we determine the IDE chip type
	270	* and initialize its drive independent registers.
	271	*/
	272
f3718d3e	273	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	274	{
1da177e4 LT	275	struct pci_dev *isa = NULL;
cd36beec	276	struct via82cxxx_dev *vdev;
7462cbff	277	struct via_isa_bridge *via_config;
1da177e4	278	u8 t, v;
cd36beec BZ	279	u32 u;
	280
	281	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	282	if (!vdev) {
	283	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	284	return -ENOMEM;
	285	}
	286	pci_set_drvdata(dev, vdev);
1da177e4 LT	287
	288	/*
	289	* Find the ISA bridge to see how good the IDE is.
	290	*/
cd36beec	291	vdev->via_config = via_config = via_config_find(&isa);
23a1b2a7 AC	292
	293	/* We checked this earlier so if it fails here deeep badness
	294	is involved */
	295
	296	BUG_ON(!via_config->id);
1da177e4 LT	297
1da177e4 LT	298	/*
cd36beec	299	* Detect cable and configure Clk66
1da177e4	300	*/
cd36beec BZ	301	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	302
	303	via_cable_detect(vdev, u);
1da177e4	304
75b1d975	305	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	306	/* Enable Clk66 */
7462cbff DD	307	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	308	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	309	/* Would cause trouble on 596a and 686 */
1da177e4 LT	310	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	311	}
	312
	313	/*
	314	* Check whether interfaces are enabled.
	315	*/
	316
	317	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	318
	319	/*
	320	* Set up FIFO sizes and thresholds.
	321	*/
	322
	323	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	324
	325	/* Disable PREQ# till DDACK# */
	326	if (via_config->flags & VIA_BAD_PREQ) {
	327	/* Would crash on 586b rev 41 */
	328	t &= 0x7f;
	329	}
	330
	331	/* Fix FIFO split between channels */
	332	if (via_config->flags & VIA_SET_FIFO) {
	333	t &= (t & 0x9f);
	334	switch (v & 3) {
	335	case 2: t \|= 0x00; break; /* 16 on primary */
	336	case 1: t \|= 0x60; break; /* 16 on secondary */
	337	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	338	}
	339	}
	340
	341	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	342
	343	/*
	344	* Determine system bus clock.
	345	*/
	346
	347	via_clock = system_bus_clock() * 1000;
	348
	349	switch (via_clock) {
	350	case 33000: via_clock = 33333; break;
	351	case 37000: via_clock = 37500; break;
	352	case 41000: via_clock = 41666; break;
	353	}
	354
	355	if (via_clock < 20000 \|\| via_clock > 50000) {
	356	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	357	"impossible (%d), using 33 MHz instead.\n", via_clock);
	358	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	359	"to assume 80-wire cable.\n");
	360	via_clock = 33333;
	361	}
	362
	363	/*
	364	* Print the boot message.
	365	*/
	366
75b1d975	367	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
1da177e4	368	"controller on pci%s\n",
44c10138	369	via_config->name, isa->revision,
75b1d975 BZ	370	via_config->udma_mask ? "U" : "MW",
	371	via_dma[via_config->udma_mask ?
	372	(fls(via_config->udma_mask) - 1) : 0],
1da177e4 LT	373	pci_name(dev));
1da177e4 LT	374
652aa162	375	pci_dev_put(isa);
1da177e4 LT	376	return 0;
	377	}
	378
bdab00b7 BZ	379	/*
	380	* Cable special cases
	381	*/
	382
1855256c	383	static const struct dmi_system_id cable_dmi_table[] = {
bdab00b7 BZ	384	{
	385	.ident = "Acer Ferrari 3400",
	386	.matches = {
	387	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	388	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	389	},
	390	},
	391	{ }
	392	};
	393
58e47bb1	394	static int via_cable_override(struct pci_dev *pdev)
bdab00b7 BZ	395	{
	396	/* Systems by DMI */
	397	if (dmi_check_system(cable_dmi_table))
	398	return 1;
58e47bb1 BZ	399
	400	/* Arima W730-K8/Targa Visionary 811/... */
	401	if (pdev->subsystem_vendor == 0x161F &&
	402	pdev->subsystem_device == 0x2032)
	403	return 1;
	404
bdab00b7 BZ	405	return 0;
	406	}
	407
	408	static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
	409	{
36501650	410	struct pci_dev *pdev = to_pci_dev(hwif->dev);
58e47bb1	411	struct via82cxxx_dev *vdev = pci_get_drvdata(pdev);
bdab00b7	412
58e47bb1	413	if (via_cable_override(pdev))
bdab00b7 BZ	414	return ATA_CBL_PATA40_SHORT;
	415
	416	if ((vdev->via_80w >> hwif->channel) & 1)
	417	return ATA_CBL_PATA80;
	418	else
	419	return ATA_CBL_PATA40;
	420	}
	421
f3718d3e	422	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	423	{
26bcb879	424	hwif->set_pio_mode = &via_set_pio_mode;
88b2b32b	425	hwif->set_dma_mode = &via_set_drive;
1da177e4	426
1da177e4 LT	427	if (!hwif->dma_base)
	428	return;
	429
bdab00b7 BZ	430	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
bdab00b7 BZ	431	hwif->cbl = via82cxxx_cable_detect(hwif);
1da177e4 LT	432	}
1da177e4 LT	433
85620436	434	static const struct ide_port_info via82cxxx_chipset __devinitdata = {
6157332e BZ	435	.name = "VP_IDE",
	436	.init_chipset = init_chipset_via82cxxx,
	437	.init_hwif = init_hwif_via82cxxx,
	438	.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	439	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \|
	440	IDE_HFLAG_PIO_NO_DOWNGRADE \|
4db90a14	441	IDE_HFLAG_ABUSE_SET_DMA_MODE \|
6157332e BZ	442	IDE_HFLAG_POST_SET_MODE \|
	443	IDE_HFLAG_IO_32BIT \|
	444	IDE_HFLAG_BOOTABLE,
	445	.pio_mask = ATA_PIO5,
	446	.swdma_mask = ATA_SWDMA2,
	447	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	448	};
	449
	450	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	451	{
23a1b2a7 AC	452	struct pci_dev *isa = NULL;
23a1b2a7 AC	453	struct via_isa_bridge *via_config;
6157332e	454	u8 idx = id->driver_data;
039788e1	455	struct ide_port_info d;
6157332e BZ	456
6157332e BZ	457	d = via82cxxx_chipset;
8acf28c0	458
23a1b2a7 AC	459	/*
	460	* Find the ISA bridge and check we know what it is.
	461	*/
	462	via_config = via_config_find(&isa);
	463	pci_dev_put(isa);
	464	if (!via_config->id) {
	465	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	466	return -ENODEV;
	467	}
8acf28c0	468
6157332e BZ	469	if (idx == 0)
6157332e BZ	470	d.host_flags \|= IDE_HFLAG_NO_AUTODMA;
caea7602	471	else
6157332e BZ	472	d.enablebits[1].reg = d.enablebits[0].reg = 0;
	473
	474	if ((via_config->flags & VIA_NO_UNMASK) == 0)
	475	d.host_flags \|= IDE_HFLAG_UNMASK_IRQS;
caea7602	476
8acf28c0 BZ	477	#ifdef CONFIG_PPC_CHRP
8acf28c0 BZ	478	if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
6157332e	479	d.host_flags \|= IDE_HFLAG_FORCE_LEGACY_IRQS;
8acf28c0 BZ	480	#endif
8acf28c0 BZ	481
6157332e	482	d.udma_mask = via_config->udma_mask;
8acf28c0	483
6157332e	484	return ide_setup_pci_device(dev, &d);
1da177e4 LT	485	}
1da177e4 LT	486
9cbcc5e3 BZ	487	static const struct pci_device_id via_pci_tbl[] = {
	488	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
	489	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
	490	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
	491	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
1da177e4 LT	492	{ 0, },
	493	};
	494	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	495
	496	static struct pci_driver driver = {
	497	.name = "VIA_IDE",
	498	.id_table = via_pci_tbl,
	499	.probe = via_init_one,
	500	};
	501
82ab1eec	502	static int __init via_ide_init(void)
1da177e4 LT	503	{
	504	return ide_pci_register_driver(&driver);
	505	}
	506
	507	module_init(via_ide_init);
	508
	509	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	510	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	511	MODULE_LICENSE("GPL");