[deliverable/linux.git] / drivers / ide / pci / via82cxxx.c

/*
 *
 * Version 3.45
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#include <asm/io.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the drive and
 *	the chipset to a desired transfer mode. It also can be called
 *	by upper layers.
 */

static int via_set_drive(ide_drive_t *drive, u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
	struct ide_timing t, p;
	unsigned int T, UT;

	if (speed != XFER_PIO_SLOW)
		ide_config_drive_speed(drive, speed);

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);

	if (!drive->init_speed)
		drive->init_speed = speed;
	drive->current_speed = speed;

	return 0;
}

/**
 *	via82cxxx_tune_drive	-	PIO setup
 *	@drive: drive to set up
 *	@pio: mode to use (255 for 'best possible')
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
{
	if (pio == 255) {
		via_set_drive(drive, ide_find_best_pio_mode(drive));
		return;
	}

	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
}

/**
 *	via82cxxx_ide_dma_check		-	set up for DMA if possible
 *	@drive: IDE drive to set up
 *
 *	Set up the drive for the highest supported speed considering the
 *	driver, controller and cable
 */
 
static int via82cxxx_ide_dma_check (ide_drive_t *drive)
{
	u8 speed = ide_max_dma_mode(drive);

	if (speed == 0)
		speed = ide_find_best_pio_mode(drive);

	via_set_drive(drive, speed);

	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
		return 0;

	return -1;
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;
	u8 t;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
			if (t >= via_config->rev_min &&
			    t <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via82cxxx_dev *vdev;
	struct via_isa_bridge *via_config;
	u8 t, v;
	u32 u;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return -ENOMEM;
	}
	pci_set_drvdata(dev, vdev);

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	vdev->via_config = via_config = via_config_find(&isa);

	/* We checked this earlier so if it fails here deeep badness
	   is involved */

	BUG_ON(!via_config->id);

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
		"controller on pci%s\n",
		via_config->name, t,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0],
		pci_name(dev));

	pci_dev_put(isa);
	return 0;
}

/*
 *	Cable special cases
 */

static struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(void)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;
	return 0;
}

static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);

	if (via_cable_override())
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	int i;

	hwif->autodma = 0;

	hwif->tuneproc = &via82cxxx_tune_drive;
	hwif->speedproc = &via_set_drive;


#ifdef CONFIG_PPC_CHRP
	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
		hwif->irq = hwif->channel ? 15 : 14;
	}
#endif

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;

	hwif->ultra_mask = vdev->via_config->udma_mask;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = via82cxxx_cable_detect(hwif);

	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= NOAUTODMA,
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
		.bootable	= ON_BOARD
	},{	/* 1 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
		.bootable	= ON_BOARD,
	}
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);
	pci_dev_put(isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
}

static struct pci_device_id via_pci_tbl[] = {
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	*
bdab00b7	3	* Version 3.45
1da177e4 LT	4	*
	5	* VIA IDE driver for Linux. Supported southbridges:
	6	*
	7	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	8	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	9	* vt8235, vt8237, vt8237a
1da177e4 LT	10	*
1da177e4 LT	11	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	12	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	13	*
	14	* Based on the work of:
	15	* Michel Aubry
	16	* Jeff Garzik
	17	* Andre Hedrick
	18	*
	19	* Documentation:
	20	* Obsolete device documentation publically available from via.com.tw
	21	* Current device documentation available under NDA only
	22	*/
	23
	24	/*
	25	* This program is free software; you can redistribute it and/or modify it
	26	* under the terms of the GNU General Public License version 2 as published by
	27	* the Free Software Foundation.
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/ioport.h>
	33	#include <linux/blkdev.h>
	34	#include <linux/pci.h>
	35	#include <linux/init.h>
	36	#include <linux/ide.h>
bdab00b7 BZ	37	#include <linux/dmi.h>
bdab00b7 BZ	38
1da177e4 LT	39	#include <asm/io.h>
1da177e4 LT	40
74a9d5f1	41	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	42	#include <asm/processor.h>
	43	#endif
	44
	45	#include "ide-timing.h"
	46
1da177e4 LT	47	#define VIA_IDE_ENABLE 0x40
	48	#define VIA_IDE_CONFIG 0x41
	49	#define VIA_FIFO_CONFIG 0x43
	50	#define VIA_MISC_1 0x44
	51	#define VIA_MISC_2 0x45
	52	#define VIA_MISC_3 0x46
	53	#define VIA_DRIVE_TIMING 0x48
	54	#define VIA_8BIT_TIMING 0x4e
	55	#define VIA_ADDRESS_SETUP 0x4c
	56	#define VIA_UDMA_TIMING 0x50
	57
75b1d975 BZ	58	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	59	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	60	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	61	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	62	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	63	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
1da177e4 LT	64
	65	/*
	66	* VIA SouthBridge chips.
	67	*/
	68
	69	static struct via_isa_bridge {
	70	char *name;
	71	u16 id;
	72	u8 rev_min;
	73	u8 rev_max;
75b1d975 BZ	74	u8 udma_mask;
75b1d975 BZ	75	u8 flags;
1da177e4	76	} via_isa_bridges[] = {
75b1d975 BZ	77	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	78	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	79	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	80	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	81	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	82	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	84	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	85	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	86	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	87	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	88	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	89	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	90	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	91	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	92	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	93	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	94	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	96	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	97	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	98	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	99	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
1da177e4 LT	100	{ NULL }
	101	};
	102
1da177e4	103	static unsigned int via_clock;
75b1d975	104	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	105
7462cbff DD	106	struct via82cxxx_dev
	107	{
	108	struct via_isa_bridge *via_config;
	109	unsigned int via_80w;
	110	};
	111
1da177e4 LT	112	/**
	113	* via_set_speed - write timing registers
	114	* @dev: PCI device
	115	* @dn: device
	116	* @timing: IDE timing data to use
	117	*
	118	* via_set_speed writes timing values to the chipset registers
	119	*/
	120
7462cbff	121	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	122	{
7462cbff	123	struct pci_dev *dev = hwif->pci_dev;
cd36beec	124	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	125	u8 t;
1da177e4 LT	126
7462cbff	127	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	128	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	129	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	130	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	131	}
	132
	133	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	134	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	135
	136	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	137	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	138
75b1d975 BZ	139	switch (vdev->via_config->udma_mask) {
	140	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	141	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	142	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	143	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	144	default: return;
1da177e4 LT	145	}
	146
	147	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	148	}
	149
	150	/**
	151	* via_set_drive - configure transfer mode
	152	* @drive: Drive to set up
	153	* @speed: desired speed
	154	*
	155	* via_set_drive() computes timing values configures the drive and
	156	* the chipset to a desired transfer mode. It also can be called
	157	* by upper layers.
	158	*/
	159
	160	static int via_set_drive(ide_drive_t *drive, u8 speed)
	161	{
	162	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
cd36beec	163	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
1da177e4 LT	164	struct ide_timing t, p;
	165	unsigned int T, UT;
	166
	167	if (speed != XFER_PIO_SLOW)
	168	ide_config_drive_speed(drive, speed);
	169
	170	T = 1000000000 / via_clock;
	171
75b1d975 BZ	172	switch (vdev->via_config->udma_mask) {
	173	case ATA_UDMA2: UT = T; break;
	174	case ATA_UDMA4: UT = T/2; break;
	175	case ATA_UDMA5: UT = T/3; break;
	176	case ATA_UDMA6: UT = T/4; break;
	177	default: UT = T;
1da177e4 LT	178	}
	179
	180	ide_timing_compute(drive, speed, &t, T, UT);
	181
	182	if (peer->present) {
	183	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	184	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	185	}
	186
7462cbff	187	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	188
	189	if (!drive->init_speed)
	190	drive->init_speed = speed;
	191	drive->current_speed = speed;
	192
	193	return 0;
	194	}
	195
	196	/**
	197	* via82cxxx_tune_drive - PIO setup
	198	* @drive: drive to set up
	199	* @pio: mode to use (255 for 'best possible')
	200	*
	201	* A callback from the upper layers for PIO-only tuning.
	202	*/
	203
	204	static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
	205	{
	206	if (pio == 255) {
75b1d975	207	via_set_drive(drive, ide_find_best_pio_mode(drive));
1da177e4 LT	208	return;
	209	}
	210
	211	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
	212	}
	213
	214	/**
	215	* via82cxxx_ide_dma_check - set up for DMA if possible
	216	* @drive: IDE drive to set up
	217	*
	218	* Set up the drive for the highest supported speed considering the
	219	* driver, controller and cable
	220	*/
	221
	222	static int via82cxxx_ide_dma_check (ide_drive_t *drive)
	223	{
75b1d975	224	u8 speed = ide_max_dma_mode(drive);
1da177e4	225
75b1d975 BZ	226	if (speed == 0)
75b1d975 BZ	227	speed = ide_find_best_pio_mode(drive);
1da177e4 LT	228
	229	via_set_drive(drive, speed);
	230
	231	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
3608b5d7 BZ	232	return 0;
	233
	234	return -1;
7462cbff DD	235	}
	236
	237	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	238	{
	239	struct via_isa_bridge *via_config;
	240	u8 t;
	241
	242	for (via_config = via_isa_bridges; via_config->id; via_config++)
652aa162	243	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	244	!!(via_config->flags & VIA_BAD_ID),
	245	via_config->id, NULL))) {
	246
	247	pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
	248	if (t >= via_config->rev_min &&
	249	t <= via_config->rev_max)
	250	break;
652aa162	251	pci_dev_put(*isa);
7462cbff DD	252	}
	253
	254	return via_config;
1da177e4 LT	255	}
1da177e4 LT	256
cd36beec BZ	257	/*
	258	* Check and handle 80-wire cable presence
	259	*/
	260	static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
	261	{
	262	int i;
	263
75b1d975 BZ	264	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	265	case ATA_UDMA4:
cd36beec BZ	266	for (i = 24; i >= 0; i -= 8)
	267	if (((u >> (i & 16)) & 8) &&
	268	((u >> i) & 0x20) &&
	269	(((u >> i) & 7) < 2)) {
	270	/*
	271	* 2x PCI clock and
	272	* UDMA w/ < 3T/cycle
	273	*/
	274	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	275	}
	276	break;
	277
75b1d975	278	case ATA_UDMA5:
cd36beec BZ	279	for (i = 24; i >= 0; i -= 8)
	280	if (((u >> i) & 0x10) \|\|
	281	(((u >> i) & 0x20) &&
	282	(((u >> i) & 7) < 4))) {
	283	/* BIOS 80-wire bit or
	284	* UDMA w/ < 60ns/cycle
	285	*/
	286	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	287	}
	288	break;
	289
75b1d975	290	case ATA_UDMA6:
cd36beec BZ	291	for (i = 24; i >= 0; i -= 8)
	292	if (((u >> i) & 0x10) \|\|
	293	(((u >> i) & 0x20) &&
	294	(((u >> i) & 7) < 6))) {
	295	/* BIOS 80-wire bit or
	296	* UDMA w/ < 60ns/cycle
	297	*/
	298	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	299	}
	300	break;
	301	}
	302	}
	303
1da177e4 LT	304	/**
	305	* init_chipset_via82cxxx - initialization handler
	306	* @dev: PCI device
	307	* @name: Name of interface
	308	*
	309	* The initialization callback. Here we determine the IDE chip type
	310	* and initialize its drive independent registers.
	311	*/
	312
f3718d3e	313	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	314	{
1da177e4 LT	315	struct pci_dev *isa = NULL;
cd36beec	316	struct via82cxxx_dev *vdev;
7462cbff	317	struct via_isa_bridge *via_config;
1da177e4	318	u8 t, v;
cd36beec BZ	319	u32 u;
	320
	321	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	322	if (!vdev) {
	323	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	324	return -ENOMEM;
	325	}
	326	pci_set_drvdata(dev, vdev);
1da177e4 LT	327
	328	/*
	329	* Find the ISA bridge to see how good the IDE is.
	330	*/
cd36beec	331	vdev->via_config = via_config = via_config_find(&isa);
23a1b2a7 AC	332
	333	/* We checked this earlier so if it fails here deeep badness
	334	is involved */
	335
	336	BUG_ON(!via_config->id);
1da177e4 LT	337
1da177e4 LT	338	/*
cd36beec	339	* Detect cable and configure Clk66
1da177e4	340	*/
cd36beec BZ	341	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	342
	343	via_cable_detect(vdev, u);
1da177e4	344
75b1d975	345	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	346	/* Enable Clk66 */
7462cbff DD	347	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	348	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	349	/* Would cause trouble on 596a and 686 */
1da177e4 LT	350	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	351	}
	352
	353	/*
	354	* Check whether interfaces are enabled.
	355	*/
	356
	357	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	358
	359	/*
	360	* Set up FIFO sizes and thresholds.
	361	*/
	362
	363	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	364
	365	/* Disable PREQ# till DDACK# */
	366	if (via_config->flags & VIA_BAD_PREQ) {
	367	/* Would crash on 586b rev 41 */
	368	t &= 0x7f;
	369	}
	370
	371	/* Fix FIFO split between channels */
	372	if (via_config->flags & VIA_SET_FIFO) {
	373	t &= (t & 0x9f);
	374	switch (v & 3) {
	375	case 2: t \|= 0x00; break; /* 16 on primary */
	376	case 1: t \|= 0x60; break; /* 16 on secondary */
	377	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	378	}
	379	}
	380
	381	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	382
	383	/*
	384	* Determine system bus clock.
	385	*/
	386
	387	via_clock = system_bus_clock() * 1000;
	388
	389	switch (via_clock) {
	390	case 33000: via_clock = 33333; break;
	391	case 37000: via_clock = 37500; break;
	392	case 41000: via_clock = 41666; break;
	393	}
	394
	395	if (via_clock < 20000 \|\| via_clock > 50000) {
	396	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	397	"impossible (%d), using 33 MHz instead.\n", via_clock);
	398	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	399	"to assume 80-wire cable.\n");
	400	via_clock = 33333;
	401	}
	402
	403	/*
	404	* Print the boot message.
	405	*/
	406
	407	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
75b1d975	408	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
1da177e4 LT	409	"controller on pci%s\n",
1da177e4 LT	410	via_config->name, t,
75b1d975 BZ	411	via_config->udma_mask ? "U" : "MW",
	412	via_dma[via_config->udma_mask ?
	413	(fls(via_config->udma_mask) - 1) : 0],
1da177e4 LT	414	pci_name(dev));
1da177e4 LT	415
652aa162	416	pci_dev_put(isa);
1da177e4 LT	417	return 0;
	418	}
	419
bdab00b7 BZ	420	/*
	421	* Cable special cases
	422	*/
	423
	424	static struct dmi_system_id cable_dmi_table[] = {
	425	{
	426	.ident = "Acer Ferrari 3400",
	427	.matches = {
	428	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	429	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	430	},
	431	},
	432	{ }
	433	};
	434
	435	static int via_cable_override(void)
	436	{
	437	/* Systems by DMI */
	438	if (dmi_check_system(cable_dmi_table))
	439	return 1;
	440	return 0;
	441	}
	442
	443	static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
	444	{
	445	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	446
	447	if (via_cable_override())
	448	return ATA_CBL_PATA40_SHORT;
	449
	450	if ((vdev->via_80w >> hwif->channel) & 1)
	451	return ATA_CBL_PATA80;
	452	else
	453	return ATA_CBL_PATA40;
	454	}
	455
f3718d3e	456	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	457	{
cd36beec	458	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	459	int i;
	460
	461	hwif->autodma = 0;
	462
	463	hwif->tuneproc = &via82cxxx_tune_drive;
	464	hwif->speedproc = &via_set_drive;
	465
	466
74a9d5f1	467	#ifdef CONFIG_PPC_CHRP
e8222502	468	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
1da177e4 LT	469	hwif->irq = hwif->channel ? 15 : 14;
	470	}
	471	#endif
	472
	473	for (i = 0; i < 2; i++) {
	474	hwif->drives[i].io_32bit = 1;
7462cbff	475	hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
1da177e4 LT	476	hwif->drives[i].autotune = 1;
	477	hwif->drives[i].dn = hwif->channel * 2 + i;
	478	}
	479
	480	if (!hwif->dma_base)
	481	return;
	482
	483	hwif->atapi_dma = 1;
75b1d975 BZ	484
75b1d975 BZ	485	hwif->ultra_mask = vdev->via_config->udma_mask;
1da177e4 LT	486	hwif->mwdma_mask = 0x07;
	487	hwif->swdma_mask = 0x07;
	488
bdab00b7 BZ	489	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
bdab00b7 BZ	490	hwif->cbl = via82cxxx_cable_detect(hwif);
49521f97	491
1da177e4 LT	492	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	493	if (!noautodma)
	494	hwif->autodma = 1;
	495	hwif->drives[0].autodma = hwif->autodma;
	496	hwif->drives[1].autodma = hwif->autodma;
	497	}
	498
4f1d774a MK	499	static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	500	{ /* 0 */
	501	.name = "VP_IDE",
	502	.init_chipset = init_chipset_via82cxxx,
	503	.init_hwif = init_hwif_via82cxxx,
	504	.channels = 2,
	505	.autodma = NOAUTODMA,
	506	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
	507	.bootable = ON_BOARD
	508	},{ /* 1 */
	509	.name = "VP_IDE",
	510	.init_chipset = init_chipset_via82cxxx,
	511	.init_hwif = init_hwif_via82cxxx,
	512	.channels = 2,
	513	.autodma = AUTODMA,
	514	.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
	515	.bootable = ON_BOARD,
	516	}
1da177e4 LT	517	};
	518
	519	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	520	{
23a1b2a7 AC	521	struct pci_dev *isa = NULL;
	522	struct via_isa_bridge *via_config;
	523	/*
	524	* Find the ISA bridge and check we know what it is.
	525	*/
	526	via_config = via_config_find(&isa);
	527	pci_dev_put(isa);
	528	if (!via_config->id) {
	529	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	530	return -ENODEV;
	531	}
4f1d774a	532	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
1da177e4 LT	533	}
	534
	535	static struct pci_device_id via_pci_tbl[] = {
	536	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	537	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
4f1d774a	538	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
e0b874df	539	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1da177e4 LT	540	{ 0, },
	541	};
	542	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	543
	544	static struct pci_driver driver = {
	545	.name = "VIA_IDE",
	546	.id_table = via_pci_tbl,
	547	.probe = via_init_one,
	548	};
	549
82ab1eec	550	static int __init via_ide_init(void)
1da177e4 LT	551	{
	552	return ide_pci_register_driver(&driver);
	553	}
	554
	555	module_init(via_ide_init);
	556
	557	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	558	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	559	MODULE_LICENSE("GPL");