Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
58e47bb1 | 3 | * Version 3.47 |
1da177e4 LT |
4 | * |
5 | * VIA IDE driver for Linux. Supported southbridges: | |
6 | * | |
7 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
8 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 9 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
10 | * |
11 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
75b1d975 | 12 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
13 | * |
14 | * Based on the work of: | |
15 | * Michel Aubry | |
16 | * Jeff Garzik | |
17 | * Andre Hedrick | |
18 | * | |
19 | * Documentation: | |
20 | * Obsolete device documentation publically available from via.com.tw | |
21 | * Current device documentation available under NDA only | |
22 | */ | |
23 | ||
24 | /* | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License version 2 as published by | |
27 | * the Free Software Foundation. | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/blkdev.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ide.h> | |
bdab00b7 BZ |
37 | #include <linux/dmi.h> |
38 | ||
1da177e4 LT |
39 | #include <asm/io.h> |
40 | ||
74a9d5f1 | 41 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
42 | #include <asm/processor.h> |
43 | #endif | |
44 | ||
45 | #include "ide-timing.h" | |
46 | ||
1da177e4 LT |
47 | #define VIA_IDE_ENABLE 0x40 |
48 | #define VIA_IDE_CONFIG 0x41 | |
49 | #define VIA_FIFO_CONFIG 0x43 | |
50 | #define VIA_MISC_1 0x44 | |
51 | #define VIA_MISC_2 0x45 | |
52 | #define VIA_MISC_3 0x46 | |
53 | #define VIA_DRIVE_TIMING 0x48 | |
54 | #define VIA_8BIT_TIMING 0x4e | |
55 | #define VIA_ADDRESS_SETUP 0x4c | |
56 | #define VIA_UDMA_TIMING 0x50 | |
57 | ||
75b1d975 BZ |
58 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
59 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
60 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
61 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
62 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
63 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
1da177e4 LT |
64 | |
65 | /* | |
66 | * VIA SouthBridge chips. | |
67 | */ | |
68 | ||
69 | static struct via_isa_bridge { | |
70 | char *name; | |
71 | u16 id; | |
72 | u8 rev_min; | |
73 | u8 rev_max; | |
75b1d975 BZ |
74 | u8 udma_mask; |
75 | u8 flags; | |
1da177e4 | 76 | } via_isa_bridges[] = { |
b311ec4a | 77 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
78 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
79 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
80 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
81 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
82 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
83 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
84 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
85 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
86 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
87 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
88 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
89 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
90 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
91 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
92 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
93 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
94 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
95 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
96 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
97 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
98 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
99 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
100 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
1da177e4 LT |
101 | { NULL } |
102 | }; | |
103 | ||
1da177e4 | 104 | static unsigned int via_clock; |
75b1d975 | 105 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 106 | |
7462cbff DD |
107 | struct via82cxxx_dev |
108 | { | |
109 | struct via_isa_bridge *via_config; | |
110 | unsigned int via_80w; | |
111 | }; | |
112 | ||
1da177e4 LT |
113 | /** |
114 | * via_set_speed - write timing registers | |
115 | * @dev: PCI device | |
116 | * @dn: device | |
117 | * @timing: IDE timing data to use | |
118 | * | |
119 | * via_set_speed writes timing values to the chipset registers | |
120 | */ | |
121 | ||
7462cbff | 122 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 123 | { |
7462cbff | 124 | struct pci_dev *dev = hwif->pci_dev; |
cd36beec | 125 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
126 | u8 t; |
127 | ||
7462cbff | 128 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 LT |
129 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
130 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
131 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); | |
132 | } | |
133 | ||
134 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
135 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
136 | ||
137 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
138 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
139 | ||
75b1d975 BZ |
140 | switch (vdev->via_config->udma_mask) { |
141 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | |
142 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
143 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
144 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
145 | default: return; | |
1da177e4 LT |
146 | } |
147 | ||
148 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
149 | } | |
150 | ||
151 | /** | |
152 | * via_set_drive - configure transfer mode | |
153 | * @drive: Drive to set up | |
154 | * @speed: desired speed | |
155 | * | |
156 | * via_set_drive() computes timing values configures the drive and | |
157 | * the chipset to a desired transfer mode. It also can be called | |
158 | * by upper layers. | |
159 | */ | |
160 | ||
161 | static int via_set_drive(ide_drive_t *drive, u8 speed) | |
162 | { | |
163 | ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1); | |
cd36beec | 164 | struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev); |
1da177e4 LT |
165 | struct ide_timing t, p; |
166 | unsigned int T, UT; | |
167 | ||
168 | if (speed != XFER_PIO_SLOW) | |
169 | ide_config_drive_speed(drive, speed); | |
170 | ||
171 | T = 1000000000 / via_clock; | |
172 | ||
75b1d975 BZ |
173 | switch (vdev->via_config->udma_mask) { |
174 | case ATA_UDMA2: UT = T; break; | |
175 | case ATA_UDMA4: UT = T/2; break; | |
176 | case ATA_UDMA5: UT = T/3; break; | |
177 | case ATA_UDMA6: UT = T/4; break; | |
178 | default: UT = T; | |
1da177e4 LT |
179 | } |
180 | ||
181 | ide_timing_compute(drive, speed, &t, T, UT); | |
182 | ||
183 | if (peer->present) { | |
184 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
185 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
186 | } | |
187 | ||
7462cbff | 188 | via_set_speed(HWIF(drive), drive->dn, &t); |
1da177e4 LT |
189 | |
190 | if (!drive->init_speed) | |
191 | drive->init_speed = speed; | |
192 | drive->current_speed = speed; | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * via82cxxx_tune_drive - PIO setup | |
199 | * @drive: drive to set up | |
200 | * @pio: mode to use (255 for 'best possible') | |
201 | * | |
202 | * A callback from the upper layers for PIO-only tuning. | |
203 | */ | |
204 | ||
205 | static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio) | |
206 | { | |
6a824c92 BZ |
207 | if (pio == 255) |
208 | pio = ide_get_best_pio_mode(drive, 255, 5); | |
1da177e4 LT |
209 | |
210 | via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5)); | |
211 | } | |
212 | ||
213 | /** | |
214 | * via82cxxx_ide_dma_check - set up for DMA if possible | |
215 | * @drive: IDE drive to set up | |
216 | * | |
217 | * Set up the drive for the highest supported speed considering the | |
218 | * driver, controller and cable | |
219 | */ | |
220 | ||
221 | static int via82cxxx_ide_dma_check (ide_drive_t *drive) | |
222 | { | |
75b1d975 | 223 | u8 speed = ide_max_dma_mode(drive); |
1da177e4 | 224 | |
6a824c92 BZ |
225 | if (speed == 0) { |
226 | via82cxxx_tune_drive(drive, 255); | |
227 | return -1; | |
228 | } | |
1da177e4 LT |
229 | |
230 | via_set_drive(drive, speed); | |
231 | ||
6a824c92 | 232 | if (drive->autodma) |
3608b5d7 BZ |
233 | return 0; |
234 | ||
235 | return -1; | |
7462cbff DD |
236 | } |
237 | ||
238 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) | |
239 | { | |
240 | struct via_isa_bridge *via_config; | |
7462cbff DD |
241 | |
242 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 243 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
244 | !!(via_config->flags & VIA_BAD_ID), |
245 | via_config->id, NULL))) { | |
246 | ||
44c10138 AK |
247 | if ((*isa)->revision >= via_config->rev_min && |
248 | (*isa)->revision <= via_config->rev_max) | |
7462cbff | 249 | break; |
652aa162 | 250 | pci_dev_put(*isa); |
7462cbff DD |
251 | } |
252 | ||
253 | return via_config; | |
1da177e4 LT |
254 | } |
255 | ||
cd36beec BZ |
256 | /* |
257 | * Check and handle 80-wire cable presence | |
258 | */ | |
259 | static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u) | |
260 | { | |
261 | int i; | |
262 | ||
75b1d975 BZ |
263 | switch (vdev->via_config->udma_mask) { |
264 | case ATA_UDMA4: | |
cd36beec BZ |
265 | for (i = 24; i >= 0; i -= 8) |
266 | if (((u >> (i & 16)) & 8) && | |
267 | ((u >> i) & 0x20) && | |
268 | (((u >> i) & 7) < 2)) { | |
269 | /* | |
270 | * 2x PCI clock and | |
271 | * UDMA w/ < 3T/cycle | |
272 | */ | |
273 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
274 | } | |
275 | break; | |
276 | ||
75b1d975 | 277 | case ATA_UDMA5: |
cd36beec BZ |
278 | for (i = 24; i >= 0; i -= 8) |
279 | if (((u >> i) & 0x10) || | |
280 | (((u >> i) & 0x20) && | |
281 | (((u >> i) & 7) < 4))) { | |
282 | /* BIOS 80-wire bit or | |
283 | * UDMA w/ < 60ns/cycle | |
284 | */ | |
285 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
286 | } | |
287 | break; | |
288 | ||
75b1d975 | 289 | case ATA_UDMA6: |
cd36beec BZ |
290 | for (i = 24; i >= 0; i -= 8) |
291 | if (((u >> i) & 0x10) || | |
292 | (((u >> i) & 0x20) && | |
293 | (((u >> i) & 7) < 6))) { | |
294 | /* BIOS 80-wire bit or | |
295 | * UDMA w/ < 60ns/cycle | |
296 | */ | |
297 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
298 | } | |
299 | break; | |
300 | } | |
301 | } | |
302 | ||
1da177e4 LT |
303 | /** |
304 | * init_chipset_via82cxxx - initialization handler | |
305 | * @dev: PCI device | |
306 | * @name: Name of interface | |
307 | * | |
308 | * The initialization callback. Here we determine the IDE chip type | |
309 | * and initialize its drive independent registers. | |
310 | */ | |
311 | ||
f3718d3e | 312 | static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name) |
1da177e4 LT |
313 | { |
314 | struct pci_dev *isa = NULL; | |
cd36beec | 315 | struct via82cxxx_dev *vdev; |
7462cbff | 316 | struct via_isa_bridge *via_config; |
1da177e4 | 317 | u8 t, v; |
cd36beec BZ |
318 | u32 u; |
319 | ||
320 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); | |
321 | if (!vdev) { | |
322 | printk(KERN_ERR "VP_IDE: out of memory :(\n"); | |
323 | return -ENOMEM; | |
324 | } | |
325 | pci_set_drvdata(dev, vdev); | |
1da177e4 LT |
326 | |
327 | /* | |
328 | * Find the ISA bridge to see how good the IDE is. | |
329 | */ | |
cd36beec | 330 | vdev->via_config = via_config = via_config_find(&isa); |
23a1b2a7 AC |
331 | |
332 | /* We checked this earlier so if it fails here deeep badness | |
333 | is involved */ | |
334 | ||
335 | BUG_ON(!via_config->id); | |
1da177e4 LT |
336 | |
337 | /* | |
cd36beec | 338 | * Detect cable and configure Clk66 |
1da177e4 | 339 | */ |
cd36beec BZ |
340 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
341 | ||
342 | via_cable_detect(vdev, u); | |
1da177e4 | 343 | |
75b1d975 | 344 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 345 | /* Enable Clk66 */ |
7462cbff DD |
346 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
347 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 348 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
349 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
350 | } | |
351 | ||
352 | /* | |
353 | * Check whether interfaces are enabled. | |
354 | */ | |
355 | ||
356 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
357 | ||
358 | /* | |
359 | * Set up FIFO sizes and thresholds. | |
360 | */ | |
361 | ||
362 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
363 | ||
364 | /* Disable PREQ# till DDACK# */ | |
365 | if (via_config->flags & VIA_BAD_PREQ) { | |
366 | /* Would crash on 586b rev 41 */ | |
367 | t &= 0x7f; | |
368 | } | |
369 | ||
370 | /* Fix FIFO split between channels */ | |
371 | if (via_config->flags & VIA_SET_FIFO) { | |
372 | t &= (t & 0x9f); | |
373 | switch (v & 3) { | |
374 | case 2: t |= 0x00; break; /* 16 on primary */ | |
375 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
376 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
377 | } | |
378 | } | |
379 | ||
380 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
381 | ||
382 | /* | |
383 | * Determine system bus clock. | |
384 | */ | |
385 | ||
386 | via_clock = system_bus_clock() * 1000; | |
387 | ||
388 | switch (via_clock) { | |
389 | case 33000: via_clock = 33333; break; | |
390 | case 37000: via_clock = 37500; break; | |
391 | case 41000: via_clock = 41666; break; | |
392 | } | |
393 | ||
394 | if (via_clock < 20000 || via_clock > 50000) { | |
395 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
396 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
397 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
398 | "to assume 80-wire cable.\n"); | |
399 | via_clock = 33333; | |
400 | } | |
401 | ||
402 | /* | |
403 | * Print the boot message. | |
404 | */ | |
405 | ||
75b1d975 | 406 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s " |
1da177e4 | 407 | "controller on pci%s\n", |
44c10138 | 408 | via_config->name, isa->revision, |
75b1d975 BZ |
409 | via_config->udma_mask ? "U" : "MW", |
410 | via_dma[via_config->udma_mask ? | |
411 | (fls(via_config->udma_mask) - 1) : 0], | |
1da177e4 LT |
412 | pci_name(dev)); |
413 | ||
652aa162 | 414 | pci_dev_put(isa); |
1da177e4 LT |
415 | return 0; |
416 | } | |
417 | ||
bdab00b7 BZ |
418 | /* |
419 | * Cable special cases | |
420 | */ | |
421 | ||
422 | static struct dmi_system_id cable_dmi_table[] = { | |
423 | { | |
424 | .ident = "Acer Ferrari 3400", | |
425 | .matches = { | |
426 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
427 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
428 | }, | |
429 | }, | |
430 | { } | |
431 | }; | |
432 | ||
58e47bb1 | 433 | static int via_cable_override(struct pci_dev *pdev) |
bdab00b7 BZ |
434 | { |
435 | /* Systems by DMI */ | |
436 | if (dmi_check_system(cable_dmi_table)) | |
437 | return 1; | |
58e47bb1 BZ |
438 | |
439 | /* Arima W730-K8/Targa Visionary 811/... */ | |
440 | if (pdev->subsystem_vendor == 0x161F && | |
441 | pdev->subsystem_device == 0x2032) | |
442 | return 1; | |
443 | ||
bdab00b7 BZ |
444 | return 0; |
445 | } | |
446 | ||
447 | static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif) | |
448 | { | |
58e47bb1 BZ |
449 | struct pci_dev *pdev = hwif->pci_dev; |
450 | struct via82cxxx_dev *vdev = pci_get_drvdata(pdev); | |
bdab00b7 | 451 | |
58e47bb1 | 452 | if (via_cable_override(pdev)) |
bdab00b7 BZ |
453 | return ATA_CBL_PATA40_SHORT; |
454 | ||
455 | if ((vdev->via_80w >> hwif->channel) & 1) | |
456 | return ATA_CBL_PATA80; | |
457 | else | |
458 | return ATA_CBL_PATA40; | |
459 | } | |
460 | ||
f3718d3e | 461 | static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif) |
1da177e4 | 462 | { |
cd36beec | 463 | struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev); |
1da177e4 LT |
464 | int i; |
465 | ||
466 | hwif->autodma = 0; | |
467 | ||
468 | hwif->tuneproc = &via82cxxx_tune_drive; | |
469 | hwif->speedproc = &via_set_drive; | |
470 | ||
471 | ||
74a9d5f1 | 472 | #ifdef CONFIG_PPC_CHRP |
e8222502 | 473 | if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) { |
1da177e4 LT |
474 | hwif->irq = hwif->channel ? 15 : 14; |
475 | } | |
476 | #endif | |
477 | ||
478 | for (i = 0; i < 2; i++) { | |
479 | hwif->drives[i].io_32bit = 1; | |
7462cbff | 480 | hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1; |
1da177e4 LT |
481 | hwif->drives[i].autotune = 1; |
482 | hwif->drives[i].dn = hwif->channel * 2 + i; | |
483 | } | |
484 | ||
485 | if (!hwif->dma_base) | |
486 | return; | |
487 | ||
488 | hwif->atapi_dma = 1; | |
75b1d975 BZ |
489 | |
490 | hwif->ultra_mask = vdev->via_config->udma_mask; | |
1da177e4 LT |
491 | hwif->mwdma_mask = 0x07; |
492 | hwif->swdma_mask = 0x07; | |
493 | ||
bdab00b7 BZ |
494 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
495 | hwif->cbl = via82cxxx_cable_detect(hwif); | |
49521f97 | 496 | |
1da177e4 LT |
497 | hwif->ide_dma_check = &via82cxxx_ide_dma_check; |
498 | if (!noautodma) | |
499 | hwif->autodma = 1; | |
500 | hwif->drives[0].autodma = hwif->autodma; | |
501 | hwif->drives[1].autodma = hwif->autodma; | |
502 | } | |
503 | ||
4f1d774a MK |
504 | static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = { |
505 | { /* 0 */ | |
506 | .name = "VP_IDE", | |
507 | .init_chipset = init_chipset_via82cxxx, | |
508 | .init_hwif = init_hwif_via82cxxx, | |
4f1d774a MK |
509 | .autodma = NOAUTODMA, |
510 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, | |
6a824c92 BZ |
511 | .bootable = ON_BOARD, |
512 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | |
513 | | IDE_HFLAG_PIO_NO_DOWNGRADE, | |
4099d143 | 514 | .pio_mask = ATA_PIO5, |
4f1d774a MK |
515 | },{ /* 1 */ |
516 | .name = "VP_IDE", | |
517 | .init_chipset = init_chipset_via82cxxx, | |
518 | .init_hwif = init_hwif_via82cxxx, | |
4f1d774a MK |
519 | .autodma = AUTODMA, |
520 | .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, | |
521 | .bootable = ON_BOARD, | |
6a824c92 BZ |
522 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
523 | | IDE_HFLAG_PIO_NO_DOWNGRADE, | |
4099d143 | 524 | .pio_mask = ATA_PIO5, |
4f1d774a | 525 | } |
1da177e4 LT |
526 | }; |
527 | ||
528 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
529 | { | |
23a1b2a7 AC |
530 | struct pci_dev *isa = NULL; |
531 | struct via_isa_bridge *via_config; | |
532 | /* | |
533 | * Find the ISA bridge and check we know what it is. | |
534 | */ | |
535 | via_config = via_config_find(&isa); | |
536 | pci_dev_put(isa); | |
537 | if (!via_config->id) { | |
538 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
539 | return -ENODEV; | |
540 | } | |
4f1d774a | 541 | return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]); |
1da177e4 LT |
542 | } |
543 | ||
544 | static struct pci_device_id via_pci_tbl[] = { | |
545 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
546 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
4f1d774a | 547 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
e0b874df | 548 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1da177e4 LT |
549 | { 0, }, |
550 | }; | |
551 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
552 | ||
553 | static struct pci_driver driver = { | |
554 | .name = "VIA_IDE", | |
555 | .id_table = via_pci_tbl, | |
556 | .probe = via_init_one, | |
557 | }; | |
558 | ||
82ab1eec | 559 | static int __init via_ide_init(void) |
1da177e4 LT |
560 | { |
561 | return ide_pci_register_driver(&driver); | |
562 | } | |
563 | ||
564 | module_init(via_ide_init); | |
565 | ||
566 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
567 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
568 | MODULE_LICENSE("GPL"); |