[deliverable/linux.git] / drivers / ide / pci / via82cxxx.c

/*
 *
 * Version 3.38
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#ifdef CONFIG_PPC_MULTIPLATFORM
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define DISPLAY_VIA_TIMINGS

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_UDMA		0x007
#define VIA_UDMA_NONE		0x000
#define VIA_UDMA_33		0x001
#define VIA_UDMA_66		0x002
#define VIA_UDMA_100		0x003
#define VIA_UDMA_133		0x004
#define VIA_BAD_PREQ		0x010	/* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x020	/* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x040	/* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x080	/* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x100	/* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x200	/* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u16 flags;
} via_isa_bridges[] = {
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, VIA_UDMA_100 },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, VIA_UDMA_100 },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->flags & VIA_UDMA) {
		case VIA_UDMA_33:  t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
		case VIA_UDMA_66:  t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
		case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
		case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
		default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the drive and
 *	the chipset to a desired transfer mode. It also can be called
 *	by upper layers.
 */

static int via_set_drive(ide_drive_t *drive, u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct via82cxxx_dev *vdev = ide_get_hwifdata(drive->hwif);
	struct ide_timing t, p;
	unsigned int T, UT;

	if (speed != XFER_PIO_SLOW)
		ide_config_drive_speed(drive, speed);

	T = 1000000000 / via_clock;

	switch (vdev->via_config->flags & VIA_UDMA) {
		case VIA_UDMA_33:   UT = T;   break;
		case VIA_UDMA_66:   UT = T/2; break;
		case VIA_UDMA_100:  UT = T/3; break;
		case VIA_UDMA_133:  UT = T/4; break;
		default: UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);

	if (!drive->init_speed)
		drive->init_speed = speed;
	drive->current_speed = speed;

	return 0;
}

/**
 *	via82cxxx_tune_drive	-	PIO setup
 *	@drive: drive to set up
 *	@pio: mode to use (255 for 'best possible')
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
{
	if (pio == 255) {
		via_set_drive(drive,
			ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
		return;
	}

	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
}

/**
 *	via82cxxx_ide_dma_check		-	set up for DMA if possible
 *	@drive: IDE drive to set up
 *
 *	Set up the drive for the highest supported speed considering the
 *	driver, controller and cable
 */
 
static int via82cxxx_ide_dma_check (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
	u16 w80 = hwif->udma_four;

	u16 speed = ide_find_best_mode(drive,
		XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
		(vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
		(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));

	via_set_drive(drive, speed);

	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
		return hwif->ide_dma_on(drive);
	return hwif->ide_dma_off_quietly(drive);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;
	u8 t;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_find_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
			if (t >= via_config->rev_min &&
			    t <= via_config->rev_max)
				break;
		}

	return via_config;
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	u8 t, v;
	unsigned int u;

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	via_config = via_config_find(&isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}

	/*
	 * Setup or disable Clk66 if appropriate
	 */

	if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) {
		/* Enable Clk66 */
		pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
		"controller on pci%s\n",
		via_config->name, t,
		via_dma[via_config->flags & VIA_UDMA],
		pci_name(dev));

	return 0;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct pci_dev *dev, struct via82cxxx_dev *vdev)
{
	unsigned int u;
	int i;
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	switch (vdev->via_config->flags & VIA_UDMA) {

		case VIA_UDMA_66:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case VIA_UDMA_100:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case VIA_UDMA_133:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

	}
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	struct via82cxxx_dev *vdev = kmalloc(sizeof(struct via82cxxx_dev),
		GFP_KERNEL);
	struct pci_dev *isa = NULL;
	int i;

	if (vdev == NULL) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return;
	}

	memset(vdev, 0, sizeof(struct via82cxxx_dev));
	ide_set_hwifdata(hwif, vdev);

	vdev->via_config = via_config_find(&isa);
	via_cable_detect(hwif->pci_dev, vdev);

	hwif->autodma = 0;

	hwif->tuneproc = &via82cxxx_tune_drive;
	hwif->speedproc = &via_set_drive;


#if defined(CONFIG_PPC_CHRP) && defined(CONFIG_PPC32)
	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
		hwif->irq = hwif->channel ? 15 : 14;
	}
#endif

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x7f;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;

	if (!hwif->udma_four)
		hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= NOAUTODMA,
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
		.bootable	= ON_BOARD
	},{	/* 1 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
		.bootable	= ON_BOARD,
	}
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
}

static struct pci_device_id via_pci_tbl[] = {
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	*
	3	* Version 3.38
	4	*
	5	* VIA IDE driver for Linux. Supported southbridges:
	6	*
	7	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	8	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
	9	* vt8235, vt8237
	10	*
	11	* Copyright (c) 2000-2002 Vojtech Pavlik
	12	*
	13	* Based on the work of:
	14	* Michel Aubry
	15	* Jeff Garzik
	16	* Andre Hedrick
	17	*
	18	* Documentation:
	19	* Obsolete device documentation publically available from via.com.tw
	20	* Current device documentation available under NDA only
	21	*/
	22
	23	/*
	24	* This program is free software; you can redistribute it and/or modify it
	25	* under the terms of the GNU General Public License version 2 as published by
	26	* the Free Software Foundation.
	27	*/
	28
1da177e4 LT	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/ioport.h>
	32	#include <linux/blkdev.h>
	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/ide.h>
	36	#include <asm/io.h>
	37
	38	#ifdef CONFIG_PPC_MULTIPLATFORM
	39	#include <asm/processor.h>
	40	#endif
	41
	42	#include "ide-timing.h"
	43
	44	#define DISPLAY_VIA_TIMINGS
	45
	46	#define VIA_IDE_ENABLE 0x40
	47	#define VIA_IDE_CONFIG 0x41
	48	#define VIA_FIFO_CONFIG 0x43
	49	#define VIA_MISC_1 0x44
	50	#define VIA_MISC_2 0x45
	51	#define VIA_MISC_3 0x46
	52	#define VIA_DRIVE_TIMING 0x48
	53	#define VIA_8BIT_TIMING 0x4e
	54	#define VIA_ADDRESS_SETUP 0x4c
	55	#define VIA_UDMA_TIMING 0x50
	56
	57	#define VIA_UDMA 0x007
	58	#define VIA_UDMA_NONE 0x000
	59	#define VIA_UDMA_33 0x001
	60	#define VIA_UDMA_66 0x002
	61	#define VIA_UDMA_100 0x003
	62	#define VIA_UDMA_133 0x004
	63	#define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
	64	#define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
	65	#define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
	66	#define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
	67	#define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
	68	#define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
	69
	70	/*
	71	* VIA SouthBridge chips.
	72	*/
	73
	74	static struct via_isa_bridge {
	75	char *name;
	76	u16 id;
	77	u8 rev_min;
	78	u8 rev_max;
	79	u16 flags;
	80	} via_isa_bridges[] = {
4f1d774a	81	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
ceef833b	82	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
1da177e4 LT	83	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	84	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	85	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	86	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
	87	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
	88	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
	89	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
	90	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
	91	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	92	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
	93	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	94	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 \| VIA_SET_FIFO },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 \| VIA_SET_FIFO \| VIA_BAD_PREQ },
	96	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 \| VIA_SET_FIFO },
	97	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 \| VIA_SET_FIFO },
	98	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE \| VIA_SET_FIFO },
	99	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK },
	100	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
	101	{ NULL }
	102	};
	103
1da177e4 LT	104	static unsigned int via_clock;
	105	static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
	106
7462cbff DD	107	struct via82cxxx_dev
	108	{
	109	struct via_isa_bridge *via_config;
	110	unsigned int via_80w;
	111	};
	112
1da177e4 LT	113	/**
	114	* via_set_speed - write timing registers
	115	* @dev: PCI device
	116	* @dn: device
	117	* @timing: IDE timing data to use
	118	*
	119	* via_set_speed writes timing values to the chipset registers
	120	*/
	121
7462cbff	122	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	123	{
7462cbff DD	124	struct pci_dev *dev = hwif->pci_dev;
7462cbff DD	125	struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
1da177e4 LT	126	u8 t;
1da177e4 LT	127
7462cbff	128	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	129	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	130	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	131	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	132	}
	133
	134	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	135	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	136
	137	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	138	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	139
7462cbff	140	switch (vdev->via_config->flags & VIA_UDMA) {
1da177e4 LT	141	case VIA_UDMA_33: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	142	case VIA_UDMA_66: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	143	case VIA_UDMA_100: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	144	case VIA_UDMA_133: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	145	default: return;
	146	}
	147
	148	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	149	}
	150
	151	/**
	152	* via_set_drive - configure transfer mode
	153	* @drive: Drive to set up
	154	* @speed: desired speed
	155	*
	156	* via_set_drive() computes timing values configures the drive and
	157	* the chipset to a desired transfer mode. It also can be called
	158	* by upper layers.
	159	*/
	160
	161	static int via_set_drive(ide_drive_t *drive, u8 speed)
	162	{
	163	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
7462cbff	164	struct via82cxxx_dev *vdev = ide_get_hwifdata(drive->hwif);
1da177e4 LT	165	struct ide_timing t, p;
	166	unsigned int T, UT;
	167
	168	if (speed != XFER_PIO_SLOW)
	169	ide_config_drive_speed(drive, speed);
	170
	171	T = 1000000000 / via_clock;
	172
7462cbff	173	switch (vdev->via_config->flags & VIA_UDMA) {
1da177e4 LT	174	case VIA_UDMA_33: UT = T; break;
	175	case VIA_UDMA_66: UT = T/2; break;
	176	case VIA_UDMA_100: UT = T/3; break;
	177	case VIA_UDMA_133: UT = T/4; break;
	178	default: UT = T;
	179	}
	180
	181	ide_timing_compute(drive, speed, &t, T, UT);
	182
	183	if (peer->present) {
	184	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	185	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	186	}
	187
7462cbff	188	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	189
	190	if (!drive->init_speed)
	191	drive->init_speed = speed;
	192	drive->current_speed = speed;
	193
	194	return 0;
	195	}
	196
	197	/**
	198	* via82cxxx_tune_drive - PIO setup
	199	* @drive: drive to set up
	200	* @pio: mode to use (255 for 'best possible')
	201	*
	202	* A callback from the upper layers for PIO-only tuning.
	203	*/
	204
	205	static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
	206	{
	207	if (pio == 255) {
	208	via_set_drive(drive,
	209	ide_find_best_mode(drive, XFER_PIO \| XFER_EPIO));
	210	return;
	211	}
	212
	213	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
	214	}
	215
	216	/**
	217	* via82cxxx_ide_dma_check - set up for DMA if possible
	218	* @drive: IDE drive to set up
	219	*
	220	* Set up the drive for the highest supported speed considering the
	221	* driver, controller and cable
	222	*/
	223
	224	static int via82cxxx_ide_dma_check (ide_drive_t *drive)
	225	{
7462cbff DD	226	ide_hwif_t *hwif = HWIF(drive);
	227	struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
	228	u16 w80 = hwif->udma_four;
1da177e4 LT	229
	230	u16 speed = ide_find_best_mode(drive,
	231	XFER_PIO \| XFER_EPIO \| XFER_SWDMA \| XFER_MWDMA \|
7462cbff DD	232	(vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) \|
	233	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) \|
	234	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) \|
	235	(w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
1da177e4 LT	236
	237	via_set_drive(drive, speed);
	238
	239	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
7462cbff DD	240	return hwif->ide_dma_on(drive);
	241	return hwif->ide_dma_off_quietly(drive);
	242	}
	243
	244	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	245	{
	246	struct via_isa_bridge *via_config;
	247	u8 t;
	248
	249	for (via_config = via_isa_bridges; via_config->id; via_config++)
	250	if ((*isa = pci_find_device(PCI_VENDOR_ID_VIA +
	251	!!(via_config->flags & VIA_BAD_ID),
	252	via_config->id, NULL))) {
	253
	254	pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
	255	if (t >= via_config->rev_min &&
	256	t <= via_config->rev_max)
	257	break;
	258	}
	259
	260	return via_config;
1da177e4 LT	261	}
	262
	263	/**
	264	* init_chipset_via82cxxx - initialization handler
	265	* @dev: PCI device
	266	* @name: Name of interface
	267	*
	268	* The initialization callback. Here we determine the IDE chip type
	269	* and initialize its drive independent registers.
	270	*/
	271
f3718d3e	272	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	273	{
1da177e4 LT	274	struct pci_dev *isa = NULL;
7462cbff	275	struct via_isa_bridge *via_config;
1da177e4 LT	276	u8 t, v;
1da177e4 LT	277	unsigned int u;
1da177e4 LT	278
	279	/*
	280	* Find the ISA bridge to see how good the IDE is.
	281	*/
7462cbff	282	via_config = via_config_find(&isa);
1da177e4 LT	283	if (!via_config->id) {
	284	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	285	return -ENODEV;
	286	}
	287
	288	/*
7462cbff	289	* Setup or disable Clk66 if appropriate
1da177e4 LT	290	*/
1da177e4 LT	291
7462cbff DD	292	if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) {
	293	/* Enable Clk66 */
	294	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	295	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
	296	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4 LT	297	/* Would cause trouble on 596a and 686 */
	298	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	299	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	300	}
	301
	302	/*
	303	* Check whether interfaces are enabled.
	304	*/
	305
	306	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	307
	308	/*
	309	* Set up FIFO sizes and thresholds.
	310	*/
	311
	312	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	313
	314	/* Disable PREQ# till DDACK# */
	315	if (via_config->flags & VIA_BAD_PREQ) {
	316	/* Would crash on 586b rev 41 */
	317	t &= 0x7f;
	318	}
	319
	320	/* Fix FIFO split between channels */
	321	if (via_config->flags & VIA_SET_FIFO) {
	322	t &= (t & 0x9f);
	323	switch (v & 3) {
	324	case 2: t \|= 0x00; break; /* 16 on primary */
	325	case 1: t \|= 0x60; break; /* 16 on secondary */
	326	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	327	}
	328	}
	329
	330	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	331
	332	/*
	333	* Determine system bus clock.
	334	*/
	335
	336	via_clock = system_bus_clock() * 1000;
	337
	338	switch (via_clock) {
	339	case 33000: via_clock = 33333; break;
	340	case 37000: via_clock = 37500; break;
	341	case 41000: via_clock = 41666; break;
	342	}
	343
	344	if (via_clock < 20000 \|\| via_clock > 50000) {
	345	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	346	"impossible (%d), using 33 MHz instead.\n", via_clock);
	347	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	348	"to assume 80-wire cable.\n");
	349	via_clock = 33333;
	350	}
	351
	352	/*
	353	* Print the boot message.
	354	*/
	355
	356	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	357	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
	358	"controller on pci%s\n",
	359	via_config->name, t,
	360	via_dma[via_config->flags & VIA_UDMA],
361	pci_name(dev));
362
1da177e4 LT	363	return 0;
	364	}
	365
7462cbff DD	366	/*
	367	* Check and handle 80-wire cable presence
	368	*/
	369	static void __devinit via_cable_detect(struct pci_dev dev, struct via82cxxx_dev vdev)
	370	{
	371	unsigned int u;
	372	int i;
	373	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	374
	375	switch (vdev->via_config->flags & VIA_UDMA) {
	376
	377	case VIA_UDMA_66:
	378	for (i = 24; i >= 0; i -= 8)
	379	if (((u >> (i & 16)) & 8) &&
	380	((u >> i) & 0x20) &&
	381	(((u >> i) & 7) < 2)) {
	382	/*
	383	* 2x PCI clock and
	384	* UDMA w/ < 3T/cycle
	385	*/
	386	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	387	}
	388	break;
	389
	390	case VIA_UDMA_100:
	391	for (i = 24; i >= 0; i -= 8)
	392	if (((u >> i) & 0x10) \|\|
	393	(((u >> i) & 0x20) &&
	394	(((u >> i) & 7) < 4))) {
	395	/* BIOS 80-wire bit or
	396	* UDMA w/ < 60ns/cycle
	397	*/
	398	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	399	}
	400	break;
	401
	402	case VIA_UDMA_133:
	403	for (i = 24; i >= 0; i -= 8)
	404	if (((u >> i) & 0x10) \|\|
	405	(((u >> i) & 0x20) &&
	406	(((u >> i) & 7) < 6))) {
	407	/* BIOS 80-wire bit or
	408	* UDMA w/ < 60ns/cycle
	409	*/
	410	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	411	}
	412	break;
	413
	414	}
	415	}
	416
f3718d3e	417	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	418	{
7462cbff DD	419	struct via82cxxx_dev *vdev = kmalloc(sizeof(struct via82cxxx_dev),
	420	GFP_KERNEL);
	421	struct pci_dev *isa = NULL;
1da177e4 LT	422	int i;
1da177e4 LT	423
7462cbff DD	424	if (vdev == NULL) {
	425	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	426	return;
	427	}
	428
	429	memset(vdev, 0, sizeof(struct via82cxxx_dev));
	430	ide_set_hwifdata(hwif, vdev);
	431
	432	vdev->via_config = via_config_find(&isa);
	433	via_cable_detect(hwif->pci_dev, vdev);
	434
1da177e4 LT	435	hwif->autodma = 0;
	436
	437	hwif->tuneproc = &via82cxxx_tune_drive;
	438	hwif->speedproc = &via_set_drive;
	439
	440
3b212db9	441	#if defined(CONFIG_PPC_CHRP) && defined(CONFIG_PPC32)
e8222502	442	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
1da177e4 LT	443	hwif->irq = hwif->channel ? 15 : 14;
	444	}
	445	#endif
	446
	447	for (i = 0; i < 2; i++) {
	448	hwif->drives[i].io_32bit = 1;
7462cbff	449	hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
1da177e4 LT	450	hwif->drives[i].autotune = 1;
	451	hwif->drives[i].dn = hwif->channel * 2 + i;
	452	}
	453
	454	if (!hwif->dma_base)
	455	return;
	456
	457	hwif->atapi_dma = 1;
	458	hwif->ultra_mask = 0x7f;
	459	hwif->mwdma_mask = 0x07;
	460	hwif->swdma_mask = 0x07;
	461
	462	if (!hwif->udma_four)
7462cbff	463	hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
1da177e4 LT	464	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	465	if (!noautodma)
	466	hwif->autodma = 1;
	467	hwif->drives[0].autodma = hwif->autodma;
	468	hwif->drives[1].autodma = hwif->autodma;
	469	}
	470
4f1d774a MK	471	static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	472	{ /* 0 */
	473	.name = "VP_IDE",
	474	.init_chipset = init_chipset_via82cxxx,
	475	.init_hwif = init_hwif_via82cxxx,
	476	.channels = 2,
	477	.autodma = NOAUTODMA,
	478	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
	479	.bootable = ON_BOARD
	480	},{ /* 1 */
	481	.name = "VP_IDE",
	482	.init_chipset = init_chipset_via82cxxx,
	483	.init_hwif = init_hwif_via82cxxx,
	484	.channels = 2,
	485	.autodma = AUTODMA,
	486	.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
	487	.bootable = ON_BOARD,
	488	}
1da177e4 LT	489	};
	490
	491	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	492	{
4f1d774a	493	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
1da177e4 LT	494	}
	495
	496	static struct pci_device_id via_pci_tbl[] = {
	497	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	498	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
4f1d774a	499	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1da177e4 LT	500	{ 0, },
	501	};
	502	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	503
	504	static struct pci_driver driver = {
	505	.name = "VIA_IDE",
	506	.id_table = via_pci_tbl,
	507	.probe = via_init_one,
	508	};
	509
	510	static int via_ide_init(void)
	511	{
	512	return ide_pci_register_driver(&driver);
	513	}
	514
	515	module_init(via_ide_init);
	516
	517	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	518	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	519	MODULE_LICENSE("GPL");