Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Promise TX2/TX4/TX2000/133 IDE driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Split from: | |
10 | * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002 | |
11 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> | |
35198234 | 12 | * Copyright (C) 2005-2007 MontaVista Software, Inc. |
1da177e4 LT |
13 | * Portions Copyright (C) 1999 Promise Technology, Inc. |
14 | * Author: Frank Tiernan (frankt@promise.com) | |
15 | * Released under terms of General Public License | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/delay.h> | |
1da177e4 LT |
22 | #include <linux/pci.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/ide.h> | |
353b39d1 | 25 | #include <linux/ktime.h> |
1da177e4 LT |
26 | |
27 | #include <asm/io.h> | |
1da177e4 LT |
28 | |
29 | #ifdef CONFIG_PPC_PMAC | |
30 | #include <asm/prom.h> | |
1da177e4 LT |
31 | #endif |
32 | ||
ced3ec8a BZ |
33 | #define DRV_NAME "pdc202xx_new" |
34 | ||
47694bb8 SS |
35 | #undef DEBUG |
36 | ||
37 | #ifdef DEBUG | |
eb63963a | 38 | #define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args) |
47694bb8 SS |
39 | #else |
40 | #define DBG(fmt, args...) | |
41 | #endif | |
42 | ||
47694bb8 | 43 | static u8 max_dma_rate(struct pci_dev *pdev) |
1da177e4 LT |
44 | { |
45 | u8 mode; | |
46 | ||
47694bb8 | 47 | switch(pdev->device) { |
1da177e4 LT |
48 | case PCI_DEVICE_ID_PROMISE_20277: |
49 | case PCI_DEVICE_ID_PROMISE_20276: | |
50 | case PCI_DEVICE_ID_PROMISE_20275: | |
51 | case PCI_DEVICE_ID_PROMISE_20271: | |
52 | case PCI_DEVICE_ID_PROMISE_20269: | |
53 | mode = 4; | |
54 | break; | |
55 | case PCI_DEVICE_ID_PROMISE_20270: | |
56 | case PCI_DEVICE_ID_PROMISE_20268: | |
57 | mode = 3; | |
58 | break; | |
59 | default: | |
60 | return 0; | |
61 | } | |
47694bb8 | 62 | |
1da177e4 LT |
63 | return mode; |
64 | } | |
65 | ||
47694bb8 SS |
66 | /** |
67 | * get_indexed_reg - Get indexed register | |
68 | * @hwif: for the port address | |
69 | * @index: index of the indexed register | |
70 | */ | |
71 | static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index) | |
72 | { | |
73 | u8 value; | |
74 | ||
41051a14 BZ |
75 | outb(index, hwif->dma_base + 1); |
76 | value = inb(hwif->dma_base + 3); | |
47694bb8 SS |
77 | |
78 | DBG("index[%02X] value[%02X]\n", index, value); | |
79 | return value; | |
80 | } | |
81 | ||
82 | /** | |
83 | * set_indexed_reg - Set indexed register | |
84 | * @hwif: for the port address | |
85 | * @index: index of the indexed register | |
86 | */ | |
87 | static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) | |
88 | { | |
41051a14 BZ |
89 | outb(index, hwif->dma_base + 1); |
90 | outb(value, hwif->dma_base + 3); | |
47694bb8 SS |
91 | DBG("index[%02X] value[%02X]\n", index, value); |
92 | } | |
93 | ||
94 | /* | |
95 | * ATA Timing Tables based on 133 MHz PLL output clock. | |
96 | * | |
97 | * If the PLL outputs 100 MHz clock, the ASIC hardware will set | |
98 | * the timing registers automatically when "set features" command is | |
99 | * issued to the device. However, if the PLL output clock is 133 MHz, | |
100 | * the following tables must be used. | |
101 | */ | |
102 | static struct pio_timing { | |
103 | u8 reg0c, reg0d, reg13; | |
104 | } pio_timings [] = { | |
105 | { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */ | |
106 | { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */ | |
107 | { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */ | |
108 | { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ | |
109 | { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ | |
110 | }; | |
111 | ||
112 | static struct mwdma_timing { | |
113 | u8 reg0e, reg0f; | |
114 | } mwdma_timings [] = { | |
115 | { 0xdf, 0x5f }, /* MWDMA mode 0 */ | |
116 | { 0x6b, 0x27 }, /* MWDMA mode 1 */ | |
117 | { 0x69, 0x25 }, /* MWDMA mode 2 */ | |
118 | }; | |
119 | ||
120 | static struct udma_timing { | |
121 | u8 reg10, reg11, reg12; | |
122 | } udma_timings [] = { | |
123 | { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ | |
124 | { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ | |
125 | { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ | |
126 | { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ | |
127 | { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ | |
128 | { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ | |
129 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ | |
130 | }; | |
131 | ||
8776168c | 132 | static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 133 | { |
36501650 | 134 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
47694bb8 | 135 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; |
8776168c | 136 | const u8 speed = drive->dma_mode; |
1da177e4 | 137 | |
47694bb8 | 138 | /* |
88b2b32b BZ |
139 | * IDE core issues SETFEATURES_XFER to the drive first (thanks to |
140 | * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will | |
47694bb8 | 141 | * automatically set the timing registers based on 100 MHz PLL output. |
88b2b32b | 142 | * |
47694bb8 SS |
143 | * As we set up the PLL to output 133 MHz for UltraDMA/133 capable |
144 | * chips, we must override the default register settings... | |
145 | */ | |
36501650 | 146 | if (max_dma_rate(dev) == 4) { |
47694bb8 SS |
147 | u8 mode = speed & 0x07; |
148 | ||
4db90a14 BZ |
149 | if (speed >= XFER_UDMA_0) { |
150 | set_indexed_reg(hwif, 0x10 + adj, | |
151 | udma_timings[mode].reg10); | |
152 | set_indexed_reg(hwif, 0x11 + adj, | |
153 | udma_timings[mode].reg11); | |
154 | set_indexed_reg(hwif, 0x12 + adj, | |
155 | udma_timings[mode].reg12); | |
156 | } else { | |
157 | set_indexed_reg(hwif, 0x0e + adj, | |
158 | mwdma_timings[mode].reg0e); | |
159 | set_indexed_reg(hwif, 0x0f + adj, | |
160 | mwdma_timings[mode].reg0f); | |
47694bb8 SS |
161 | } |
162 | } else if (speed == XFER_UDMA_2) { | |
163 | /* Set tHOLD bit to 0 if using UDMA mode 2 */ | |
164 | u8 tmp = get_indexed_reg(hwif, 0x10 + adj); | |
165 | ||
166 | set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f); | |
167 | } | |
1da177e4 LT |
168 | } |
169 | ||
e085b3ca | 170 | static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 171 | { |
36501650 | 172 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ad4ba7dc | 173 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; |
e085b3ca | 174 | const u8 pio = drive->pio_mode - XFER_PIO_0; |
ad4ba7dc | 175 | |
36501650 | 176 | if (max_dma_rate(dev) == 4) { |
ad4ba7dc BZ |
177 | set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c); |
178 | set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d); | |
179 | set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13); | |
180 | } | |
1da177e4 LT |
181 | } |
182 | ||
f454cbe8 | 183 | static u8 pdcnew_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 184 | { |
49521f97 BZ |
185 | if (get_indexed_reg(hwif, 0x0b) & 0x04) |
186 | return ATA_CBL_PATA40; | |
187 | else | |
188 | return ATA_CBL_PATA80; | |
1da177e4 | 189 | } |
47694bb8 | 190 | |
47694bb8 | 191 | static void pdcnew_reset(ide_drive_t *drive) |
1da177e4 LT |
192 | { |
193 | /* | |
194 | * Deleted this because it is redundant from the caller. | |
195 | */ | |
47694bb8 | 196 | printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n", |
898ec223 | 197 | drive->hwif->channel ? "Secondary" : "Primary"); |
1da177e4 LT |
198 | } |
199 | ||
47694bb8 SS |
200 | /** |
201 | * read_counter - Read the byte count registers | |
202 | * @dma_base: for the port address | |
203 | */ | |
feb22b7f | 204 | static long read_counter(u32 dma_base) |
47694bb8 SS |
205 | { |
206 | u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08; | |
207 | u8 cnt0, cnt1, cnt2, cnt3; | |
208 | long count = 0, last; | |
209 | int retry = 3; | |
210 | ||
211 | do { | |
212 | last = count; | |
213 | ||
214 | /* Read the current count */ | |
215 | outb(0x20, pri_dma_base + 0x01); | |
216 | cnt0 = inb(pri_dma_base + 0x03); | |
217 | outb(0x21, pri_dma_base + 0x01); | |
218 | cnt1 = inb(pri_dma_base + 0x03); | |
219 | outb(0x20, sec_dma_base + 0x01); | |
220 | cnt2 = inb(sec_dma_base + 0x03); | |
221 | outb(0x21, sec_dma_base + 0x01); | |
222 | cnt3 = inb(sec_dma_base + 0x03); | |
223 | ||
224 | count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0; | |
225 | ||
226 | /* | |
227 | * The 30-bit decrementing counter is read in 4 pieces. | |
228 | * Incorrect value may be read when the most significant bytes | |
229 | * are changing... | |
230 | */ | |
231 | } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count)); | |
232 | ||
233 | DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n", | |
234 | cnt0, cnt1, cnt2, cnt3); | |
235 | ||
236 | return count; | |
237 | } | |
238 | ||
239 | /** | |
240 | * detect_pll_input_clock - Detect the PLL input clock in Hz. | |
241 | * @dma_base: for the port address | |
242 | * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock. | |
243 | */ | |
feb22b7f | 244 | static long detect_pll_input_clock(unsigned long dma_base) |
47694bb8 | 245 | { |
353b39d1 | 246 | ktime_t start_time, end_time; |
47694bb8 | 247 | long start_count, end_count; |
8006bf56 | 248 | long pll_input, usec_elapsed; |
47694bb8 SS |
249 | u8 scr1; |
250 | ||
251 | start_count = read_counter(dma_base); | |
353b39d1 | 252 | start_time = ktime_get(); |
47694bb8 SS |
253 | |
254 | /* Start the test mode */ | |
255 | outb(0x01, dma_base + 0x01); | |
256 | scr1 = inb(dma_base + 0x03); | |
257 | DBG("scr1[%02X]\n", scr1); | |
258 | outb(scr1 | 0x40, dma_base + 0x03); | |
259 | ||
260 | /* Let the counter run for 10 ms. */ | |
261 | mdelay(10); | |
262 | ||
263 | end_count = read_counter(dma_base); | |
353b39d1 | 264 | end_time = ktime_get(); |
47694bb8 SS |
265 | |
266 | /* Stop the test mode */ | |
267 | outb(0x01, dma_base + 0x01); | |
268 | scr1 = inb(dma_base + 0x03); | |
269 | DBG("scr1[%02X]\n", scr1); | |
270 | outb(scr1 & ~0x40, dma_base + 0x03); | |
271 | ||
272 | /* | |
273 | * Calculate the input clock in Hz | |
274 | * (the clock counter is 30 bit wide and counts down) | |
275 | */ | |
353b39d1 | 276 | usec_elapsed = ktime_us_delta(end_time, start_time); |
56fe23d5 | 277 | pll_input = ((start_count - end_count) & 0x3fffffff) / 10 * |
8006bf56 | 278 | (10000000 / usec_elapsed); |
47694bb8 SS |
279 | |
280 | DBG("start[%ld] end[%ld]\n", start_count, end_count); | |
281 | ||
282 | return pll_input; | |
283 | } | |
284 | ||
1da177e4 | 285 | #ifdef CONFIG_PPC_PMAC |
feb22b7f | 286 | static void apple_kiwi_init(struct pci_dev *pdev) |
1da177e4 LT |
287 | { |
288 | struct device_node *np = pci_device_to_OF_node(pdev); | |
1da177e4 LT |
289 | u8 conf; |
290 | ||
55b61fec | 291 | if (np == NULL || !of_device_is_compatible(np, "kiwi-root")) |
1da177e4 LT |
292 | return; |
293 | ||
fc212bb1 | 294 | if (pdev->revision >= 0x03) { |
1da177e4 | 295 | /* Setup chip magic config stuff (from darwin) */ |
47694bb8 SS |
296 | pci_read_config_byte (pdev, 0x40, &conf); |
297 | pci_write_config_byte(pdev, 0x40, (conf | 0x01)); | |
1da177e4 | 298 | } |
1da177e4 LT |
299 | } |
300 | #endif /* CONFIG_PPC_PMAC */ | |
301 | ||
2ed0ef54 | 302 | static int init_chipset_pdcnew(struct pci_dev *dev) |
1da177e4 | 303 | { |
a326b02b | 304 | const char *name = DRV_NAME; |
47694bb8 SS |
305 | unsigned long dma_base = pci_resource_start(dev, 4); |
306 | unsigned long sec_dma_base = dma_base + 0x08; | |
307 | long pll_input, pll_output, ratio; | |
308 | int f, r; | |
309 | u8 pll_ctl0, pll_ctl1; | |
310 | ||
01cc643a BZ |
311 | if (dma_base == 0) |
312 | return -EFAULT; | |
313 | ||
1da177e4 LT |
314 | #ifdef CONFIG_PPC_PMAC |
315 | apple_kiwi_init(dev); | |
316 | #endif | |
317 | ||
47694bb8 SS |
318 | /* Calculate the required PLL output frequency */ |
319 | switch(max_dma_rate(dev)) { | |
320 | case 4: /* it's 133 MHz for Ultra133 chips */ | |
321 | pll_output = 133333333; | |
322 | break; | |
323 | case 3: /* and 100 MHz for Ultra100 chips */ | |
324 | default: | |
325 | pll_output = 100000000; | |
326 | break; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Detect PLL input clock. | |
331 | * On some systems, where PCI bus is running at non-standard clock rate | |
332 | * (e.g. 25 or 40 MHz), we have to adjust the cycle time. | |
333 | * PDC20268 and newer chips employ PLL circuit to help correct timing | |
334 | * registers setting. | |
335 | */ | |
336 | pll_input = detect_pll_input_clock(dma_base); | |
28cfd8af BZ |
337 | printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n", |
338 | name, pci_name(dev), pll_input / 1000); | |
47694bb8 SS |
339 | |
340 | /* Sanity check */ | |
341 | if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) { | |
28cfd8af BZ |
342 | printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!" |
343 | "\n", name, pci_name(dev), pll_input); | |
47694bb8 SS |
344 | goto out; |
345 | } | |
346 | ||
347 | #ifdef DEBUG | |
348 | DBG("pll_output is %ld Hz\n", pll_output); | |
349 | ||
350 | /* Show the current clock value of PLL control register | |
351 | * (maybe already configured by the BIOS) | |
352 | */ | |
353 | outb(0x02, sec_dma_base + 0x01); | |
354 | pll_ctl0 = inb(sec_dma_base + 0x03); | |
355 | outb(0x03, sec_dma_base + 0x01); | |
356 | pll_ctl1 = inb(sec_dma_base + 0x03); | |
357 | ||
358 | DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
359 | #endif | |
360 | ||
361 | /* | |
362 | * Calculate the ratio of F, R and NO | |
363 | * POUT = (F + 2) / (( R + 2) * NO) | |
364 | */ | |
365 | ratio = pll_output / (pll_input / 1000); | |
366 | if (ratio < 8600L) { /* 8.6x */ | |
367 | /* Using NO = 0x01, R = 0x0d */ | |
368 | r = 0x0d; | |
369 | } else if (ratio < 12900L) { /* 12.9x */ | |
370 | /* Using NO = 0x01, R = 0x08 */ | |
371 | r = 0x08; | |
372 | } else if (ratio < 16100L) { /* 16.1x */ | |
373 | /* Using NO = 0x01, R = 0x06 */ | |
374 | r = 0x06; | |
375 | } else if (ratio < 64000L) { /* 64x */ | |
376 | r = 0x00; | |
377 | } else { | |
378 | /* Invalid ratio */ | |
28cfd8af BZ |
379 | printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n", |
380 | name, pci_name(dev), ratio); | |
47694bb8 SS |
381 | goto out; |
382 | } | |
383 | ||
384 | f = (ratio * (r + 2)) / 1000 - 2; | |
385 | ||
386 | DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio); | |
387 | ||
388 | if (unlikely(f < 0 || f > 127)) { | |
389 | /* Invalid F */ | |
28cfd8af BZ |
390 | printk(KERN_ERR "%s %s: F[%d] invalid!\n", |
391 | name, pci_name(dev), f); | |
47694bb8 SS |
392 | goto out; |
393 | } | |
394 | ||
395 | pll_ctl0 = (u8) f; | |
396 | pll_ctl1 = (u8) r; | |
397 | ||
398 | DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
399 | ||
400 | outb(0x02, sec_dma_base + 0x01); | |
401 | outb(pll_ctl0, sec_dma_base + 0x03); | |
402 | outb(0x03, sec_dma_base + 0x01); | |
403 | outb(pll_ctl1, sec_dma_base + 0x03); | |
404 | ||
405 | /* Wait the PLL circuit to be stable */ | |
406 | mdelay(30); | |
407 | ||
408 | #ifdef DEBUG | |
409 | /* | |
410 | * Show the current clock value of PLL control register | |
411 | */ | |
412 | outb(0x02, sec_dma_base + 0x01); | |
413 | pll_ctl0 = inb(sec_dma_base + 0x03); | |
414 | outb(0x03, sec_dma_base + 0x01); | |
415 | pll_ctl1 = inb(sec_dma_base + 0x03); | |
416 | ||
417 | DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
418 | #endif | |
419 | ||
420 | out: | |
2ed0ef54 | 421 | return 0; |
1da177e4 LT |
422 | } |
423 | ||
fe31edc8 | 424 | static struct pci_dev *pdc20270_get_dev2(struct pci_dev *dev) |
1da177e4 | 425 | { |
099b1f42 BZ |
426 | struct pci_dev *dev2; |
427 | ||
eadb6ecf | 428 | dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1, |
099b1f42 | 429 | PCI_FUNC(dev->devfn))); |
eadb6ecf | 430 | |
099b1f42 BZ |
431 | if (dev2 && |
432 | dev2->vendor == dev->vendor && | |
433 | dev2->device == dev->device) { | |
434 | ||
435 | if (dev2->irq != dev->irq) { | |
436 | dev2->irq = dev->irq; | |
ced3ec8a | 437 | printk(KERN_INFO DRV_NAME " %s: PCI config space " |
28cfd8af | 438 | "interrupt fixed\n", pci_name(dev)); |
1da177e4 | 439 | } |
07047935 | 440 | |
099b1f42 | 441 | return dev2; |
1da177e4 | 442 | } |
099b1f42 BZ |
443 | |
444 | return NULL; | |
1da177e4 LT |
445 | } |
446 | ||
ac95beed BZ |
447 | static const struct ide_port_ops pdcnew_port_ops = { |
448 | .set_pio_mode = pdcnew_set_pio_mode, | |
449 | .set_dma_mode = pdcnew_set_dma_mode, | |
ac95beed BZ |
450 | .resetproc = pdcnew_reset, |
451 | .cable_detect = pdcnew_cable_detect, | |
452 | }; | |
453 | ||
ced3ec8a | 454 | #define DECLARE_PDCNEW_DEV(udma) \ |
05d7e6cb | 455 | { \ |
ced3ec8a | 456 | .name = DRV_NAME, \ |
05d7e6cb | 457 | .init_chipset = init_chipset_pdcnew, \ |
ac95beed | 458 | .port_ops = &pdcnew_port_ops, \ |
05d7e6cb | 459 | .host_flags = IDE_HFLAG_POST_SET_MODE | \ |
ed67b923 | 460 | IDE_HFLAG_ERROR_STOPS_FIFO | \ |
05d7e6cb BZ |
461 | IDE_HFLAG_OFF_BOARD, \ |
462 | .pio_mask = ATA_PIO4, \ | |
463 | .mwdma_mask = ATA_MWDMA2, \ | |
464 | .udma_mask = udma, \ | |
1da177e4 | 465 | } |
05d7e6cb | 466 | |
fe31edc8 | 467 | static const struct ide_port_info pdcnew_chipsets[] = { |
ced3ec8a BZ |
468 | /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5), |
469 | /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6), | |
1da177e4 LT |
470 | }; |
471 | ||
472 | /** | |
473 | * pdc202new_init_one - called when a pdc202xx is found | |
474 | * @dev: the pdc202new device | |
475 | * @id: the matching pci id | |
476 | * | |
477 | * Called when the PCI registration layer (or the IDE initialization) | |
478 | * finds a device matching our IDE device tables. | |
479 | */ | |
480 | ||
fe31edc8 | 481 | static int pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 482 | { |
ced3ec8a | 483 | const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data]; |
099b1f42 | 484 | struct pci_dev *bridge = dev->bus->self; |
099b1f42 | 485 | |
ced3ec8a | 486 | if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge && |
099b1f42 BZ |
487 | bridge->vendor == PCI_VENDOR_ID_DEC && |
488 | bridge->device == PCI_DEVICE_ID_DEC_21150) { | |
489 | struct pci_dev *dev2; | |
490 | ||
491 | if (PCI_SLOT(dev->devfn) & 2) | |
492 | return -ENODEV; | |
1da177e4 | 493 | |
099b1f42 BZ |
494 | dev2 = pdc20270_get_dev2(dev); |
495 | ||
496 | if (dev2) { | |
6cdf6eb3 | 497 | int ret = ide_pci_init_two(dev, dev2, d, NULL); |
099b1f42 BZ |
498 | if (ret < 0) |
499 | pci_dev_put(dev2); | |
500 | return ret; | |
501 | } | |
502 | } | |
503 | ||
ced3ec8a | 504 | if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge && |
099b1f42 BZ |
505 | bridge->vendor == PCI_VENDOR_ID_INTEL && |
506 | (bridge->device == PCI_DEVICE_ID_INTEL_I960 || | |
507 | bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { | |
ced3ec8a | 508 | printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller," |
28cfd8af | 509 | " skipping\n", pci_name(dev)); |
099b1f42 BZ |
510 | return -ENODEV; |
511 | } | |
512 | ||
6cdf6eb3 | 513 | return ide_pci_init_one(dev, d, NULL); |
1da177e4 LT |
514 | } |
515 | ||
fe31edc8 | 516 | static void pdc202new_remove(struct pci_dev *dev) |
d69c8f8c BZ |
517 | { |
518 | struct ide_host *host = pci_get_drvdata(dev); | |
519 | struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; | |
520 | ||
521 | ide_pci_remove(dev); | |
522 | pci_dev_put(dev2); | |
523 | } | |
524 | ||
9cbcc5e3 BZ |
525 | static const struct pci_device_id pdc202new_pci_tbl[] = { |
526 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 }, | |
527 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 }, | |
ced3ec8a BZ |
528 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 }, |
529 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 }, | |
530 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 }, | |
531 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 }, | |
532 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 }, | |
1da177e4 LT |
533 | { 0, }, |
534 | }; | |
535 | MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl); | |
536 | ||
a9ab09e2 | 537 | static struct pci_driver pdc202new_pci_driver = { |
1da177e4 LT |
538 | .name = "Promise_IDE", |
539 | .id_table = pdc202new_pci_tbl, | |
540 | .probe = pdc202new_init_one, | |
fe31edc8 | 541 | .remove = pdc202new_remove, |
feb22b7f BZ |
542 | .suspend = ide_pci_suspend, |
543 | .resume = ide_pci_resume, | |
1da177e4 LT |
544 | }; |
545 | ||
82ab1eec | 546 | static int __init pdc202new_ide_init(void) |
1da177e4 | 547 | { |
a9ab09e2 | 548 | return ide_pci_register_driver(&pdc202new_pci_driver); |
1da177e4 LT |
549 | } |
550 | ||
d69c8f8c BZ |
551 | static void __exit pdc202new_ide_exit(void) |
552 | { | |
a9ab09e2 | 553 | pci_unregister_driver(&pdc202new_pci_driver); |
d69c8f8c BZ |
554 | } |
555 | ||
1da177e4 | 556 | module_init(pdc202new_ide_init); |
d69c8f8c | 557 | module_exit(pdc202new_ide_exit); |
1da177e4 LT |
558 | |
559 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); | |
560 | MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher"); | |
561 | MODULE_LICENSE("GPL"); |