Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Support for IDE interfaces on PowerMacs. |
58f189fc | 3 | * |
1da177e4 LT |
4 | * These IDE interfaces are memory-mapped and have a DBDMA channel |
5 | * for doing DMA. | |
6 | * | |
7 | * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt | |
8a97206e | 8 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * Some code taken from drivers/ide/ide-dma.c: | |
16 | * | |
17 | * Copyright (c) 1995-1998 Mark Lord | |
18 | * | |
19 | * TODO: - Use pre-calculated (kauai) timing tables all the time and | |
20 | * get rid of the "rounded" tables used previously, so we have the | |
21 | * same table format for all controllers and can then just have one | |
22 | * big table | |
23 | * | |
24 | */ | |
1da177e4 LT |
25 | #include <linux/types.h> |
26 | #include <linux/kernel.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/ide.h> | |
30 | #include <linux/notifier.h> | |
31 | #include <linux/reboot.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/adb.h> | |
34 | #include <linux/pmu.h> | |
35 | #include <linux/scatterlist.h> | |
36 | ||
37 | #include <asm/prom.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/dbdma.h> | |
40 | #include <asm/ide.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/machdep.h> | |
43 | #include <asm/pmac_feature.h> | |
44 | #include <asm/sections.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #ifndef CONFIG_PPC64 | |
48 | #include <asm/mediabay.h> | |
49 | #endif | |
50 | ||
1da177e4 LT |
51 | #undef IDE_PMAC_DEBUG |
52 | ||
53 | #define DMA_WAIT_TIMEOUT 50 | |
54 | ||
55 | typedef struct pmac_ide_hwif { | |
56 | unsigned long regbase; | |
57 | int irq; | |
58 | int kind; | |
59 | int aapl_bus_id; | |
1da177e4 LT |
60 | unsigned mediabay : 1; |
61 | unsigned broken_dma : 1; | |
62 | unsigned broken_dma_warn : 1; | |
63 | struct device_node* node; | |
64 | struct macio_dev *mdev; | |
65 | u32 timings[4]; | |
66 | volatile u32 __iomem * *kauai_fcr; | |
67 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
68 | /* Those fields are duplicating what is in hwif. We currently | |
69 | * can't use the hwif ones because of some assumptions that are | |
70 | * beeing done by the generic code about the kind of dma controller | |
71 | * and format of the dma table. This will have to be fixed though. | |
72 | */ | |
73 | volatile struct dbdma_regs __iomem * dma_regs; | |
74 | struct dbdma_cmd* dma_table_cpu; | |
75 | #endif | |
76 | ||
77 | } pmac_ide_hwif_t; | |
78 | ||
1da177e4 LT |
79 | enum { |
80 | controller_ohare, /* OHare based */ | |
81 | controller_heathrow, /* Heathrow/Paddington */ | |
82 | controller_kl_ata3, /* KeyLargo ATA-3 */ | |
83 | controller_kl_ata4, /* KeyLargo ATA-4 */ | |
84 | controller_un_ata6, /* UniNorth2 ATA-6 */ | |
85 | controller_k2_ata6, /* K2 ATA-6 */ | |
86 | controller_sh_ata6, /* Shasta ATA-6 */ | |
87 | }; | |
88 | ||
89 | static const char* model_name[] = { | |
90 | "OHare ATA", /* OHare based */ | |
91 | "Heathrow ATA", /* Heathrow/Paddington */ | |
92 | "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ | |
93 | "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ | |
94 | "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ | |
95 | "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ | |
96 | "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ | |
97 | }; | |
98 | ||
99 | /* | |
100 | * Extra registers, both 32-bit little-endian | |
101 | */ | |
102 | #define IDE_TIMING_CONFIG 0x200 | |
103 | #define IDE_INTERRUPT 0x300 | |
104 | ||
105 | /* Kauai (U2) ATA has different register setup */ | |
106 | #define IDE_KAUAI_PIO_CONFIG 0x200 | |
107 | #define IDE_KAUAI_ULTRA_CONFIG 0x210 | |
108 | #define IDE_KAUAI_POLL_CONFIG 0x220 | |
109 | ||
110 | /* | |
111 | * Timing configuration register definitions | |
112 | */ | |
113 | ||
114 | /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ | |
115 | #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) | |
116 | #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) | |
117 | #define IDE_SYSCLK_NS 30 /* 33Mhz cell */ | |
118 | #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ | |
119 | ||
120 | /* 133Mhz cell, found in shasta. | |
121 | * See comments about 100 Mhz Uninorth 2... | |
122 | * Note that PIO_MASK and MDMA_MASK seem to overlap | |
123 | */ | |
124 | #define TR_133_PIOREG_PIO_MASK 0xff000fff | |
125 | #define TR_133_PIOREG_MDMA_MASK 0x00fff800 | |
126 | #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff | |
127 | #define TR_133_UDMAREG_UDMA_EN 0x00000001 | |
128 | ||
129 | /* 100Mhz cell, found in Uninorth 2. I don't have much infos about | |
130 | * this one yet, it appears as a pci device (106b/0033) on uninorth | |
131 | * internal PCI bus and it's clock is controlled like gem or fw. It | |
132 | * appears to be an evolution of keylargo ATA4 with a timing register | |
133 | * extended to 2 32bits registers and a similar DBDMA channel. Other | |
134 | * registers seem to exist but I can't tell much about them. | |
135 | * | |
136 | * So far, I'm using pre-calculated tables for this extracted from | |
137 | * the values used by the MacOS X driver. | |
138 | * | |
139 | * The "PIO" register controls PIO and MDMA timings, the "ULTRA" | |
140 | * register controls the UDMA timings. At least, it seems bit 0 | |
141 | * of this one enables UDMA vs. MDMA, and bits 4..7 are the | |
142 | * cycle time in units of 10ns. Bits 8..15 are used by I don't | |
143 | * know their meaning yet | |
144 | */ | |
145 | #define TR_100_PIOREG_PIO_MASK 0xff000fff | |
146 | #define TR_100_PIOREG_MDMA_MASK 0x00fff000 | |
147 | #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff | |
148 | #define TR_100_UDMAREG_UDMA_EN 0x00000001 | |
149 | ||
150 | ||
151 | /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on | |
152 | * 40 connector cable and to 4 on 80 connector one. | |
153 | * Clock unit is 15ns (66Mhz) | |
154 | * | |
155 | * 3 Values can be programmed: | |
156 | * - Write data setup, which appears to match the cycle time. They | |
157 | * also call it DIOW setup. | |
158 | * - Ready to pause time (from spec) | |
159 | * - Address setup. That one is weird. I don't see where exactly | |
160 | * it fits in UDMA cycles, I got it's name from an obscure piece | |
161 | * of commented out code in Darwin. They leave it to 0, we do as | |
162 | * well, despite a comment that would lead to think it has a | |
163 | * min value of 45ns. | |
164 | * Apple also add 60ns to the write data setup (or cycle time ?) on | |
165 | * reads. | |
166 | */ | |
167 | #define TR_66_UDMA_MASK 0xfff00000 | |
168 | #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ | |
169 | #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */ | |
170 | #define TR_66_UDMA_ADDRSETUP_SHIFT 29 | |
171 | #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ | |
172 | #define TR_66_UDMA_RDY2PAUS_SHIFT 25 | |
173 | #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ | |
174 | #define TR_66_UDMA_WRDATASETUP_SHIFT 21 | |
175 | #define TR_66_MDMA_MASK 0x000ffc00 | |
176 | #define TR_66_MDMA_RECOVERY_MASK 0x000f8000 | |
177 | #define TR_66_MDMA_RECOVERY_SHIFT 15 | |
178 | #define TR_66_MDMA_ACCESS_MASK 0x00007c00 | |
179 | #define TR_66_MDMA_ACCESS_SHIFT 10 | |
180 | #define TR_66_PIO_MASK 0x000003ff | |
181 | #define TR_66_PIO_RECOVERY_MASK 0x000003e0 | |
182 | #define TR_66_PIO_RECOVERY_SHIFT 5 | |
183 | #define TR_66_PIO_ACCESS_MASK 0x0000001f | |
184 | #define TR_66_PIO_ACCESS_SHIFT 0 | |
185 | ||
186 | /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo | |
187 | * Can do pio & mdma modes, clock unit is 30ns (33Mhz) | |
188 | * | |
189 | * The access time and recovery time can be programmed. Some older | |
190 | * Darwin code base limit OHare to 150ns cycle time. I decided to do | |
191 | * the same here fore safety against broken old hardware ;) | |
192 | * The HalfTick bit, when set, adds half a clock (15ns) to the access | |
193 | * time and removes one from recovery. It's not supported on KeyLargo | |
194 | * implementation afaik. The E bit appears to be set for PIO mode 0 and | |
195 | * is used to reach long timings used in this mode. | |
196 | */ | |
197 | #define TR_33_MDMA_MASK 0x003ff800 | |
198 | #define TR_33_MDMA_RECOVERY_MASK 0x001f0000 | |
199 | #define TR_33_MDMA_RECOVERY_SHIFT 16 | |
200 | #define TR_33_MDMA_ACCESS_MASK 0x0000f800 | |
201 | #define TR_33_MDMA_ACCESS_SHIFT 11 | |
202 | #define TR_33_MDMA_HALFTICK 0x00200000 | |
203 | #define TR_33_PIO_MASK 0x000007ff | |
204 | #define TR_33_PIO_E 0x00000400 | |
205 | #define TR_33_PIO_RECOVERY_MASK 0x000003e0 | |
206 | #define TR_33_PIO_RECOVERY_SHIFT 5 | |
207 | #define TR_33_PIO_ACCESS_MASK 0x0000001f | |
208 | #define TR_33_PIO_ACCESS_SHIFT 0 | |
209 | ||
210 | /* | |
211 | * Interrupt register definitions | |
212 | */ | |
213 | #define IDE_INTR_DMA 0x80000000 | |
214 | #define IDE_INTR_DEVICE 0x40000000 | |
215 | ||
216 | /* | |
217 | * FCR Register on Kauai. Not sure what bit 0x4 is ... | |
218 | */ | |
219 | #define KAUAI_FCR_UATA_MAGIC 0x00000004 | |
220 | #define KAUAI_FCR_UATA_RESET_N 0x00000002 | |
221 | #define KAUAI_FCR_UATA_ENABLE 0x00000001 | |
222 | ||
223 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
224 | ||
225 | /* Rounded Multiword DMA timings | |
226 | * | |
227 | * I gave up finding a generic formula for all controller | |
228 | * types and instead, built tables based on timing values | |
229 | * used by Apple in Darwin's implementation. | |
230 | */ | |
231 | struct mdma_timings_t { | |
232 | int accessTime; | |
233 | int recoveryTime; | |
234 | int cycleTime; | |
235 | }; | |
236 | ||
aacaf9bd | 237 | struct mdma_timings_t mdma_timings_33[] = |
1da177e4 LT |
238 | { |
239 | { 240, 240, 480 }, | |
240 | { 180, 180, 360 }, | |
241 | { 135, 135, 270 }, | |
242 | { 120, 120, 240 }, | |
243 | { 105, 105, 210 }, | |
244 | { 90, 90, 180 }, | |
245 | { 75, 75, 150 }, | |
246 | { 75, 45, 120 }, | |
247 | { 0, 0, 0 } | |
248 | }; | |
249 | ||
aacaf9bd | 250 | struct mdma_timings_t mdma_timings_33k[] = |
1da177e4 LT |
251 | { |
252 | { 240, 240, 480 }, | |
253 | { 180, 180, 360 }, | |
254 | { 150, 150, 300 }, | |
255 | { 120, 120, 240 }, | |
256 | { 90, 120, 210 }, | |
257 | { 90, 90, 180 }, | |
258 | { 90, 60, 150 }, | |
259 | { 90, 30, 120 }, | |
260 | { 0, 0, 0 } | |
261 | }; | |
262 | ||
aacaf9bd | 263 | struct mdma_timings_t mdma_timings_66[] = |
1da177e4 LT |
264 | { |
265 | { 240, 240, 480 }, | |
266 | { 180, 180, 360 }, | |
267 | { 135, 135, 270 }, | |
268 | { 120, 120, 240 }, | |
269 | { 105, 105, 210 }, | |
270 | { 90, 90, 180 }, | |
271 | { 90, 75, 165 }, | |
272 | { 75, 45, 120 }, | |
273 | { 0, 0, 0 } | |
274 | }; | |
275 | ||
276 | /* KeyLargo ATA-4 Ultra DMA timings (rounded) */ | |
277 | struct { | |
278 | int addrSetup; /* ??? */ | |
279 | int rdy2pause; | |
280 | int wrDataSetup; | |
aacaf9bd | 281 | } kl66_udma_timings[] = |
1da177e4 LT |
282 | { |
283 | { 0, 180, 120 }, /* Mode 0 */ | |
284 | { 0, 150, 90 }, /* 1 */ | |
285 | { 0, 120, 60 }, /* 2 */ | |
286 | { 0, 90, 45 }, /* 3 */ | |
287 | { 0, 90, 30 } /* 4 */ | |
288 | }; | |
289 | ||
290 | /* UniNorth 2 ATA/100 timings */ | |
291 | struct kauai_timing { | |
292 | int cycle_time; | |
293 | u32 timing_reg; | |
294 | }; | |
295 | ||
aacaf9bd | 296 | static struct kauai_timing kauai_pio_timings[] = |
1da177e4 LT |
297 | { |
298 | { 930 , 0x08000fff }, | |
299 | { 600 , 0x08000a92 }, | |
300 | { 383 , 0x0800060f }, | |
301 | { 360 , 0x08000492 }, | |
302 | { 330 , 0x0800048f }, | |
303 | { 300 , 0x080003cf }, | |
304 | { 270 , 0x080003cc }, | |
305 | { 240 , 0x0800038b }, | |
306 | { 239 , 0x0800030c }, | |
307 | { 180 , 0x05000249 }, | |
c15d5d43 BZ |
308 | { 120 , 0x04000148 }, |
309 | { 0 , 0 }, | |
1da177e4 LT |
310 | }; |
311 | ||
aacaf9bd | 312 | static struct kauai_timing kauai_mdma_timings[] = |
1da177e4 LT |
313 | { |
314 | { 1260 , 0x00fff000 }, | |
315 | { 480 , 0x00618000 }, | |
316 | { 360 , 0x00492000 }, | |
317 | { 270 , 0x0038e000 }, | |
318 | { 240 , 0x0030c000 }, | |
319 | { 210 , 0x002cb000 }, | |
320 | { 180 , 0x00249000 }, | |
321 | { 150 , 0x00209000 }, | |
322 | { 120 , 0x00148000 }, | |
323 | { 0 , 0 }, | |
324 | }; | |
325 | ||
aacaf9bd | 326 | static struct kauai_timing kauai_udma_timings[] = |
1da177e4 LT |
327 | { |
328 | { 120 , 0x000070c0 }, | |
329 | { 90 , 0x00005d80 }, | |
330 | { 60 , 0x00004a60 }, | |
331 | { 45 , 0x00003a50 }, | |
332 | { 30 , 0x00002a30 }, | |
333 | { 20 , 0x00002921 }, | |
334 | { 0 , 0 }, | |
335 | }; | |
336 | ||
aacaf9bd | 337 | static struct kauai_timing shasta_pio_timings[] = |
1da177e4 LT |
338 | { |
339 | { 930 , 0x08000fff }, | |
340 | { 600 , 0x0A000c97 }, | |
341 | { 383 , 0x07000712 }, | |
342 | { 360 , 0x040003cd }, | |
343 | { 330 , 0x040003cd }, | |
344 | { 300 , 0x040003cd }, | |
345 | { 270 , 0x040003cd }, | |
346 | { 240 , 0x040003cd }, | |
347 | { 239 , 0x040003cd }, | |
348 | { 180 , 0x0400028b }, | |
c15d5d43 BZ |
349 | { 120 , 0x0400010a }, |
350 | { 0 , 0 }, | |
1da177e4 LT |
351 | }; |
352 | ||
aacaf9bd | 353 | static struct kauai_timing shasta_mdma_timings[] = |
1da177e4 LT |
354 | { |
355 | { 1260 , 0x00fff000 }, | |
356 | { 480 , 0x00820800 }, | |
357 | { 360 , 0x00820800 }, | |
358 | { 270 , 0x00820800 }, | |
359 | { 240 , 0x00820800 }, | |
360 | { 210 , 0x00820800 }, | |
361 | { 180 , 0x00820800 }, | |
362 | { 150 , 0x0028b000 }, | |
363 | { 120 , 0x001ca000 }, | |
364 | { 0 , 0 }, | |
365 | }; | |
366 | ||
aacaf9bd | 367 | static struct kauai_timing shasta_udma133_timings[] = |
1da177e4 LT |
368 | { |
369 | { 120 , 0x00035901, }, | |
370 | { 90 , 0x000348b1, }, | |
371 | { 60 , 0x00033881, }, | |
372 | { 45 , 0x00033861, }, | |
373 | { 30 , 0x00033841, }, | |
374 | { 20 , 0x00033031, }, | |
375 | { 15 , 0x00033021, }, | |
376 | { 0 , 0 }, | |
377 | }; | |
378 | ||
379 | ||
380 | static inline u32 | |
381 | kauai_lookup_timing(struct kauai_timing* table, int cycle_time) | |
382 | { | |
383 | int i; | |
384 | ||
385 | for (i=0; table[i].cycle_time; i++) | |
386 | if (cycle_time > table[i+1].cycle_time) | |
387 | return table[i].timing_reg; | |
90a87ea4 | 388 | BUG(); |
1da177e4 LT |
389 | return 0; |
390 | } | |
391 | ||
392 | /* allow up to 256 DBDMA commands per xfer */ | |
393 | #define MAX_DCMDS 256 | |
394 | ||
395 | /* | |
396 | * Wait 1s for disk to answer on IDE bus after a hard reset | |
397 | * of the device (via GPIO/FCR). | |
398 | * | |
399 | * Some devices seem to "pollute" the bus even after dropping | |
400 | * the BSY bit (typically some combo drives slave on the UDMA | |
401 | * bus) after a hard reset. Since we hard reset all drives on | |
402 | * KeyLargo ATA66, we have to keep that delay around. I may end | |
403 | * up not hard resetting anymore on these and keep the delay only | |
404 | * for older interfaces instead (we have to reset when coming | |
405 | * from MacOS...) --BenH. | |
406 | */ | |
407 | #define IDE_WAKEUP_DELAY (1*HZ) | |
408 | ||
0d071922 | 409 | static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); |
1da177e4 | 410 | static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq); |
1da177e4 LT |
411 | static void pmac_ide_selectproc(ide_drive_t *drive); |
412 | static void pmac_ide_kauai_selectproc(ide_drive_t *drive); | |
413 | ||
414 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
415 | ||
23579a2a | 416 | #define PMAC_IDE_REG(x) \ |
4c3032d8 | 417 | ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) |
1da177e4 LT |
418 | |
419 | /* | |
420 | * Apply the timings of the proper unit (master/slave) to the shared | |
421 | * timing register when selecting that unit. This version is for | |
422 | * ASICs with a single timing register | |
423 | */ | |
aacaf9bd | 424 | static void |
1da177e4 LT |
425 | pmac_ide_selectproc(ide_drive_t *drive) |
426 | { | |
7b8797ac BZ |
427 | ide_hwif_t *hwif = drive->hwif; |
428 | pmac_ide_hwif_t *pmif = | |
429 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
430 | |
431 | if (pmif == NULL) | |
432 | return; | |
433 | ||
434 | if (drive->select.b.unit & 0x01) | |
435 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
436 | else | |
437 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
438 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
439 | } | |
440 | ||
441 | /* | |
442 | * Apply the timings of the proper unit (master/slave) to the shared | |
443 | * timing register when selecting that unit. This version is for | |
444 | * ASICs with a dual timing register (Kauai) | |
445 | */ | |
aacaf9bd | 446 | static void |
1da177e4 LT |
447 | pmac_ide_kauai_selectproc(ide_drive_t *drive) |
448 | { | |
7b8797ac BZ |
449 | ide_hwif_t *hwif = drive->hwif; |
450 | pmac_ide_hwif_t *pmif = | |
451 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
452 | |
453 | if (pmif == NULL) | |
454 | return; | |
455 | ||
456 | if (drive->select.b.unit & 0x01) { | |
457 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
458 | writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
459 | } else { | |
460 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
461 | writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
462 | } | |
463 | (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
464 | } | |
465 | ||
466 | /* | |
467 | * Force an update of controller timing values for a given drive | |
468 | */ | |
aacaf9bd | 469 | static void |
1da177e4 LT |
470 | pmac_ide_do_update_timings(ide_drive_t *drive) |
471 | { | |
7b8797ac BZ |
472 | ide_hwif_t *hwif = drive->hwif; |
473 | pmac_ide_hwif_t *pmif = | |
474 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
475 | |
476 | if (pmif == NULL) | |
477 | return; | |
478 | ||
479 | if (pmif->kind == controller_sh_ata6 || | |
480 | pmif->kind == controller_un_ata6 || | |
481 | pmif->kind == controller_k2_ata6) | |
482 | pmac_ide_kauai_selectproc(drive); | |
483 | else | |
484 | pmac_ide_selectproc(drive); | |
485 | } | |
486 | ||
f8c4bd0a | 487 | static void pmac_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port) |
1da177e4 LT |
488 | { |
489 | u32 tmp; | |
490 | ||
491 | writeb(value, (void __iomem *) port); | |
f8c4bd0a BZ |
492 | tmp = readl((void __iomem *)(hwif->io_ports.data_addr |
493 | + IDE_TIMING_CONFIG)); | |
1da177e4 LT |
494 | } |
495 | ||
1da177e4 LT |
496 | /* |
497 | * Old tuning functions (called on hdparm -p), sets up drive PIO timings | |
498 | */ | |
aacaf9bd | 499 | static void |
26bcb879 | 500 | pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 501 | { |
7b8797ac BZ |
502 | ide_hwif_t *hwif = drive->hwif; |
503 | pmac_ide_hwif_t *pmif = | |
504 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
8a97206e | 505 | struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio); |
0b46ff2e | 506 | u32 *timings, t; |
1da177e4 LT |
507 | unsigned accessTicks, recTicks; |
508 | unsigned accessTime, recTime; | |
7dd00083 BZ |
509 | unsigned int cycle_time; |
510 | ||
1da177e4 LT |
511 | if (pmif == NULL) |
512 | return; | |
513 | ||
514 | /* which drive is it ? */ | |
515 | timings = &pmif->timings[drive->select.b.unit & 0x01]; | |
0b46ff2e | 516 | t = *timings; |
1da177e4 | 517 | |
7dd00083 | 518 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 LT |
519 | |
520 | switch (pmif->kind) { | |
521 | case controller_sh_ata6: { | |
522 | /* 133Mhz cell */ | |
7dd00083 | 523 | u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time); |
0b46ff2e | 524 | t = (t & ~TR_133_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
525 | break; |
526 | } | |
527 | case controller_un_ata6: | |
528 | case controller_k2_ata6: { | |
529 | /* 100Mhz cell */ | |
7dd00083 | 530 | u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time); |
0b46ff2e | 531 | t = (t & ~TR_100_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
532 | break; |
533 | } | |
534 | case controller_kl_ata4: | |
535 | /* 66Mhz cell */ | |
8a97206e | 536 | recTime = cycle_time - tim->active - tim->setup; |
1da177e4 | 537 | recTime = max(recTime, 150U); |
8a97206e | 538 | accessTime = tim->active; |
1da177e4 LT |
539 | accessTime = max(accessTime, 150U); |
540 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
541 | accessTicks = min(accessTicks, 0x1fU); | |
542 | recTicks = SYSCLK_TICKS_66(recTime); | |
543 | recTicks = min(recTicks, 0x1fU); | |
0b46ff2e BH |
544 | t = (t & ~TR_66_PIO_MASK) | |
545 | (accessTicks << TR_66_PIO_ACCESS_SHIFT) | | |
546 | (recTicks << TR_66_PIO_RECOVERY_SHIFT); | |
1da177e4 LT |
547 | break; |
548 | default: { | |
549 | /* 33Mhz cell */ | |
550 | int ebit = 0; | |
8a97206e | 551 | recTime = cycle_time - tim->active - tim->setup; |
1da177e4 | 552 | recTime = max(recTime, 150U); |
8a97206e | 553 | accessTime = tim->active; |
1da177e4 LT |
554 | accessTime = max(accessTime, 150U); |
555 | accessTicks = SYSCLK_TICKS(accessTime); | |
556 | accessTicks = min(accessTicks, 0x1fU); | |
557 | accessTicks = max(accessTicks, 4U); | |
558 | recTicks = SYSCLK_TICKS(recTime); | |
559 | recTicks = min(recTicks, 0x1fU); | |
560 | recTicks = max(recTicks, 5U) - 4; | |
561 | if (recTicks > 9) { | |
562 | recTicks--; /* guess, but it's only for PIO0, so... */ | |
563 | ebit = 1; | |
564 | } | |
0b46ff2e | 565 | t = (t & ~TR_33_PIO_MASK) | |
1da177e4 LT |
566 | (accessTicks << TR_33_PIO_ACCESS_SHIFT) | |
567 | (recTicks << TR_33_PIO_RECOVERY_SHIFT); | |
568 | if (ebit) | |
0b46ff2e | 569 | t |= TR_33_PIO_E; |
1da177e4 LT |
570 | break; |
571 | } | |
572 | } | |
573 | ||
574 | #ifdef IDE_PMAC_DEBUG | |
575 | printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", | |
576 | drive->name, pio, *timings); | |
577 | #endif | |
578 | ||
0b46ff2e | 579 | *timings = t; |
c15d5d43 | 580 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
581 | } |
582 | ||
583 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
584 | ||
585 | /* | |
586 | * Calculate KeyLargo ATA/66 UDMA timings | |
587 | */ | |
aacaf9bd | 588 | static int |
1da177e4 LT |
589 | set_timings_udma_ata4(u32 *timings, u8 speed) |
590 | { | |
591 | unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; | |
592 | ||
593 | if (speed > XFER_UDMA_4) | |
594 | return 1; | |
595 | ||
596 | rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause); | |
597 | wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup); | |
598 | addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup); | |
599 | ||
600 | *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) | | |
601 | (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | | |
602 | (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) | | |
603 | (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) | | |
604 | TR_66_UDMA_EN; | |
605 | #ifdef IDE_PMAC_DEBUG | |
606 | printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", | |
607 | speed & 0xf, *timings); | |
608 | #endif | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | /* | |
614 | * Calculate Kauai ATA/100 UDMA timings | |
615 | */ | |
aacaf9bd | 616 | static int |
1da177e4 LT |
617 | set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
618 | { | |
619 | struct ide_timing *t = ide_timing_find_mode(speed); | |
620 | u32 tr; | |
621 | ||
622 | if (speed > XFER_UDMA_5 || t == NULL) | |
623 | return 1; | |
624 | tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma); | |
1da177e4 LT |
625 | *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr; |
626 | *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN; | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | /* | |
632 | * Calculate Shasta ATA/133 UDMA timings | |
633 | */ | |
aacaf9bd | 634 | static int |
1da177e4 LT |
635 | set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
636 | { | |
637 | struct ide_timing *t = ide_timing_find_mode(speed); | |
638 | u32 tr; | |
639 | ||
640 | if (speed > XFER_UDMA_6 || t == NULL) | |
641 | return 1; | |
642 | tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma); | |
1da177e4 LT |
643 | *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr; |
644 | *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN; | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | /* | |
650 | * Calculate MDMA timings for all cells | |
651 | */ | |
90f72eca | 652 | static void |
1da177e4 | 653 | set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, |
90f72eca | 654 | u8 speed) |
1da177e4 LT |
655 | { |
656 | int cycleTime, accessTime = 0, recTime = 0; | |
657 | unsigned accessTicks, recTicks; | |
90f72eca | 658 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
659 | struct mdma_timings_t* tm = NULL; |
660 | int i; | |
661 | ||
662 | /* Get default cycle time for mode */ | |
663 | switch(speed & 0xf) { | |
664 | case 0: cycleTime = 480; break; | |
665 | case 1: cycleTime = 150; break; | |
666 | case 2: cycleTime = 120; break; | |
667 | default: | |
90f72eca BZ |
668 | BUG(); |
669 | break; | |
1da177e4 | 670 | } |
90f72eca BZ |
671 | |
672 | /* Check if drive provides explicit DMA cycle time */ | |
673 | if ((id->field_valid & 2) && id->eide_dma_time) | |
674 | cycleTime = max_t(int, id->eide_dma_time, cycleTime); | |
675 | ||
1da177e4 LT |
676 | /* OHare limits according to some old Apple sources */ |
677 | if ((intf_type == controller_ohare) && (cycleTime < 150)) | |
678 | cycleTime = 150; | |
679 | /* Get the proper timing array for this controller */ | |
680 | switch(intf_type) { | |
681 | case controller_sh_ata6: | |
682 | case controller_un_ata6: | |
683 | case controller_k2_ata6: | |
684 | break; | |
685 | case controller_kl_ata4: | |
686 | tm = mdma_timings_66; | |
687 | break; | |
688 | case controller_kl_ata3: | |
689 | tm = mdma_timings_33k; | |
690 | break; | |
691 | default: | |
692 | tm = mdma_timings_33; | |
693 | break; | |
694 | } | |
695 | if (tm != NULL) { | |
696 | /* Lookup matching access & recovery times */ | |
697 | i = -1; | |
698 | for (;;) { | |
699 | if (tm[i+1].cycleTime < cycleTime) | |
700 | break; | |
701 | i++; | |
702 | } | |
1da177e4 LT |
703 | cycleTime = tm[i].cycleTime; |
704 | accessTime = tm[i].accessTime; | |
705 | recTime = tm[i].recoveryTime; | |
706 | ||
707 | #ifdef IDE_PMAC_DEBUG | |
708 | printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", | |
709 | drive->name, cycleTime, accessTime, recTime); | |
710 | #endif | |
711 | } | |
712 | switch(intf_type) { | |
713 | case controller_sh_ata6: { | |
714 | /* 133Mhz cell */ | |
715 | u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime); | |
1da177e4 LT |
716 | *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr; |
717 | *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN; | |
718 | } | |
719 | case controller_un_ata6: | |
720 | case controller_k2_ata6: { | |
721 | /* 100Mhz cell */ | |
722 | u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime); | |
1da177e4 LT |
723 | *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr; |
724 | *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN; | |
725 | } | |
726 | break; | |
727 | case controller_kl_ata4: | |
728 | /* 66Mhz cell */ | |
729 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
730 | accessTicks = min(accessTicks, 0x1fU); | |
731 | accessTicks = max(accessTicks, 0x1U); | |
732 | recTicks = SYSCLK_TICKS_66(recTime); | |
733 | recTicks = min(recTicks, 0x1fU); | |
734 | recTicks = max(recTicks, 0x3U); | |
735 | /* Clear out mdma bits and disable udma */ | |
736 | *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) | | |
737 | (accessTicks << TR_66_MDMA_ACCESS_SHIFT) | | |
738 | (recTicks << TR_66_MDMA_RECOVERY_SHIFT); | |
739 | break; | |
740 | case controller_kl_ata3: | |
741 | /* 33Mhz cell on KeyLargo */ | |
742 | accessTicks = SYSCLK_TICKS(accessTime); | |
743 | accessTicks = max(accessTicks, 1U); | |
744 | accessTicks = min(accessTicks, 0x1fU); | |
745 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
746 | recTicks = SYSCLK_TICKS(recTime); | |
747 | recTicks = max(recTicks, 1U); | |
748 | recTicks = min(recTicks, 0x1fU); | |
749 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
750 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
751 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
752 | break; | |
753 | default: { | |
754 | /* 33Mhz cell on others */ | |
755 | int halfTick = 0; | |
756 | int origAccessTime = accessTime; | |
757 | int origRecTime = recTime; | |
758 | ||
759 | accessTicks = SYSCLK_TICKS(accessTime); | |
760 | accessTicks = max(accessTicks, 1U); | |
761 | accessTicks = min(accessTicks, 0x1fU); | |
762 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
763 | recTicks = SYSCLK_TICKS(recTime); | |
764 | recTicks = max(recTicks, 2U) - 1; | |
765 | recTicks = min(recTicks, 0x1fU); | |
766 | recTime = (recTicks + 1) * IDE_SYSCLK_NS; | |
767 | if ((accessTicks > 1) && | |
768 | ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) && | |
769 | ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) { | |
770 | halfTick = 1; | |
771 | accessTicks--; | |
772 | } | |
773 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
774 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
775 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
776 | if (halfTick) | |
777 | *timings |= TR_33_MDMA_HALFTICK; | |
778 | } | |
779 | } | |
780 | #ifdef IDE_PMAC_DEBUG | |
781 | printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", | |
782 | drive->name, speed & 0xf, *timings); | |
783 | #endif | |
1da177e4 LT |
784 | } |
785 | #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
786 | ||
88b2b32b | 787 | static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 788 | { |
7b8797ac BZ |
789 | ide_hwif_t *hwif = drive->hwif; |
790 | pmac_ide_hwif_t *pmif = | |
791 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
792 | int unit = (drive->select.b.unit & 0x01); |
793 | int ret = 0; | |
085798b1 | 794 | u32 *timings, *timings2, tl[2]; |
1da177e4 | 795 | |
1da177e4 LT |
796 | timings = &pmif->timings[unit]; |
797 | timings2 = &pmif->timings[unit+2]; | |
085798b1 BZ |
798 | |
799 | /* Copy timings to local image */ | |
800 | tl[0] = *timings; | |
801 | tl[1] = *timings2; | |
802 | ||
1da177e4 | 803 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC |
4db90a14 BZ |
804 | if (speed >= XFER_UDMA_0) { |
805 | if (pmif->kind == controller_kl_ata4) | |
806 | ret = set_timings_udma_ata4(&tl[0], speed); | |
807 | else if (pmif->kind == controller_un_ata6 | |
808 | || pmif->kind == controller_k2_ata6) | |
809 | ret = set_timings_udma_ata6(&tl[0], &tl[1], speed); | |
810 | else if (pmif->kind == controller_sh_ata6) | |
811 | ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); | |
812 | else | |
813 | ret = -1; | |
814 | } else | |
815 | set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); | |
1da177e4 | 816 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ |
1da177e4 | 817 | if (ret) |
88b2b32b | 818 | return; |
085798b1 BZ |
819 | |
820 | /* Apply timings to controller */ | |
821 | *timings = tl[0]; | |
822 | *timings2 = tl[1]; | |
823 | ||
1da177e4 | 824 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
825 | } |
826 | ||
827 | /* | |
828 | * Blast some well known "safe" values to the timing registers at init or | |
829 | * wakeup from sleep time, before we do real calculation | |
830 | */ | |
aacaf9bd | 831 | static void |
1da177e4 LT |
832 | sanitize_timings(pmac_ide_hwif_t *pmif) |
833 | { | |
834 | unsigned int value, value2 = 0; | |
835 | ||
836 | switch(pmif->kind) { | |
837 | case controller_sh_ata6: | |
838 | value = 0x0a820c97; | |
839 | value2 = 0x00033031; | |
840 | break; | |
841 | case controller_un_ata6: | |
842 | case controller_k2_ata6: | |
843 | value = 0x08618a92; | |
844 | value2 = 0x00002921; | |
845 | break; | |
846 | case controller_kl_ata4: | |
847 | value = 0x0008438c; | |
848 | break; | |
849 | case controller_kl_ata3: | |
850 | value = 0x00084526; | |
851 | break; | |
852 | case controller_heathrow: | |
853 | case controller_ohare: | |
854 | default: | |
855 | value = 0x00074526; | |
856 | break; | |
857 | } | |
858 | pmif->timings[0] = pmif->timings[1] = value; | |
859 | pmif->timings[2] = pmif->timings[3] = value2; | |
860 | } | |
861 | ||
1da177e4 LT |
862 | /* Suspend call back, should be called after the child devices |
863 | * have actually been suspended | |
864 | */ | |
7b8797ac | 865 | static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif) |
1da177e4 | 866 | { |
1da177e4 LT |
867 | /* We clear the timings */ |
868 | pmif->timings[0] = 0; | |
869 | pmif->timings[1] = 0; | |
870 | ||
616299af BH |
871 | disable_irq(pmif->irq); |
872 | ||
1da177e4 LT |
873 | /* The media bay will handle itself just fine */ |
874 | if (pmif->mediabay) | |
875 | return 0; | |
876 | ||
877 | /* Kauai has bus control FCRs directly here */ | |
878 | if (pmif->kauai_fcr) { | |
879 | u32 fcr = readl(pmif->kauai_fcr); | |
880 | fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); | |
881 | writel(fcr, pmif->kauai_fcr); | |
882 | } | |
883 | ||
884 | /* Disable the bus on older machines and the cell on kauai */ | |
885 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, | |
886 | 0); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | /* Resume call back, should be called before the child devices | |
892 | * are resumed | |
893 | */ | |
7b8797ac | 894 | static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif) |
1da177e4 | 895 | { |
1da177e4 LT |
896 | /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ |
897 | if (!pmif->mediabay) { | |
898 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); | |
899 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); | |
900 | msleep(10); | |
901 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0); | |
1da177e4 LT |
902 | |
903 | /* Kauai has it different */ | |
904 | if (pmif->kauai_fcr) { | |
905 | u32 fcr = readl(pmif->kauai_fcr); | |
906 | fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; | |
907 | writel(fcr, pmif->kauai_fcr); | |
908 | } | |
616299af BH |
909 | |
910 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1da177e4 LT |
911 | } |
912 | ||
913 | /* Sanitize drive timings */ | |
914 | sanitize_timings(pmif); | |
915 | ||
616299af BH |
916 | enable_irq(pmif->irq); |
917 | ||
1da177e4 LT |
918 | return 0; |
919 | } | |
920 | ||
07a6c66d BZ |
921 | static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) |
922 | { | |
7b8797ac BZ |
923 | pmac_ide_hwif_t *pmif = |
924 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
07a6c66d BZ |
925 | struct device_node *np = pmif->node; |
926 | const char *cable = of_get_property(np, "cable-type", NULL); | |
927 | ||
928 | /* Get cable type from device-tree. */ | |
929 | if (cable && !strncmp(cable, "80-", 3)) | |
930 | return ATA_CBL_PATA80; | |
931 | ||
932 | /* | |
933 | * G5's seem to have incorrect cable type in device-tree. | |
934 | * Let's assume they have a 80 conductor cable, this seem | |
935 | * to be always the case unless the user mucked around. | |
936 | */ | |
937 | if (of_device_is_compatible(np, "K2-UATA") || | |
938 | of_device_is_compatible(np, "shasta-ata")) | |
939 | return ATA_CBL_PATA80; | |
940 | ||
941 | return ATA_CBL_PATA40; | |
942 | } | |
943 | ||
07eb106f BZ |
944 | static void pmac_ide_init_dev(ide_drive_t *drive) |
945 | { | |
946 | ide_hwif_t *hwif = drive->hwif; | |
947 | pmac_ide_hwif_t *pmif = | |
948 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
949 | ||
950 | if (pmif->mediabay) { | |
951 | #ifdef CONFIG_PMAC_MEDIABAY | |
952 | if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) { | |
953 | drive->noprobe = 0; | |
954 | return; | |
955 | } | |
956 | #endif | |
957 | drive->noprobe = 1; | |
958 | } | |
959 | } | |
960 | ||
ac95beed | 961 | static const struct ide_port_ops pmac_ide_ata6_port_ops = { |
07eb106f | 962 | .init_dev = pmac_ide_init_dev, |
ac95beed BZ |
963 | .set_pio_mode = pmac_ide_set_pio_mode, |
964 | .set_dma_mode = pmac_ide_set_dma_mode, | |
965 | .selectproc = pmac_ide_kauai_selectproc, | |
07a6c66d BZ |
966 | .cable_detect = pmac_ide_cable_detect, |
967 | }; | |
968 | ||
969 | static const struct ide_port_ops pmac_ide_ata4_port_ops = { | |
07eb106f | 970 | .init_dev = pmac_ide_init_dev, |
07a6c66d BZ |
971 | .set_pio_mode = pmac_ide_set_pio_mode, |
972 | .set_dma_mode = pmac_ide_set_dma_mode, | |
973 | .selectproc = pmac_ide_selectproc, | |
974 | .cable_detect = pmac_ide_cable_detect, | |
ac95beed BZ |
975 | }; |
976 | ||
977 | static const struct ide_port_ops pmac_ide_port_ops = { | |
07eb106f | 978 | .init_dev = pmac_ide_init_dev, |
ac95beed BZ |
979 | .set_pio_mode = pmac_ide_set_pio_mode, |
980 | .set_dma_mode = pmac_ide_set_dma_mode, | |
981 | .selectproc = pmac_ide_selectproc, | |
982 | }; | |
983 | ||
f37afdac | 984 | static const struct ide_dma_ops pmac_dma_ops; |
5e37bdc0 | 985 | |
c413b9b9 | 986 | static const struct ide_port_info pmac_port_info = { |
0d071922 | 987 | .init_dma = pmac_ide_init_dma, |
c413b9b9 | 988 | .chipset = ide_pmac, |
5e37bdc0 BZ |
989 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC |
990 | .dma_ops = &pmac_dma_ops, | |
991 | #endif | |
ac95beed | 992 | .port_ops = &pmac_ide_port_ops, |
c413b9b9 | 993 | .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | |
c413b9b9 | 994 | IDE_HFLAG_POST_SET_MODE | |
c5dd43ec | 995 | IDE_HFLAG_MMIO | |
c413b9b9 BZ |
996 | IDE_HFLAG_UNMASK_IRQS, |
997 | .pio_mask = ATA_PIO4, | |
998 | .mwdma_mask = ATA_MWDMA2, | |
999 | }; | |
1000 | ||
1da177e4 LT |
1001 | /* |
1002 | * Setup, register & probe an IDE channel driven by this driver, this is | |
5b16464a | 1003 | * called by one of the 2 probe functions (macio or PCI). |
1da177e4 | 1004 | */ |
468e4681 | 1005 | static int __devinit |
57c802e8 | 1006 | pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) |
1da177e4 LT |
1007 | { |
1008 | struct device_node *np = pmif->node; | |
018a3d1d | 1009 | const int *bidp; |
8447d9d5 | 1010 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
c413b9b9 | 1011 | struct ide_port_info d = pmac_port_info; |
1da177e4 | 1012 | |
1da177e4 | 1013 | pmif->broken_dma = pmif->broken_dma_warn = 0; |
c413b9b9 | 1014 | if (of_device_is_compatible(np, "shasta-ata")) { |
1da177e4 | 1015 | pmif->kind = controller_sh_ata6; |
ac95beed | 1016 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1017 | d.udma_mask = ATA_UDMA6; |
1018 | } else if (of_device_is_compatible(np, "kauai-ata")) { | |
1da177e4 | 1019 | pmif->kind = controller_un_ata6; |
ac95beed | 1020 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1021 | d.udma_mask = ATA_UDMA5; |
1022 | } else if (of_device_is_compatible(np, "K2-UATA")) { | |
1da177e4 | 1023 | pmif->kind = controller_k2_ata6; |
ac95beed | 1024 | d.port_ops = &pmac_ide_ata6_port_ops; |
c413b9b9 BZ |
1025 | d.udma_mask = ATA_UDMA5; |
1026 | } else if (of_device_is_compatible(np, "keylargo-ata")) { | |
1027 | if (strcmp(np->name, "ata-4") == 0) { | |
1da177e4 | 1028 | pmif->kind = controller_kl_ata4; |
07a6c66d | 1029 | d.port_ops = &pmac_ide_ata4_port_ops; |
c413b9b9 BZ |
1030 | d.udma_mask = ATA_UDMA4; |
1031 | } else | |
1da177e4 | 1032 | pmif->kind = controller_kl_ata3; |
c413b9b9 | 1033 | } else if (of_device_is_compatible(np, "heathrow-ata")) { |
1da177e4 | 1034 | pmif->kind = controller_heathrow; |
c413b9b9 | 1035 | } else { |
1da177e4 LT |
1036 | pmif->kind = controller_ohare; |
1037 | pmif->broken_dma = 1; | |
1038 | } | |
1039 | ||
40cd3a45 | 1040 | bidp = of_get_property(np, "AAPL,bus-id", NULL); |
1da177e4 LT |
1041 | pmif->aapl_bus_id = bidp ? *bidp : 0; |
1042 | ||
1da177e4 LT |
1043 | /* On Kauai-type controllers, we make sure the FCR is correct */ |
1044 | if (pmif->kauai_fcr) | |
1045 | writel(KAUAI_FCR_UATA_MAGIC | | |
1046 | KAUAI_FCR_UATA_RESET_N | | |
1047 | KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); | |
1048 | ||
1049 | pmif->mediabay = 0; | |
1050 | ||
1051 | /* Make sure we have sane timings */ | |
1052 | sanitize_timings(pmif); | |
1053 | ||
1054 | #ifndef CONFIG_PPC64 | |
1055 | /* XXX FIXME: Media bay stuff need re-organizing */ | |
1056 | if (np->parent && np->parent->name | |
1057 | && strcasecmp(np->parent->name, "media-bay") == 0) { | |
8c870933 | 1058 | #ifdef CONFIG_PMAC_MEDIABAY |
2dde7861 BZ |
1059 | media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, |
1060 | hwif); | |
8c870933 | 1061 | #endif /* CONFIG_PMAC_MEDIABAY */ |
1da177e4 LT |
1062 | pmif->mediabay = 1; |
1063 | if (!bidp) | |
1064 | pmif->aapl_bus_id = 1; | |
1065 | } else if (pmif->kind == controller_ohare) { | |
1066 | /* The code below is having trouble on some ohare machines | |
1067 | * (timing related ?). Until I can put my hand on one of these | |
1068 | * units, I keep the old way | |
1069 | */ | |
1070 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); | |
1071 | } else | |
1072 | #endif | |
1073 | { | |
1074 | /* This is necessary to enable IDE when net-booting */ | |
1075 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); | |
1076 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); | |
1077 | msleep(10); | |
1078 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0); | |
1079 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1080 | } | |
1081 | ||
1082 | /* Setup MMIO ops */ | |
1083 | default_hwif_mmiops(hwif); | |
1084 | hwif->OUTBSYNC = pmac_outbsync; | |
1085 | ||
57c802e8 | 1086 | ide_init_port_hw(hwif, hw); |
1da177e4 | 1087 | |
1da177e4 LT |
1088 | printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", |
1089 | hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, | |
1090 | pmif->mediabay ? " (mediabay)" : "", hwif->irq); | |
e53cd458 | 1091 | |
8447d9d5 | 1092 | idx[0] = hwif->index; |
1da177e4 | 1093 | |
c413b9b9 | 1094 | ide_device_add(idx, &d); |
5cbf79cd | 1095 | |
1da177e4 LT |
1096 | return 0; |
1097 | } | |
1098 | ||
5c58666f BZ |
1099 | static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base) |
1100 | { | |
1101 | int i; | |
1102 | ||
1103 | for (i = 0; i < 8; ++i) | |
4c3032d8 BZ |
1104 | hw->io_ports_array[i] = base + i * 0x10; |
1105 | ||
1106 | hw->io_ports.ctl_addr = base + 0x160; | |
5c58666f BZ |
1107 | } |
1108 | ||
1da177e4 LT |
1109 | /* |
1110 | * Attach to a macio probed interface | |
1111 | */ | |
1112 | static int __devinit | |
5e655772 | 1113 | pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
1114 | { |
1115 | void __iomem *base; | |
1116 | unsigned long regbase; | |
1da177e4 LT |
1117 | ide_hwif_t *hwif; |
1118 | pmac_ide_hwif_t *pmif; | |
939b0f1d | 1119 | int irq, rc; |
57c802e8 | 1120 | hw_regs_t hw; |
1da177e4 | 1121 | |
5297a3e5 BZ |
1122 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); |
1123 | if (pmif == NULL) | |
1124 | return -ENOMEM; | |
1125 | ||
939b0f1d BZ |
1126 | hwif = ide_find_port(); |
1127 | if (hwif == NULL) { | |
1da177e4 LT |
1128 | printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n"); |
1129 | printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1130 | rc = -ENODEV; |
1131 | goto out_free_pmif; | |
1da177e4 LT |
1132 | } |
1133 | ||
cc5d0189 | 1134 | if (macio_resource_count(mdev) == 0) { |
939b0f1d BZ |
1135 | printk(KERN_WARNING "ide-pmac: no address for %s\n", |
1136 | mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1137 | rc = -ENXIO; |
1138 | goto out_free_pmif; | |
1da177e4 LT |
1139 | } |
1140 | ||
1141 | /* Request memory resource for IO ports */ | |
1142 | if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) { | |
939b0f1d BZ |
1143 | printk(KERN_ERR "ide-pmac: can't request MMIO resource for " |
1144 | "%s!\n", mdev->ofdev.node->full_name); | |
5297a3e5 BZ |
1145 | rc = -EBUSY; |
1146 | goto out_free_pmif; | |
1da177e4 LT |
1147 | } |
1148 | ||
1149 | /* XXX This is bogus. Should be fixed in the registry by checking | |
1150 | * the kind of host interrupt controller, a bit like gatwick | |
1151 | * fixes in irq.c. That works well enough for the single case | |
1152 | * where that happens though... | |
1153 | */ | |
1154 | if (macio_irq_count(mdev) == 0) { | |
939b0f1d BZ |
1155 | printk(KERN_WARNING "ide-pmac: no intrs for device %s, using " |
1156 | "13\n", mdev->ofdev.node->full_name); | |
69917c26 | 1157 | irq = irq_create_mapping(NULL, 13); |
1da177e4 LT |
1158 | } else |
1159 | irq = macio_irq(mdev, 0); | |
1160 | ||
1161 | base = ioremap(macio_resource_start(mdev, 0), 0x400); | |
1162 | regbase = (unsigned long) base; | |
1163 | ||
1da177e4 LT |
1164 | pmif->mdev = mdev; |
1165 | pmif->node = mdev->ofdev.node; | |
1166 | pmif->regbase = regbase; | |
1167 | pmif->irq = irq; | |
1168 | pmif->kauai_fcr = NULL; | |
1169 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1170 | if (macio_resource_count(mdev) >= 2) { | |
1171 | if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) | |
939b0f1d BZ |
1172 | printk(KERN_WARNING "ide-pmac: can't request DMA " |
1173 | "resource for %s!\n", | |
1174 | mdev->ofdev.node->full_name); | |
1da177e4 LT |
1175 | else |
1176 | pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); | |
1177 | } else | |
1178 | pmif->dma_regs = NULL; | |
1179 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
7b8797ac | 1180 | dev_set_drvdata(&mdev->ofdev.dev, pmif); |
1da177e4 | 1181 | |
57c802e8 | 1182 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1183 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 | 1184 | hw.irq = irq; |
c56c5648 BZ |
1185 | hw.dev = &mdev->bus->pdev->dev; |
1186 | hw.parent = &mdev->ofdev.dev; | |
57c802e8 BZ |
1187 | |
1188 | rc = pmac_ide_setup_device(pmif, hwif, &hw); | |
1da177e4 LT |
1189 | if (rc != 0) { |
1190 | /* The inteface is released to the common IDE layer */ | |
1191 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1192 | iounmap(base); | |
ed908fa1 | 1193 | if (pmif->dma_regs) { |
1da177e4 | 1194 | iounmap(pmif->dma_regs); |
ed908fa1 BZ |
1195 | macio_release_resource(mdev, 1); |
1196 | } | |
1da177e4 | 1197 | macio_release_resource(mdev, 0); |
5297a3e5 | 1198 | kfree(pmif); |
1da177e4 LT |
1199 | } |
1200 | ||
1201 | return rc; | |
5297a3e5 BZ |
1202 | |
1203 | out_free_pmif: | |
1204 | kfree(pmif); | |
1205 | return rc; | |
1da177e4 LT |
1206 | } |
1207 | ||
1208 | static int | |
8b4b8a24 | 1209 | pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) |
1da177e4 | 1210 | { |
7b8797ac BZ |
1211 | pmac_ide_hwif_t *pmif = |
1212 | (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1213 | int rc = 0; | |
1da177e4 | 1214 | |
8b4b8a24 | 1215 | if (mesg.event != mdev->ofdev.dev.power.power_state.event |
3a2d5b70 | 1216 | && (mesg.event & PM_EVENT_SLEEP)) { |
7b8797ac | 1217 | rc = pmac_ide_do_suspend(pmif); |
1da177e4 | 1218 | if (rc == 0) |
8b4b8a24 | 1219 | mdev->ofdev.dev.power.power_state = mesg; |
1da177e4 LT |
1220 | } |
1221 | ||
1222 | return rc; | |
1223 | } | |
1224 | ||
1225 | static int | |
1226 | pmac_ide_macio_resume(struct macio_dev *mdev) | |
1227 | { | |
7b8797ac BZ |
1228 | pmac_ide_hwif_t *pmif = |
1229 | (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1230 | int rc = 0; | |
1231 | ||
ca078bae | 1232 | if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) { |
7b8797ac | 1233 | rc = pmac_ide_do_resume(pmif); |
1da177e4 | 1234 | if (rc == 0) |
829ca9a3 | 1235 | mdev->ofdev.dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1236 | } |
1237 | ||
1238 | return rc; | |
1239 | } | |
1240 | ||
1241 | /* | |
1242 | * Attach to a PCI probed interface | |
1243 | */ | |
1244 | static int __devinit | |
1245 | pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) | |
1246 | { | |
1247 | ide_hwif_t *hwif; | |
1248 | struct device_node *np; | |
1249 | pmac_ide_hwif_t *pmif; | |
1250 | void __iomem *base; | |
1251 | unsigned long rbase, rlen; | |
939b0f1d | 1252 | int rc; |
57c802e8 | 1253 | hw_regs_t hw; |
1da177e4 LT |
1254 | |
1255 | np = pci_device_to_OF_node(pdev); | |
1256 | if (np == NULL) { | |
1257 | printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n"); | |
1258 | return -ENODEV; | |
1259 | } | |
5297a3e5 BZ |
1260 | |
1261 | pmif = kzalloc(sizeof(*pmif), GFP_KERNEL); | |
1262 | if (pmif == NULL) | |
1263 | return -ENOMEM; | |
1264 | ||
939b0f1d BZ |
1265 | hwif = ide_find_port(); |
1266 | if (hwif == NULL) { | |
1da177e4 LT |
1267 | printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n"); |
1268 | printk(KERN_ERR " %s\n", np->full_name); | |
5297a3e5 BZ |
1269 | rc = -ENODEV; |
1270 | goto out_free_pmif; | |
1da177e4 LT |
1271 | } |
1272 | ||
1da177e4 | 1273 | if (pci_enable_device(pdev)) { |
939b0f1d BZ |
1274 | printk(KERN_WARNING "ide-pmac: Can't enable PCI device for " |
1275 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1276 | rc = -ENXIO; |
1277 | goto out_free_pmif; | |
1da177e4 LT |
1278 | } |
1279 | pci_set_master(pdev); | |
1280 | ||
1281 | if (pci_request_regions(pdev, "Kauai ATA")) { | |
939b0f1d BZ |
1282 | printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for " |
1283 | "%s\n", np->full_name); | |
5297a3e5 BZ |
1284 | rc = -ENXIO; |
1285 | goto out_free_pmif; | |
1da177e4 LT |
1286 | } |
1287 | ||
1da177e4 LT |
1288 | pmif->mdev = NULL; |
1289 | pmif->node = np; | |
1290 | ||
1291 | rbase = pci_resource_start(pdev, 0); | |
1292 | rlen = pci_resource_len(pdev, 0); | |
1293 | ||
1294 | base = ioremap(rbase, rlen); | |
1295 | pmif->regbase = (unsigned long) base + 0x2000; | |
1296 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1297 | pmif->dma_regs = base + 0x1000; | |
1298 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1299 | pmif->kauai_fcr = base; | |
1300 | pmif->irq = pdev->irq; | |
1301 | ||
7b8797ac | 1302 | pci_set_drvdata(pdev, pmif); |
1da177e4 | 1303 | |
57c802e8 | 1304 | memset(&hw, 0, sizeof(hw)); |
5c58666f | 1305 | pmac_ide_init_ports(&hw, pmif->regbase); |
57c802e8 BZ |
1306 | hw.irq = pdev->irq; |
1307 | hw.dev = &pdev->dev; | |
1308 | ||
1309 | rc = pmac_ide_setup_device(pmif, hwif, &hw); | |
1da177e4 LT |
1310 | if (rc != 0) { |
1311 | /* The inteface is released to the common IDE layer */ | |
1312 | pci_set_drvdata(pdev, NULL); | |
1313 | iounmap(base); | |
1da177e4 | 1314 | pci_release_regions(pdev); |
5297a3e5 | 1315 | kfree(pmif); |
1da177e4 LT |
1316 | } |
1317 | ||
1318 | return rc; | |
5297a3e5 BZ |
1319 | |
1320 | out_free_pmif: | |
1321 | kfree(pmif); | |
1322 | return rc; | |
1da177e4 LT |
1323 | } |
1324 | ||
1325 | static int | |
8b4b8a24 | 1326 | pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1da177e4 | 1327 | { |
7b8797ac BZ |
1328 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); |
1329 | int rc = 0; | |
1330 | ||
8b4b8a24 | 1331 | if (mesg.event != pdev->dev.power.power_state.event |
3a2d5b70 | 1332 | && (mesg.event & PM_EVENT_SLEEP)) { |
7b8797ac | 1333 | rc = pmac_ide_do_suspend(pmif); |
1da177e4 | 1334 | if (rc == 0) |
8b4b8a24 | 1335 | pdev->dev.power.power_state = mesg; |
1da177e4 LT |
1336 | } |
1337 | ||
1338 | return rc; | |
1339 | } | |
1340 | ||
1341 | static int | |
1342 | pmac_ide_pci_resume(struct pci_dev *pdev) | |
1343 | { | |
7b8797ac BZ |
1344 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev); |
1345 | int rc = 0; | |
1346 | ||
ca078bae | 1347 | if (pdev->dev.power.power_state.event != PM_EVENT_ON) { |
7b8797ac | 1348 | rc = pmac_ide_do_resume(pmif); |
1da177e4 | 1349 | if (rc == 0) |
829ca9a3 | 1350 | pdev->dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1351 | } |
1352 | ||
1353 | return rc; | |
1354 | } | |
1355 | ||
5e655772 | 1356 | static struct of_device_id pmac_ide_macio_match[] = |
1da177e4 LT |
1357 | { |
1358 | { | |
1359 | .name = "IDE", | |
1da177e4 LT |
1360 | }, |
1361 | { | |
1362 | .name = "ATA", | |
1da177e4 LT |
1363 | }, |
1364 | { | |
1da177e4 | 1365 | .type = "ide", |
1da177e4 LT |
1366 | }, |
1367 | { | |
1da177e4 | 1368 | .type = "ata", |
1da177e4 LT |
1369 | }, |
1370 | {}, | |
1371 | }; | |
1372 | ||
1373 | static struct macio_driver pmac_ide_macio_driver = | |
1374 | { | |
1375 | .name = "ide-pmac", | |
1376 | .match_table = pmac_ide_macio_match, | |
1377 | .probe = pmac_ide_macio_attach, | |
1378 | .suspend = pmac_ide_macio_suspend, | |
1379 | .resume = pmac_ide_macio_resume, | |
1380 | }; | |
1381 | ||
9cbcc5e3 BZ |
1382 | static const struct pci_device_id pmac_ide_pci_match[] = { |
1383 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, | |
1384 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, | |
1385 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, | |
1386 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, | |
1387 | { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, | |
71e4eda8 | 1388 | {}, |
1da177e4 LT |
1389 | }; |
1390 | ||
1391 | static struct pci_driver pmac_ide_pci_driver = { | |
1392 | .name = "ide-pmac", | |
1393 | .id_table = pmac_ide_pci_match, | |
1394 | .probe = pmac_ide_pci_attach, | |
1395 | .suspend = pmac_ide_pci_suspend, | |
1396 | .resume = pmac_ide_pci_resume, | |
1397 | }; | |
1398 | MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match); | |
1399 | ||
9e5755bc | 1400 | int __init pmac_ide_probe(void) |
1da177e4 | 1401 | { |
9e5755bc AM |
1402 | int error; |
1403 | ||
e8222502 | 1404 | if (!machine_is(powermac)) |
9e5755bc | 1405 | return -ENODEV; |
1da177e4 LT |
1406 | |
1407 | #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST | |
9e5755bc AM |
1408 | error = pci_register_driver(&pmac_ide_pci_driver); |
1409 | if (error) | |
1410 | goto out; | |
1411 | error = macio_register_driver(&pmac_ide_macio_driver); | |
1412 | if (error) { | |
1413 | pci_unregister_driver(&pmac_ide_pci_driver); | |
1414 | goto out; | |
1415 | } | |
1da177e4 | 1416 | #else |
9e5755bc AM |
1417 | error = macio_register_driver(&pmac_ide_macio_driver); |
1418 | if (error) | |
1419 | goto out; | |
1420 | error = pci_register_driver(&pmac_ide_pci_driver); | |
1421 | if (error) { | |
1422 | macio_unregister_driver(&pmac_ide_macio_driver); | |
1423 | goto out; | |
1424 | } | |
1beb6a7d | 1425 | #endif |
9e5755bc AM |
1426 | out: |
1427 | return error; | |
1da177e4 LT |
1428 | } |
1429 | ||
1430 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1431 | ||
1432 | /* | |
1433 | * pmac_ide_build_dmatable builds the DBDMA command list | |
1434 | * for a transfer and sets the DBDMA channel to point to it. | |
1435 | */ | |
aacaf9bd | 1436 | static int |
1da177e4 LT |
1437 | pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) |
1438 | { | |
7b8797ac BZ |
1439 | ide_hwif_t *hwif = drive->hwif; |
1440 | pmac_ide_hwif_t *pmif = | |
1441 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1442 | struct dbdma_cmd *table; |
1443 | int i, count = 0; | |
1da177e4 LT |
1444 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; |
1445 | struct scatterlist *sg; | |
1446 | int wr = (rq_data_dir(rq) == WRITE); | |
1447 | ||
1448 | /* DMA table is already aligned */ | |
1449 | table = (struct dbdma_cmd *) pmif->dma_table_cpu; | |
1450 | ||
1451 | /* Make sure DMA controller is stopped (necessary ?) */ | |
1452 | writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); | |
1453 | while (readl(&dma->status) & RUN) | |
1454 | udelay(1); | |
1455 | ||
1456 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
1457 | ||
1458 | if (!i) | |
1459 | return 0; | |
1460 | ||
1461 | /* Build DBDMA commands list */ | |
1462 | sg = hwif->sg_table; | |
1463 | while (i && sg_dma_len(sg)) { | |
1464 | u32 cur_addr; | |
1465 | u32 cur_len; | |
1466 | ||
1467 | cur_addr = sg_dma_address(sg); | |
1468 | cur_len = sg_dma_len(sg); | |
1469 | ||
1470 | if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) { | |
1471 | if (pmif->broken_dma_warn == 0) { | |
aca38a51 | 1472 | printk(KERN_WARNING "%s: DMA on non aligned address, " |
1da177e4 LT |
1473 | "switching to PIO on Ohare chipset\n", drive->name); |
1474 | pmif->broken_dma_warn = 1; | |
1475 | } | |
1476 | goto use_pio_instead; | |
1477 | } | |
1478 | while (cur_len) { | |
1479 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
1480 | ||
1481 | if (count++ >= MAX_DCMDS) { | |
1482 | printk(KERN_WARNING "%s: DMA table too small\n", | |
1483 | drive->name); | |
1484 | goto use_pio_instead; | |
1485 | } | |
1486 | st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE); | |
1487 | st_le16(&table->req_count, tc); | |
1488 | st_le32(&table->phy_addr, cur_addr); | |
1489 | table->cmd_dep = 0; | |
1490 | table->xfer_status = 0; | |
1491 | table->res_count = 0; | |
1492 | cur_addr += tc; | |
1493 | cur_len -= tc; | |
1494 | ++table; | |
1495 | } | |
55c16a70 | 1496 | sg = sg_next(sg); |
1da177e4 LT |
1497 | i--; |
1498 | } | |
1499 | ||
1500 | /* convert the last command to an input/output last command */ | |
1501 | if (count) { | |
1502 | st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST); | |
1503 | /* add the stop command to the end of the list */ | |
1504 | memset(table, 0, sizeof(struct dbdma_cmd)); | |
1505 | st_le16(&table->command, DBDMA_STOP); | |
1506 | mb(); | |
1507 | writel(hwif->dmatable_dma, &dma->cmdptr); | |
1508 | return 1; | |
1509 | } | |
1510 | ||
1511 | printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name); | |
f6fb786d BZ |
1512 | |
1513 | use_pio_instead: | |
1514 | ide_destroy_dmatable(drive); | |
1515 | ||
1da177e4 LT |
1516 | return 0; /* revert to PIO for this request */ |
1517 | } | |
1518 | ||
1519 | /* Teardown mappings after DMA has completed. */ | |
aacaf9bd | 1520 | static void |
1da177e4 LT |
1521 | pmac_ide_destroy_dmatable (ide_drive_t *drive) |
1522 | { | |
1523 | ide_hwif_t *hwif = drive->hwif; | |
1da177e4 | 1524 | |
f6fb786d BZ |
1525 | if (hwif->sg_nents) { |
1526 | ide_destroy_dmatable(drive); | |
1da177e4 LT |
1527 | hwif->sg_nents = 0; |
1528 | } | |
1529 | } | |
1530 | ||
1da177e4 LT |
1531 | /* |
1532 | * Prepare a DMA transfer. We build the DMA table, adjust the timings for | |
1533 | * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion | |
1534 | */ | |
aacaf9bd | 1535 | static int |
1da177e4 LT |
1536 | pmac_ide_dma_setup(ide_drive_t *drive) |
1537 | { | |
1538 | ide_hwif_t *hwif = HWIF(drive); | |
7b8797ac BZ |
1539 | pmac_ide_hwif_t *pmif = |
1540 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1541 | struct request *rq = HWGROUP(drive)->rq; |
1542 | u8 unit = (drive->select.b.unit & 0x01); | |
1543 | u8 ata4; | |
1544 | ||
1545 | if (pmif == NULL) | |
1546 | return 1; | |
1547 | ata4 = (pmif->kind == controller_kl_ata4); | |
1548 | ||
1549 | if (!pmac_ide_build_dmatable(drive, rq)) { | |
1550 | ide_map_sg(drive, rq); | |
1551 | return 1; | |
1552 | } | |
1553 | ||
1554 | /* Apple adds 60ns to wrDataSetup on reads */ | |
1555 | if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { | |
1556 | writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0), | |
1557 | PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1558 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1559 | } | |
1560 | ||
1561 | drive->waiting_for_dma = 1; | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
aacaf9bd | 1566 | static void |
1da177e4 LT |
1567 | pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1568 | { | |
1569 | /* issue cmd to drive */ | |
1570 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL); | |
1571 | } | |
1572 | ||
1573 | /* | |
1574 | * Kick the DMA controller into life after the DMA command has been issued | |
1575 | * to the drive. | |
1576 | */ | |
aacaf9bd | 1577 | static void |
1da177e4 LT |
1578 | pmac_ide_dma_start(ide_drive_t *drive) |
1579 | { | |
7b8797ac BZ |
1580 | ide_hwif_t *hwif = drive->hwif; |
1581 | pmac_ide_hwif_t *pmif = | |
1582 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1583 | volatile struct dbdma_regs __iomem *dma; |
1584 | ||
1585 | dma = pmif->dma_regs; | |
1586 | ||
1587 | writel((RUN << 16) | RUN, &dma->control); | |
1588 | /* Make sure it gets to the controller right now */ | |
1589 | (void)readl(&dma->control); | |
1590 | } | |
1591 | ||
1592 | /* | |
1593 | * After a DMA transfer, make sure the controller is stopped | |
1594 | */ | |
aacaf9bd | 1595 | static int |
1da177e4 LT |
1596 | pmac_ide_dma_end (ide_drive_t *drive) |
1597 | { | |
7b8797ac BZ |
1598 | ide_hwif_t *hwif = drive->hwif; |
1599 | pmac_ide_hwif_t *pmif = | |
1600 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1601 | volatile struct dbdma_regs __iomem *dma; |
1602 | u32 dstat; | |
1603 | ||
1604 | if (pmif == NULL) | |
1605 | return 0; | |
1606 | dma = pmif->dma_regs; | |
1607 | ||
1608 | drive->waiting_for_dma = 0; | |
1609 | dstat = readl(&dma->status); | |
1610 | writel(((RUN|WAKE|DEAD) << 16), &dma->control); | |
1611 | pmac_ide_destroy_dmatable(drive); | |
1612 | /* verify good dma status. we don't check for ACTIVE beeing 0. We should... | |
1613 | * in theory, but with ATAPI decices doing buffer underruns, that would | |
1614 | * cause us to disable DMA, which isn't what we want | |
1615 | */ | |
1616 | return (dstat & (RUN|DEAD)) != RUN; | |
1617 | } | |
1618 | ||
1619 | /* | |
1620 | * Check out that the interrupt we got was for us. We can't always know this | |
1621 | * for sure with those Apple interfaces (well, we could on the recent ones but | |
1622 | * that's not implemented yet), on the other hand, we don't have shared interrupts | |
1623 | * so it's not really a problem | |
1624 | */ | |
aacaf9bd | 1625 | static int |
1da177e4 LT |
1626 | pmac_ide_dma_test_irq (ide_drive_t *drive) |
1627 | { | |
7b8797ac BZ |
1628 | ide_hwif_t *hwif = drive->hwif; |
1629 | pmac_ide_hwif_t *pmif = | |
1630 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1631 | volatile struct dbdma_regs __iomem *dma; |
1632 | unsigned long status, timeout; | |
1633 | ||
1634 | if (pmif == NULL) | |
1635 | return 0; | |
1636 | dma = pmif->dma_regs; | |
1637 | ||
1638 | /* We have to things to deal with here: | |
1639 | * | |
1640 | * - The dbdma won't stop if the command was started | |
1641 | * but completed with an error without transferring all | |
1642 | * datas. This happens when bad blocks are met during | |
1643 | * a multi-block transfer. | |
1644 | * | |
1645 | * - The dbdma fifo hasn't yet finished flushing to | |
1646 | * to system memory when the disk interrupt occurs. | |
1647 | * | |
1648 | */ | |
1649 | ||
1650 | /* If ACTIVE is cleared, the STOP command have passed and | |
1651 | * transfer is complete. | |
1652 | */ | |
1653 | status = readl(&dma->status); | |
1654 | if (!(status & ACTIVE)) | |
1655 | return 1; | |
1656 | if (!drive->waiting_for_dma) | |
1657 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1658 | called while not waiting\n", HWIF(drive)->index); | |
1659 | ||
1660 | /* If dbdma didn't execute the STOP command yet, the | |
1661 | * active bit is still set. We consider that we aren't | |
1662 | * sharing interrupts (which is hopefully the case with | |
1663 | * those controllers) and so we just try to flush the | |
1664 | * channel for pending data in the fifo | |
1665 | */ | |
1666 | udelay(1); | |
1667 | writel((FLUSH << 16) | FLUSH, &dma->control); | |
1668 | timeout = 0; | |
1669 | for (;;) { | |
1670 | udelay(1); | |
1671 | status = readl(&dma->status); | |
1672 | if ((status & FLUSH) == 0) | |
1673 | break; | |
1674 | if (++timeout > 100) { | |
1675 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1676 | timeout flushing channel\n", HWIF(drive)->index); | |
1677 | break; | |
1678 | } | |
1679 | } | |
1680 | return 1; | |
1681 | } | |
1682 | ||
15ce926a | 1683 | static void pmac_ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 1684 | { |
1da177e4 LT |
1685 | } |
1686 | ||
841d2a9b SS |
1687 | static void |
1688 | pmac_ide_dma_lost_irq (ide_drive_t *drive) | |
1da177e4 | 1689 | { |
7b8797ac BZ |
1690 | ide_hwif_t *hwif = drive->hwif; |
1691 | pmac_ide_hwif_t *pmif = | |
1692 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
1da177e4 LT |
1693 | volatile struct dbdma_regs __iomem *dma; |
1694 | unsigned long status; | |
1695 | ||
1696 | if (pmif == NULL) | |
841d2a9b | 1697 | return; |
1da177e4 LT |
1698 | dma = pmif->dma_regs; |
1699 | ||
1700 | status = readl(&dma->status); | |
1701 | printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status); | |
1da177e4 LT |
1702 | } |
1703 | ||
f37afdac | 1704 | static const struct ide_dma_ops pmac_dma_ops = { |
5e37bdc0 BZ |
1705 | .dma_host_set = pmac_ide_dma_host_set, |
1706 | .dma_setup = pmac_ide_dma_setup, | |
1707 | .dma_exec_cmd = pmac_ide_dma_exec_cmd, | |
1708 | .dma_start = pmac_ide_dma_start, | |
1709 | .dma_end = pmac_ide_dma_end, | |
1710 | .dma_test_irq = pmac_ide_dma_test_irq, | |
1711 | .dma_timeout = ide_dma_timeout, | |
1712 | .dma_lost_irq = pmac_ide_dma_lost_irq, | |
1713 | }; | |
1714 | ||
1da177e4 LT |
1715 | /* |
1716 | * Allocate the data structures needed for using DMA with an interface | |
1717 | * and fill the proper list of functions pointers | |
1718 | */ | |
0d071922 BZ |
1719 | static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, |
1720 | const struct ide_port_info *d) | |
1da177e4 | 1721 | { |
7b8797ac BZ |
1722 | pmac_ide_hwif_t *pmif = |
1723 | (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); | |
36501650 BZ |
1724 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1725 | ||
1da177e4 LT |
1726 | /* We won't need pci_dev if we switch to generic consistent |
1727 | * DMA routines ... | |
1728 | */ | |
0d071922 | 1729 | if (dev == NULL || pmif->dma_regs == 0) |
c413b9b9 | 1730 | return -ENODEV; |
1da177e4 LT |
1731 | /* |
1732 | * Allocate space for the DBDMA commands. | |
1733 | * The +2 is +1 for the stop command and +1 to allow for | |
1734 | * aligning the start address to a multiple of 16 bytes. | |
1735 | */ | |
1736 | pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent( | |
36501650 | 1737 | dev, |
1da177e4 LT |
1738 | (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), |
1739 | &hwif->dmatable_dma); | |
1740 | if (pmif->dma_table_cpu == NULL) { | |
1741 | printk(KERN_ERR "%s: unable to allocate DMA command list\n", | |
1742 | hwif->name); | |
c413b9b9 | 1743 | return -ENOMEM; |
1da177e4 LT |
1744 | } |
1745 | ||
4f52a329 BZ |
1746 | hwif->sg_max_nents = MAX_DCMDS; |
1747 | ||
c413b9b9 | 1748 | return 0; |
1da177e4 | 1749 | } |
0d071922 BZ |
1750 | #else |
1751 | static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, | |
1752 | const struct ide_port_info *d) | |
1753 | { | |
1754 | return -EOPNOTSUPP; | |
1755 | } | |
1da177e4 | 1756 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ |
ade2daf9 BZ |
1757 | |
1758 | module_init(pmac_ide_probe); | |
de9facbf AB |
1759 | |
1760 | MODULE_LICENSE("GPL"); |