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ide: add PIO masks
[deliverable/linux.git] / drivers / ide / ppc / pmac.c
CommitLineData
1da177e4 1/*
f30c2269 2 * linux/drivers/ide/ppc/pmac.c
1da177e4
LT		 3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
1da177e4
LT		 25#include <linux/types.h>
26#include <linux/kernel.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
9e5755bc 51#include "../ide-timing.h"
1da177e4
LT		 52
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78#endif
79
80} pmac_ide_hwif_t;
81
aacaf9bd 82static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 83static int pmac_ide_count;
84
85enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93};
94
95static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103};
104
105/*
106 * Extra registers, both 32-bit little-endian
107 */
108#define IDE_TIMING_CONFIG 0x200
109#define IDE_INTERRUPT 0x300
110
111/* Kauai (U2) ATA has different register setup */
112#define IDE_KAUAI_PIO_CONFIG 0x200
113#define IDE_KAUAI_ULTRA_CONFIG 0x210
114#define IDE_KAUAI_POLL_CONFIG 0x220
115
116/*
117 * Timing configuration register definitions
118 */
119
120/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126/* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130#define TR_133_PIOREG_PIO_MASK 0xff000fff
131#define TR_133_PIOREG_MDMA_MASK 0x00fff800
132#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133#define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151#define TR_100_PIOREG_PIO_MASK 0xff000fff
152#define TR_100_PIOREG_MDMA_MASK 0x00fff000
153#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154#define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173#define TR_66_UDMA_MASK 0xfff00000
174#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176#define TR_66_UDMA_ADDRSETUP_SHIFT 29
177#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178#define TR_66_UDMA_RDY2PAUS_SHIFT 25
179#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180#define TR_66_UDMA_WRDATASETUP_SHIFT 21
181#define TR_66_MDMA_MASK 0x000ffc00
182#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183#define TR_66_MDMA_RECOVERY_SHIFT 15
184#define TR_66_MDMA_ACCESS_MASK 0x00007c00
185#define TR_66_MDMA_ACCESS_SHIFT 10
186#define TR_66_PIO_MASK 0x000003ff
187#define TR_66_PIO_RECOVERY_MASK 0x000003e0
188#define TR_66_PIO_RECOVERY_SHIFT 5
189#define TR_66_PIO_ACCESS_MASK 0x0000001f
190#define TR_66_PIO_ACCESS_SHIFT 0
191
192/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203#define TR_33_MDMA_MASK 0x003ff800
204#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205#define TR_33_MDMA_RECOVERY_SHIFT 16
206#define TR_33_MDMA_ACCESS_MASK 0x0000f800
207#define TR_33_MDMA_ACCESS_SHIFT 11
208#define TR_33_MDMA_HALFTICK 0x00200000
209#define TR_33_PIO_MASK 0x000007ff
210#define TR_33_PIO_E 0x00000400
211#define TR_33_PIO_RECOVERY_MASK 0x000003e0
212#define TR_33_PIO_RECOVERY_SHIFT 5
213#define TR_33_PIO_ACCESS_MASK 0x0000001f
214#define TR_33_PIO_ACCESS_SHIFT 0
215
216/*
217 * Interrupt register definitions
218 */
219#define IDE_INTR_DMA 0x80000000
220#define IDE_INTR_DEVICE 0x40000000
221
222/*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225#define KAUAI_FCR_UATA_MAGIC 0x00000004
226#define KAUAI_FCR_UATA_RESET_N 0x00000002
227#define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231/* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241};
242
aacaf9bd 243struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 244{
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254};
255
aacaf9bd 256struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 257{
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267};
268
aacaf9bd 269struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 270{
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280};
281
282/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
aacaf9bd 287} kl66_udma_timings[] =
1da177e4
LT		 288{
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294};
295
296/* UniNorth 2 ATA/100 timings */
297struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300};
301
aacaf9bd 302static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 303{
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
314 { 120 , 0x04000148 }
315};
316
aacaf9bd 317static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 318{
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329};
330
aacaf9bd 331static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 332{
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340};
341
aacaf9bd 342static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 343{
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
354 { 120 , 0x0400010a }
355};
356
aacaf9bd 357static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 358{
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
368 { 0 , 0 },
369};
370
aacaf9bd 371static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 372{
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
380 { 0 , 0 },
381};
382
383
384static inline u32
385kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
386{
387 int i;
388
389 for (i=0; table[i].cycle_time; i++)
390 if (cycle_time > table[i+1].cycle_time)
391 return table[i].timing_reg;
392 return 0;
393}
394
395/* allow up to 256 DBDMA commands per xfer */
396#define MAX_DCMDS 256
397
398/*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410#define IDE_WAKEUP_DELAY (1*HZ)
411
412static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
413static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
414static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
415static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
416static void pmac_ide_selectproc(ide_drive_t *drive);
417static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
418
419#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420
1da177e4
LT		 421/*
422 * N.B. this can't be an initfunc, because the media-bay task can
423 * call ide_[un]register at any time.
424 */
aacaf9bd 425void
1da177e4
LT		 426pmac_ide_init_hwif_ports(hw_regs_t *hw,
427 unsigned long data_port, unsigned long ctrl_port,
428 int *irq)
429{
430 int i, ix;
431
432 if (data_port == 0)
433 return;
434
435 for (ix = 0; ix < MAX_HWIFS; ++ix)
436 if (data_port == pmac_ide[ix].regbase)
437 break;
438
439 if (ix >= MAX_HWIFS) {
440 /* Probably a PCI interface... */
441 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
442 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
443 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
444 return;
445 }
446
447 for (i = 0; i < 8; ++i)
448 hw->io_ports[i] = data_port + i * 0x10;
449 hw->io_ports[8] = data_port + 0x160;
450
451 if (irq != NULL)
452 *irq = pmac_ide[ix].irq;
22192ccd
BH		 453
454 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
1da177e4
LT		 455}
456
457#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
458
459/*
460 * Apply the timings of the proper unit (master/slave) to the shared
461 * timing register when selecting that unit. This version is for
462 * ASICs with a single timing register
463 */
aacaf9bd 464static void
1da177e4
LT		 465pmac_ide_selectproc(ide_drive_t *drive)
466{
467 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
468
469 if (pmif == NULL)
470 return;
471
472 if (drive->select.b.unit & 0x01)
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
474 else
475 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
477}
478
479/*
480 * Apply the timings of the proper unit (master/slave) to the shared
481 * timing register when selecting that unit. This version is for
482 * ASICs with a dual timing register (Kauai)
483 */
aacaf9bd 484static void
1da177e4
LT		 485pmac_ide_kauai_selectproc(ide_drive_t *drive)
486{
487 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
488
489 if (pmif == NULL)
490 return;
491
492 if (drive->select.b.unit & 0x01) {
493 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
495 } else {
496 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
498 }
499 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
500}
501
502/*
503 * Force an update of controller timing values for a given drive
504 */
aacaf9bd 505static void
1da177e4
LT		 506pmac_ide_do_update_timings(ide_drive_t *drive)
507{
508 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
509
510 if (pmif == NULL)
511 return;
512
513 if (pmif->kind == controller_sh_ata6 ||
514 pmif->kind == controller_un_ata6 ||
515 pmif->kind == controller_k2_ata6)
516 pmac_ide_kauai_selectproc(drive);
517 else
518 pmac_ide_selectproc(drive);
519}
520
521static void
522pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
523{
524 u32 tmp;
525
526 writeb(value, (void __iomem *) port);
527 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
528}
529
530/*
531 * Send the SET_FEATURE IDE command to the drive and update drive->id with
532 * the new state. We currently don't use the generic routine as it used to
533 * cause various trouble, especially with older mediabays.
534 * This code is sometimes triggering a spurrious interrupt though, I need
535 * to sort that out sooner or later and see if I can finally get the
536 * common version to work properly in all cases
537 */
aacaf9bd 538static int
1da177e4
LT		 539pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
540{
541 ide_hwif_t *hwif = HWIF(drive);
542 int result = 1;
543
544 disable_irq_nosync(hwif->irq);
545 udelay(1);
546 SELECT_DRIVE(drive);
547 SELECT_MASK(drive, 0);
548 udelay(1);
549 /* Get rid of pending error state */
550 (void) hwif->INB(IDE_STATUS_REG);
551 /* Timeout bumped for some powerbooks */
552 if (wait_for_ready(drive, 2000)) {
553 /* Timeout bumped for some powerbooks */
554 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
555 "before SET_FEATURE!\n", drive->name);
556 goto out;
557 }
558 udelay(10);
559 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
560 hwif->OUTB(command, IDE_NSECTOR_REG);
561 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
562 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
563 udelay(1);
564 /* Timeout bumped for some powerbooks */
565 result = wait_for_ready(drive, 2000);
566 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
567 if (result)
568 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
569 "after SET_FEATURE !\n", drive->name);
570out:
571 SELECT_MASK(drive, 0);
572 if (result == 0) {
573 drive->id->dma_ultra &= ~0xFF00;
574 drive->id->dma_mword &= ~0x0F00;
575 drive->id->dma_1word &= ~0x0F00;
576 switch(command) {
577 case XFER_UDMA_7:
578 drive->id->dma_ultra |= 0x8080; break;
579 case XFER_UDMA_6:
580 drive->id->dma_ultra |= 0x4040; break;
581 case XFER_UDMA_5:
582 drive->id->dma_ultra |= 0x2020; break;
583 case XFER_UDMA_4:
584 drive->id->dma_ultra |= 0x1010; break;
585 case XFER_UDMA_3:
586 drive->id->dma_ultra |= 0x0808; break;
587 case XFER_UDMA_2:
588 drive->id->dma_ultra |= 0x0404; break;
589 case XFER_UDMA_1:
590 drive->id->dma_ultra |= 0x0202; break;
591 case XFER_UDMA_0:
592 drive->id->dma_ultra |= 0x0101; break;
593 case XFER_MW_DMA_2:
594 drive->id->dma_mword |= 0x0404; break;
595 case XFER_MW_DMA_1:
596 drive->id->dma_mword |= 0x0202; break;
597 case XFER_MW_DMA_0:
598 drive->id->dma_mword |= 0x0101; break;
599 case XFER_SW_DMA_2:
600 drive->id->dma_1word |= 0x0404; break;
601 case XFER_SW_DMA_1:
602 drive->id->dma_1word |= 0x0202; break;
603 case XFER_SW_DMA_0:
604 drive->id->dma_1word |= 0x0101; break;
605 default: break;
606 }
607 }
608 enable_irq(hwif->irq);
609 return result;
610}
611
612/*
613 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
614 */
aacaf9bd 615static void
1da177e4
LT		 616pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
617{
1da177e4
LT		 618 u32 *timings;
619 unsigned accessTicks, recTicks;
620 unsigned accessTime, recTime;
621 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
7dd00083
BZ		 622 unsigned int cycle_time;
623
1da177e4
LT		 624 if (pmif == NULL)
625 return;
626
627 /* which drive is it ? */
628 timings = &pmif->timings[drive->select.b.unit & 0x01];
629
2134758d 630 pio = ide_get_best_pio_mode(drive, pio, 4);
7dd00083 631 cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4
LT		 632
633 switch (pmif->kind) {
634 case controller_sh_ata6: {
635 /* 133Mhz cell */
7dd00083 636 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
1da177e4
LT		 637 if (tr == 0)
638 return;
639 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
640 break;
641 }
642 case controller_un_ata6:
643 case controller_k2_ata6: {
644 /* 100Mhz cell */
7dd00083 645 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
1da177e4
LT		 646 if (tr == 0)
647 return;
648 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
649 break;
650 }
651 case controller_kl_ata4:
652 /* 66Mhz cell */
7dd00083 653 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 654 - ide_pio_timings[pio].setup_time;
655 recTime = max(recTime, 150U);
656 accessTime = ide_pio_timings[pio].active_time;
657 accessTime = max(accessTime, 150U);
658 accessTicks = SYSCLK_TICKS_66(accessTime);
659 accessTicks = min(accessTicks, 0x1fU);
660 recTicks = SYSCLK_TICKS_66(recTime);
661 recTicks = min(recTicks, 0x1fU);
662 *timings = ((*timings) & ~TR_66_PIO_MASK) |
663 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
664 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
665 break;
666 default: {
667 /* 33Mhz cell */
668 int ebit = 0;
7dd00083 669 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 670 - ide_pio_timings[pio].setup_time;
671 recTime = max(recTime, 150U);
672 accessTime = ide_pio_timings[pio].active_time;
673 accessTime = max(accessTime, 150U);
674 accessTicks = SYSCLK_TICKS(accessTime);
675 accessTicks = min(accessTicks, 0x1fU);
676 accessTicks = max(accessTicks, 4U);
677 recTicks = SYSCLK_TICKS(recTime);
678 recTicks = min(recTicks, 0x1fU);
679 recTicks = max(recTicks, 5U) - 4;
680 if (recTicks > 9) {
681 recTicks--; /* guess, but it's only for PIO0, so... */
682 ebit = 1;
683 }
684 *timings = ((*timings) & ~TR_33_PIO_MASK) |
685 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
686 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
687 if (ebit)
688 *timings |= TR_33_PIO_E;
689 break;
690 }
691 }
692
693#ifdef IDE_PMAC_DEBUG
694 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
695 drive->name, pio, *timings);
696#endif
697
698 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
699 pmac_ide_do_update_timings(drive);
700}
701
702#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
703
704/*
705 * Calculate KeyLargo ATA/66 UDMA timings
706 */
aacaf9bd 707static int
1da177e4
LT		 708set_timings_udma_ata4(u32 *timings, u8 speed)
709{
710 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
711
712 if (speed > XFER_UDMA_4)
713 return 1;
714
715 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
716 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
717 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
718
719 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
720 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
721 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
722 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
723 TR_66_UDMA_EN;
724#ifdef IDE_PMAC_DEBUG
725 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
726 speed & 0xf, *timings);
727#endif
728
729 return 0;
730}
731
732/*
733 * Calculate Kauai ATA/100 UDMA timings
734 */
aacaf9bd 735static int
1da177e4
LT		 736set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
737{
738 struct ide_timing *t = ide_timing_find_mode(speed);
739 u32 tr;
740
741 if (speed > XFER_UDMA_5 || t == NULL)
742 return 1;
743 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
744 if (tr == 0)
745 return 1;
746 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
747 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
748
749 return 0;
750}
751
752/*
753 * Calculate Shasta ATA/133 UDMA timings
754 */
aacaf9bd 755static int
1da177e4
LT		 756set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
757{
758 struct ide_timing *t = ide_timing_find_mode(speed);
759 u32 tr;
760
761 if (speed > XFER_UDMA_6 || t == NULL)
762 return 1;
763 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
764 if (tr == 0)
765 return 1;
766 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
767 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
768
769 return 0;
770}
771
772/*
773 * Calculate MDMA timings for all cells
774 */
aacaf9bd 775static int
1da177e4
LT		 776set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
777 u8 speed, int drive_cycle_time)
778{
779 int cycleTime, accessTime = 0, recTime = 0;
780 unsigned accessTicks, recTicks;
781 struct mdma_timings_t* tm = NULL;
782 int i;
783
784 /* Get default cycle time for mode */
785 switch(speed & 0xf) {
786 case 0: cycleTime = 480; break;
787 case 1: cycleTime = 150; break;
788 case 2: cycleTime = 120; break;
789 default:
790 return 1;
791 }
792 /* Adjust for drive */
793 if (drive_cycle_time && drive_cycle_time > cycleTime)
794 cycleTime = drive_cycle_time;
795 /* OHare limits according to some old Apple sources */
796 if ((intf_type == controller_ohare) && (cycleTime < 150))
797 cycleTime = 150;
798 /* Get the proper timing array for this controller */
799 switch(intf_type) {
800 case controller_sh_ata6:
801 case controller_un_ata6:
802 case controller_k2_ata6:
803 break;
804 case controller_kl_ata4:
805 tm = mdma_timings_66;
806 break;
807 case controller_kl_ata3:
808 tm = mdma_timings_33k;
809 break;
810 default:
811 tm = mdma_timings_33;
812 break;
813 }
814 if (tm != NULL) {
815 /* Lookup matching access & recovery times */
816 i = -1;
817 for (;;) {
818 if (tm[i+1].cycleTime < cycleTime)
819 break;
820 i++;
821 }
822 if (i < 0)
823 return 1;
824 cycleTime = tm[i].cycleTime;
825 accessTime = tm[i].accessTime;
826 recTime = tm[i].recoveryTime;
827
828#ifdef IDE_PMAC_DEBUG
829 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
830 drive->name, cycleTime, accessTime, recTime);
831#endif
832 }
833 switch(intf_type) {
834 case controller_sh_ata6: {
835 /* 133Mhz cell */
836 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
837 if (tr == 0)
838 return 1;
839 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
840 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
841 }
842 case controller_un_ata6:
843 case controller_k2_ata6: {
844 /* 100Mhz cell */
845 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
846 if (tr == 0)
847 return 1;
848 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
849 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
850 }
851 break;
852 case controller_kl_ata4:
853 /* 66Mhz cell */
854 accessTicks = SYSCLK_TICKS_66(accessTime);
855 accessTicks = min(accessTicks, 0x1fU);
856 accessTicks = max(accessTicks, 0x1U);
857 recTicks = SYSCLK_TICKS_66(recTime);
858 recTicks = min(recTicks, 0x1fU);
859 recTicks = max(recTicks, 0x3U);
860 /* Clear out mdma bits and disable udma */
861 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
862 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
863 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
864 break;
865 case controller_kl_ata3:
866 /* 33Mhz cell on KeyLargo */
867 accessTicks = SYSCLK_TICKS(accessTime);
868 accessTicks = max(accessTicks, 1U);
869 accessTicks = min(accessTicks, 0x1fU);
870 accessTime = accessTicks * IDE_SYSCLK_NS;
871 recTicks = SYSCLK_TICKS(recTime);
872 recTicks = max(recTicks, 1U);
873 recTicks = min(recTicks, 0x1fU);
874 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
875 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
876 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
877 break;
878 default: {
879 /* 33Mhz cell on others */
880 int halfTick = 0;
881 int origAccessTime = accessTime;
882 int origRecTime = recTime;
883
884 accessTicks = SYSCLK_TICKS(accessTime);
885 accessTicks = max(accessTicks, 1U);
886 accessTicks = min(accessTicks, 0x1fU);
887 accessTime = accessTicks * IDE_SYSCLK_NS;
888 recTicks = SYSCLK_TICKS(recTime);
889 recTicks = max(recTicks, 2U) - 1;
890 recTicks = min(recTicks, 0x1fU);
891 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
892 if ((accessTicks > 1) &&
893 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
894 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
895 halfTick = 1;
896 accessTicks--;
897 }
898 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
899 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
900 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
901 if (halfTick)
902 *timings |= TR_33_MDMA_HALFTICK;
903 }
904 }
905#ifdef IDE_PMAC_DEBUG
906 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
907 drive->name, speed & 0xf, *timings);
908#endif
909 return 0;
910}
911#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
912
913/*
914 * Speedproc. This function is called by the core to set any of the standard
915 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
916 * You may notice we don't use this function on normal "dma check" operation,
917 * our dedicated function is more precise as it uses the drive provided
918 * cycle time value. We should probably fix this one to deal with that too...
919 */
aacaf9bd 920static int
1da177e4
LT		 921pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
922{
923 int unit = (drive->select.b.unit & 0x01);
924 int ret = 0;
925 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
926 u32 *timings, *timings2;
927
928 if (pmif == NULL)
929 return 1;
930
931 timings = &pmif->timings[unit];
932 timings2 = &pmif->timings[unit+2];
933
934 switch(speed) {
935#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
936 case XFER_UDMA_6:
937 if (pmif->kind != controller_sh_ata6)
938 return 1;
939 case XFER_UDMA_5:
940 if (pmif->kind != controller_un_ata6 &&
941 pmif->kind != controller_k2_ata6 &&
942 pmif->kind != controller_sh_ata6)
943 return 1;
944 case XFER_UDMA_4:
945 case XFER_UDMA_3:
49521f97
BZ		 946 if (drive->hwif->cbl != ATA_CBL_PATA80)
947 return 1;
1da177e4
LT		 948 case XFER_UDMA_2:
949 case XFER_UDMA_1:
950 case XFER_UDMA_0:
951 if (pmif->kind == controller_kl_ata4)
952 ret = set_timings_udma_ata4(timings, speed);
953 else if (pmif->kind == controller_un_ata6
954 || pmif->kind == controller_k2_ata6)
955 ret = set_timings_udma_ata6(timings, timings2, speed);
956 else if (pmif->kind == controller_sh_ata6)
957 ret = set_timings_udma_shasta(timings, timings2, speed);
958 else
959 ret = 1;
960 break;
961 case XFER_MW_DMA_2:
962 case XFER_MW_DMA_1:
963 case XFER_MW_DMA_0:
964 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
965 break;
966 case XFER_SW_DMA_2:
967 case XFER_SW_DMA_1:
968 case XFER_SW_DMA_0:
969 return 1;
970#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
971 case XFER_PIO_4:
972 case XFER_PIO_3:
973 case XFER_PIO_2:
974 case XFER_PIO_1:
975 case XFER_PIO_0:
976 pmac_ide_tuneproc(drive, speed & 0x07);
977 break;
978 default:
979 ret = 1;
980 }
981 if (ret)
982 return ret;
983
984 ret = pmac_ide_do_setfeature(drive, speed);
985 if (ret)
986 return ret;
987
988 pmac_ide_do_update_timings(drive);
989 drive->current_speed = speed;
990
991 return 0;
992}
993
994/*
995 * Blast some well known "safe" values to the timing registers at init or
996 * wakeup from sleep time, before we do real calculation
997 */
aacaf9bd 998static void
1da177e4
LT		 999sanitize_timings(pmac_ide_hwif_t *pmif)
1000{
1001 unsigned int value, value2 = 0;
1002
1003 switch(pmif->kind) {
1004 case controller_sh_ata6:
1005 value = 0x0a820c97;
1006 value2 = 0x00033031;
1007 break;
1008 case controller_un_ata6:
1009 case controller_k2_ata6:
1010 value = 0x08618a92;
1011 value2 = 0x00002921;
1012 break;
1013 case controller_kl_ata4:
1014 value = 0x0008438c;
1015 break;
1016 case controller_kl_ata3:
1017 value = 0x00084526;
1018 break;
1019 case controller_heathrow:
1020 case controller_ohare:
1021 default:
1022 value = 0x00074526;
1023 break;
1024 }
1025 pmif->timings[0] = pmif->timings[1] = value;
1026 pmif->timings[2] = pmif->timings[3] = value2;
1027}
1028
aacaf9bd 1029unsigned long
1da177e4
LT		 1030pmac_ide_get_base(int index)
1031{
1032 return pmac_ide[index].regbase;
1033}
1034
aacaf9bd 1035int
1da177e4
LT		 1036pmac_ide_check_base(unsigned long base)
1037{
1038 int ix;
1039
1040 for (ix = 0; ix < MAX_HWIFS; ++ix)
1041 if (base == pmac_ide[ix].regbase)
1042 return ix;
1043 return -1;
1044}
1045
aacaf9bd 1046int
1da177e4
LT		 1047pmac_ide_get_irq(unsigned long base)
1048{
1049 int ix;
1050
1051 for (ix = 0; ix < MAX_HWIFS; ++ix)
1052 if (base == pmac_ide[ix].regbase)
1053 return pmac_ide[ix].irq;
1054 return 0;
1055}
1056
aacaf9bd 1057static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1da177e4
LT		 1058
1059dev_t __init
1060pmac_find_ide_boot(char *bootdevice, int n)
1061{
1062 int i;
1063
1064 /*
1065 * Look through the list of IDE interfaces for this one.
1066 */
1067 for (i = 0; i < pmac_ide_count; ++i) {
1068 char *name;
1069 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1070 continue;
1071 name = pmac_ide[i].node->full_name;
1072 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1073 /* XXX should cope with the 2nd drive as well... */
1074 return MKDEV(ide_majors[i], 0);
1075 }
1076 }
1077
1078 return 0;
1079}
1080
1081/* Suspend call back, should be called after the child devices
1082 * have actually been suspended
1083 */
1084static int
1085pmac_ide_do_suspend(ide_hwif_t *hwif)
1086{
1087 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1088
1089 /* We clear the timings */
1090 pmif->timings[0] = 0;
1091 pmif->timings[1] = 0;
1092
616299af
BH		 1093 disable_irq(pmif->irq);
1094
1da177e4
LT		 1095 /* The media bay will handle itself just fine */
1096 if (pmif->mediabay)
1097 return 0;
1098
1099 /* Kauai has bus control FCRs directly here */
1100 if (pmif->kauai_fcr) {
1101 u32 fcr = readl(pmif->kauai_fcr);
1102 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1103 writel(fcr, pmif->kauai_fcr);
1104 }
1105
1106 /* Disable the bus on older machines and the cell on kauai */
1107 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1108 0);
1109
1110 return 0;
1111}
1112
1113/* Resume call back, should be called before the child devices
1114 * are resumed
1115 */
1116static int
1117pmac_ide_do_resume(ide_hwif_t *hwif)
1118{
1119 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1120
1121 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1122 if (!pmif->mediabay) {
1123 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1124 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1125 msleep(10);
1126 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 1127
1128 /* Kauai has it different */
1129 if (pmif->kauai_fcr) {
1130 u32 fcr = readl(pmif->kauai_fcr);
1131 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1132 writel(fcr, pmif->kauai_fcr);
1133 }
616299af
BH		 1134
1135 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 1136 }
1137
1138 /* Sanitize drive timings */
1139 sanitize_timings(pmif);
1140
616299af
BH		 1141 enable_irq(pmif->irq);
1142
1da177e4
LT		 1143 return 0;
1144}
1145
1146/*
1147 * Setup, register & probe an IDE channel driven by this driver, this is
1148 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1149 * that ends up beeing free of any device is not kept around by this driver
1150 * (it is kept in 2.4). This introduce an interface numbering change on some
1151 * rare machines unfortunately, but it's better this way.
1152 */
1153static int
1154pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1155{
1156 struct device_node *np = pmif->node;
018a3d1d 1157 const int *bidp;
1da177e4
LT		 1158
1159 pmif->cable_80 = 0;
1160 pmif->broken_dma = pmif->broken_dma_warn = 0;
55b61fec 1161 if (of_device_is_compatible(np, "shasta-ata"))
1da177e4 1162 pmif->kind = controller_sh_ata6;
55b61fec 1163 else if (of_device_is_compatible(np, "kauai-ata"))
1da177e4 1164 pmif->kind = controller_un_ata6;
55b61fec 1165 else if (of_device_is_compatible(np, "K2-UATA"))
1da177e4 1166 pmif->kind = controller_k2_ata6;
55b61fec 1167 else if (of_device_is_compatible(np, "keylargo-ata")) {
1da177e4
LT		 1168 if (strcmp(np->name, "ata-4") == 0)
1169 pmif->kind = controller_kl_ata4;
1170 else
1171 pmif->kind = controller_kl_ata3;
55b61fec 1172 } else if (of_device_is_compatible(np, "heathrow-ata"))
1da177e4
LT		 1173 pmif->kind = controller_heathrow;
1174 else {
1175 pmif->kind = controller_ohare;
1176 pmif->broken_dma = 1;
1177 }
1178
40cd3a45 1179 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1da177e4
LT		 1180 pmif->aapl_bus_id = bidp ? *bidp : 0;
1181
1182 /* Get cable type from device-tree */
1183 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1184 || pmif->kind == controller_k2_ata6
1185 || pmif->kind == controller_sh_ata6) {
40cd3a45 1186 const char* cable = of_get_property(np, "cable-type", NULL);
1da177e4
LT		 1187 if (cable && !strncmp(cable, "80-", 3))
1188 pmif->cable_80 = 1;
1189 }
1190 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1191 * they have a 80 conductor cable, this seem to be always the case unless
1192 * the user mucked around
1193 */
55b61fec
SR		 1194 if (of_device_is_compatible(np, "K2-UATA") ||
1195 of_device_is_compatible(np, "shasta-ata"))
1da177e4
LT		 1196 pmif->cable_80 = 1;
1197
1198 /* On Kauai-type controllers, we make sure the FCR is correct */
1199 if (pmif->kauai_fcr)
1200 writel(KAUAI_FCR_UATA_MAGIC |
1201 KAUAI_FCR_UATA_RESET_N |
1202 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1203
1204 pmif->mediabay = 0;
1205
1206 /* Make sure we have sane timings */
1207 sanitize_timings(pmif);
1208
1209#ifndef CONFIG_PPC64
1210 /* XXX FIXME: Media bay stuff need re-organizing */
1211 if (np->parent && np->parent->name
1212 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1213#ifdef CONFIG_PMAC_MEDIABAY
1da177e4 1214 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
8c870933 1215#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1216 pmif->mediabay = 1;
1217 if (!bidp)
1218 pmif->aapl_bus_id = 1;
1219 } else if (pmif->kind == controller_ohare) {
1220 /* The code below is having trouble on some ohare machines
1221 * (timing related ?). Until I can put my hand on one of these
1222 * units, I keep the old way
1223 */
1224 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1225 } else
1226#endif
1227 {
1228 /* This is necessary to enable IDE when net-booting */
1229 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1230 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1231 msleep(10);
1232 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1233 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1234 }
1235
1236 /* Setup MMIO ops */
1237 default_hwif_mmiops(hwif);
1238 hwif->OUTBSYNC = pmac_outbsync;
1239
1240 /* Tell common code _not_ to mess with resources */
2ad1e558 1241 hwif->mmio = 1;
1da177e4
LT		 1242 hwif->hwif_data = pmif;
1243 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1244 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1245 hwif->chipset = ide_pmac;
1246 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1247 hwif->hold = pmif->mediabay;
49521f97 1248 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 1249 hwif->drives[0].unmask = 1;
1250 hwif->drives[1].unmask = 1;
4099d143 1251 hwif->pio_mask = ATA_PIO4;
1da177e4
LT		 1252 hwif->tuneproc = pmac_ide_tuneproc;
1253 if (pmif->kind == controller_un_ata6
1254 || pmif->kind == controller_k2_ata6
1255 || pmif->kind == controller_sh_ata6)
1256 hwif->selectproc = pmac_ide_kauai_selectproc;
1257 else
1258 hwif->selectproc = pmac_ide_selectproc;
1259 hwif->speedproc = pmac_ide_tune_chipset;
1260
1da177e4
LT		 1261 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1262 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1263 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1264
8c870933 1265#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1266 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1267 hwif->noprobe = 0;
8c870933 1268#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1269
1270 hwif->sg_max_nents = MAX_DCMDS;
1271
1272#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1273 /* has a DBDMA controller channel */
1274 if (pmif->dma_regs)
1275 pmac_ide_setup_dma(pmif, hwif);
1276#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1277
1278 /* We probe the hwif now */
1279 probe_hwif_init(hwif);
1280
5cbf79cd
BZ		 1281 ide_proc_register_port(hwif);
1282
1da177e4
LT		 1283 return 0;
1284}
1285
1286/*
1287 * Attach to a macio probed interface
1288 */
1289static int __devinit
5e655772 1290pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1291{
1292 void __iomem *base;
1293 unsigned long regbase;
1294 int irq;
1295 ide_hwif_t *hwif;
1296 pmac_ide_hwif_t *pmif;
1297 int i, rc;
1298
1299 i = 0;
1300 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1301 || pmac_ide[i].node != NULL))
1302 ++i;
1303 if (i >= MAX_HWIFS) {
1304 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1305 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1306 return -ENODEV;
1307 }
1308
1309 pmif = &pmac_ide[i];
1310 hwif = &ide_hwifs[i];
1311
cc5d0189 1312 if (macio_resource_count(mdev) == 0) {
1da177e4
LT		 1313 printk(KERN_WARNING "ide%d: no address for %s\n",
1314 i, mdev->ofdev.node->full_name);
1315 return -ENXIO;
1316 }
1317
1318 /* Request memory resource for IO ports */
1319 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1320 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1321 return -EBUSY;
1322 }
1323
1324 /* XXX This is bogus. Should be fixed in the registry by checking
1325 * the kind of host interrupt controller, a bit like gatwick
1326 * fixes in irq.c. That works well enough for the single case
1327 * where that happens though...
1328 */
1329 if (macio_irq_count(mdev) == 0) {
1330 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1331 i, mdev->ofdev.node->full_name);
69917c26 1332 irq = irq_create_mapping(NULL, 13);
1da177e4
LT		 1333 } else
1334 irq = macio_irq(mdev, 0);
1335
1336 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1337 regbase = (unsigned long) base;
1338
1339 hwif->pci_dev = mdev->bus->pdev;
1340 hwif->gendev.parent = &mdev->ofdev.dev;
1341
1342 pmif->mdev = mdev;
1343 pmif->node = mdev->ofdev.node;
1344 pmif->regbase = regbase;
1345 pmif->irq = irq;
1346 pmif->kauai_fcr = NULL;
1347#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1348 if (macio_resource_count(mdev) >= 2) {
1349 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1350 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1351 else
1352 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1353 } else
1354 pmif->dma_regs = NULL;
1355#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1356 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1357
1358 rc = pmac_ide_setup_device(pmif, hwif);
1359 if (rc != 0) {
1360 /* The inteface is released to the common IDE layer */
1361 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1362 iounmap(base);
1363 if (pmif->dma_regs)
1364 iounmap(pmif->dma_regs);
1365 memset(pmif, 0, sizeof(*pmif));
1366 macio_release_resource(mdev, 0);
1367 if (pmif->dma_regs)
1368 macio_release_resource(mdev, 1);
1369 }
1370
1371 return rc;
1372}
1373
1374static int
8b4b8a24 1375pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1da177e4
LT		 1376{
1377 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1378 int rc = 0;
1379
8b4b8a24
DB		 1380 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1381 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1382 rc = pmac_ide_do_suspend(hwif);
1383 if (rc == 0)
8b4b8a24 1384 mdev->ofdev.dev.power.power_state = mesg;
1da177e4
LT		 1385 }
1386
1387 return rc;
1388}
1389
1390static int
1391pmac_ide_macio_resume(struct macio_dev *mdev)
1392{
1393 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1394 int rc = 0;
1395
ca078bae 1396 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1397 rc = pmac_ide_do_resume(hwif);
1398 if (rc == 0)
829ca9a3 1399 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1400 }
1401
1402 return rc;
1403}
1404
1405/*
1406 * Attach to a PCI probed interface
1407 */
1408static int __devinit
1409pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1410{
1411 ide_hwif_t *hwif;
1412 struct device_node *np;
1413 pmac_ide_hwif_t *pmif;
1414 void __iomem *base;
1415 unsigned long rbase, rlen;
1416 int i, rc;
1417
1418 np = pci_device_to_OF_node(pdev);
1419 if (np == NULL) {
1420 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1421 return -ENODEV;
1422 }
1423 i = 0;
1424 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1425 || pmac_ide[i].node != NULL))
1426 ++i;
1427 if (i >= MAX_HWIFS) {
1428 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1429 printk(KERN_ERR " %s\n", np->full_name);
1430 return -ENODEV;
1431 }
1432
1433 pmif = &pmac_ide[i];
1434 hwif = &ide_hwifs[i];
1435
1436 if (pci_enable_device(pdev)) {
1437 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1438 i, np->full_name);
1439 return -ENXIO;
1440 }
1441 pci_set_master(pdev);
1442
1443 if (pci_request_regions(pdev, "Kauai ATA")) {
1444 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1445 i, np->full_name);
1446 return -ENXIO;
1447 }
1448
1449 hwif->pci_dev = pdev;
1450 hwif->gendev.parent = &pdev->dev;
1451 pmif->mdev = NULL;
1452 pmif->node = np;
1453
1454 rbase = pci_resource_start(pdev, 0);
1455 rlen = pci_resource_len(pdev, 0);
1456
1457 base = ioremap(rbase, rlen);
1458 pmif->regbase = (unsigned long) base + 0x2000;
1459#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1460 pmif->dma_regs = base + 0x1000;
1461#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1462 pmif->kauai_fcr = base;
1463 pmif->irq = pdev->irq;
1464
1465 pci_set_drvdata(pdev, hwif);
1466
1467 rc = pmac_ide_setup_device(pmif, hwif);
1468 if (rc != 0) {
1469 /* The inteface is released to the common IDE layer */
1470 pci_set_drvdata(pdev, NULL);
1471 iounmap(base);
1472 memset(pmif, 0, sizeof(*pmif));
1473 pci_release_regions(pdev);
1474 }
1475
1476 return rc;
1477}
1478
1479static int
8b4b8a24 1480pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1da177e4
LT		 1481{
1482 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1483 int rc = 0;
1484
8b4b8a24
DB		 1485 if (mesg.event != pdev->dev.power.power_state.event
1486 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1487 rc = pmac_ide_do_suspend(hwif);
1488 if (rc == 0)
8b4b8a24 1489 pdev->dev.power.power_state = mesg;
1da177e4
LT		 1490 }
1491
1492 return rc;
1493}
1494
1495static int
1496pmac_ide_pci_resume(struct pci_dev *pdev)
1497{
1498 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1499 int rc = 0;
1500
ca078bae 1501 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1502 rc = pmac_ide_do_resume(hwif);
1503 if (rc == 0)
829ca9a3 1504 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1505 }
1506
1507 return rc;
1508}
1509
5e655772 1510static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1511{
1512 {
1513 .name = "IDE",
1da177e4
LT		 1514 },
1515 {
1516 .name = "ATA",
1da177e4
LT		 1517 },
1518 {
1da177e4 1519 .type = "ide",
1da177e4
LT		 1520 },
1521 {
1da177e4 1522 .type = "ata",
1da177e4
LT		 1523 },
1524 {},
1525};
1526
1527static struct macio_driver pmac_ide_macio_driver =
1528{
1529 .name = "ide-pmac",
1530 .match_table = pmac_ide_macio_match,
1531 .probe = pmac_ide_macio_attach,
1532 .suspend = pmac_ide_macio_suspend,
1533 .resume = pmac_ide_macio_resume,
1534};
1535
1536static struct pci_device_id pmac_ide_pci_match[] = {
7fce260a
OJ		 1537 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1543 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
7fce260a
OJ		 1545 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1547};
1548
1549static struct pci_driver pmac_ide_pci_driver = {
1550 .name = "ide-pmac",
1551 .id_table = pmac_ide_pci_match,
1552 .probe = pmac_ide_pci_attach,
1553 .suspend = pmac_ide_pci_suspend,
1554 .resume = pmac_ide_pci_resume,
1555};
1556MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1557
9e5755bc 1558int __init pmac_ide_probe(void)
1da177e4 1559{
9e5755bc
AM		 1560 int error;
1561
e8222502 1562 if (!machine_is(powermac))
9e5755bc 1563 return -ENODEV;
1da177e4
LT		 1564
1565#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
9e5755bc
AM		 1566 error = pci_register_driver(&pmac_ide_pci_driver);
1567 if (error)
1568 goto out;
1569 error = macio_register_driver(&pmac_ide_macio_driver);
1570 if (error) {
1571 pci_unregister_driver(&pmac_ide_pci_driver);
1572 goto out;
1573 }
1da177e4 1574#else
9e5755bc
AM		 1575 error = macio_register_driver(&pmac_ide_macio_driver);
1576 if (error)
1577 goto out;
1578 error = pci_register_driver(&pmac_ide_pci_driver);
1579 if (error) {
1580 macio_unregister_driver(&pmac_ide_macio_driver);
1581 goto out;
1582 }
1beb6a7d 1583#endif
9e5755bc
AM		 1584out:
1585 return error;
1da177e4
LT		 1586}
1587
1588#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1589
1590/*
1591 * pmac_ide_build_dmatable builds the DBDMA command list
1592 * for a transfer and sets the DBDMA channel to point to it.
1593 */
aacaf9bd 1594static int
1da177e4
LT		 1595pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1596{
1597 struct dbdma_cmd *table;
1598 int i, count = 0;
1599 ide_hwif_t *hwif = HWIF(drive);
1600 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1601 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1602 struct scatterlist *sg;
1603 int wr = (rq_data_dir(rq) == WRITE);
1604
1605 /* DMA table is already aligned */
1606 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1607
1608 /* Make sure DMA controller is stopped (necessary ?) */
1609 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1610 while (readl(&dma->status) & RUN)
1611 udelay(1);
1612
1613 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1614
1615 if (!i)
1616 return 0;
1617
1618 /* Build DBDMA commands list */
1619 sg = hwif->sg_table;
1620 while (i && sg_dma_len(sg)) {
1621 u32 cur_addr;
1622 u32 cur_len;
1623
1624 cur_addr = sg_dma_address(sg);
1625 cur_len = sg_dma_len(sg);
1626
1627 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1628 if (pmif->broken_dma_warn == 0) {
1629 printk(KERN_WARNING "%s: DMA on non aligned address,"
1630 "switching to PIO on Ohare chipset\n", drive->name);
1631 pmif->broken_dma_warn = 1;
1632 }
1633 goto use_pio_instead;
1634 }
1635 while (cur_len) {
1636 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1637
1638 if (count++ >= MAX_DCMDS) {
1639 printk(KERN_WARNING "%s: DMA table too small\n",
1640 drive->name);
1641 goto use_pio_instead;
1642 }
1643 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1644 st_le16(&table->req_count, tc);
1645 st_le32(&table->phy_addr, cur_addr);
1646 table->cmd_dep = 0;
1647 table->xfer_status = 0;
1648 table->res_count = 0;
1649 cur_addr += tc;
1650 cur_len -= tc;
1651 ++table;
1652 }
1653 sg++;
1654 i--;
1655 }
1656
1657 /* convert the last command to an input/output last command */
1658 if (count) {
1659 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1660 /* add the stop command to the end of the list */
1661 memset(table, 0, sizeof(struct dbdma_cmd));
1662 st_le16(&table->command, DBDMA_STOP);
1663 mb();
1664 writel(hwif->dmatable_dma, &dma->cmdptr);
1665 return 1;
1666 }
1667
1668 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1669 use_pio_instead:
1670 pci_unmap_sg(hwif->pci_dev,
1671 hwif->sg_table,
1672 hwif->sg_nents,
1673 hwif->sg_dma_direction);
1674 return 0; /* revert to PIO for this request */
1675}
1676
1677/* Teardown mappings after DMA has completed. */
aacaf9bd 1678static void
1da177e4
LT		 1679pmac_ide_destroy_dmatable (ide_drive_t *drive)
1680{
1681 ide_hwif_t *hwif = drive->hwif;
1682 struct pci_dev *dev = HWIF(drive)->pci_dev;
1683 struct scatterlist *sg = hwif->sg_table;
1684 int nents = hwif->sg_nents;
1685
1686 if (nents) {
1687 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1688 hwif->sg_nents = 0;
1689 }
1690}
1691
1692/*
1693 * Pick up best MDMA timing for the drive and apply it
1694 */
aacaf9bd 1695static int
1da177e4
LT		 1696pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1697{
1698 ide_hwif_t *hwif = HWIF(drive);
1699 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1700 int drive_cycle_time;
1701 struct hd_driveid *id = drive->id;
1702 u32 *timings, *timings2;
1703 u32 timing_local[2];
1704 int ret;
1705
1706 /* which drive is it ? */
1707 timings = &pmif->timings[drive->select.b.unit & 0x01];
1708 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1709
1710 /* Check if drive provide explicit cycle time */
1711 if ((id->field_valid & 2) && (id->eide_dma_time))
1712 drive_cycle_time = id->eide_dma_time;
1713 else
1714 drive_cycle_time = 0;
1715
1716 /* Copy timings to local image */
1717 timing_local[0] = *timings;
1718 timing_local[1] = *timings2;
1719
1720 /* Calculate controller timings */
1721 ret = set_timings_mdma( drive, pmif->kind,
1722 &timing_local[0],
1723 &timing_local[1],
1724 mode,
1725 drive_cycle_time);
1726 if (ret)
1727 return 0;
1728
1729 /* Set feature on drive */
1730 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1731 ret = pmac_ide_do_setfeature(drive, mode);
1732 if (ret) {
1733 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1734 return 0;
1735 }
1736
1737 /* Apply timings to controller */
1738 *timings = timing_local[0];
1739 *timings2 = timing_local[1];
1740
1741 /* Set speed info in drive */
1742 drive->current_speed = mode;
1743 if (!drive->init_speed)
1744 drive->init_speed = mode;
1745
1746 return 1;
1747}
1748
1749/*
1750 * Pick up best UDMA timing for the drive and apply it
1751 */
aacaf9bd 1752static int
1da177e4
LT		 1753pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1754{
1755 ide_hwif_t *hwif = HWIF(drive);
1756 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1757 u32 *timings, *timings2;
1758 u32 timing_local[2];
1759 int ret;
1760
1761 /* which drive is it ? */
1762 timings = &pmif->timings[drive->select.b.unit & 0x01];
1763 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1764
1765 /* Copy timings to local image */
1766 timing_local[0] = *timings;
1767 timing_local[1] = *timings2;
1768
1769 /* Calculate timings for interface */
1770 if (pmif->kind == controller_un_ata6
1771 || pmif->kind == controller_k2_ata6)
1772 ret = set_timings_udma_ata6( &timing_local[0],
1773 &timing_local[1],
1774 mode);
1775 else if (pmif->kind == controller_sh_ata6)
1776 ret = set_timings_udma_shasta( &timing_local[0],
1777 &timing_local[1],
1778 mode);
1779 else
1780 ret = set_timings_udma_ata4(&timing_local[0], mode);
1781 if (ret)
1782 return 0;
1783
1784 /* Set feature on drive */
1785 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1786 ret = pmac_ide_do_setfeature(drive, mode);
1787 if (ret) {
1788 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1789 return 0;
1790 }
1791
1792 /* Apply timings to controller */
1793 *timings = timing_local[0];
1794 *timings2 = timing_local[1];
1795
1796 /* Set speed info in drive */
1797 drive->current_speed = mode;
1798 if (!drive->init_speed)
1799 drive->init_speed = mode;
1800
1801 return 1;
1802}
1803
1804/*
1805 * Check what is the best DMA timing setting for the drive and
1806 * call appropriate functions to apply it.
1807 */
aacaf9bd 1808static int
1da177e4
LT		 1809pmac_ide_dma_check(ide_drive_t *drive)
1810{
1811 struct hd_driveid *id = drive->id;
1812 ide_hwif_t *hwif = HWIF(drive);
1813 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1814 int enable = 1;
1815 int map;
1816 drive->using_dma = 0;
1817
1818 if (drive->media == ide_floppy)
1819 enable = 0;
1820 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1821 enable = 0;
1822 if (__ide_dma_bad_drive(drive))
1823 enable = 0;
1824
1825 if (enable) {
75b1d975
BZ		 1826 u8 mode = ide_max_dma_mode(drive);
1827
1828 if (mode >= XFER_UDMA_0)
1da177e4 1829 drive->using_dma = pmac_ide_udma_enable(drive, mode);
75b1d975 1830 else if (mode >= XFER_MW_DMA_0)
1da177e4
LT		 1831 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1832 hwif->OUTB(0, IDE_CONTROL_REG);
1833 /* Apply settings to controller */
1834 pmac_ide_do_update_timings(drive);
1835 }
1836 return 0;
1837}
1838
1839/*
1840 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1841 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1842 */
aacaf9bd 1843static int
1da177e4
LT		 1844pmac_ide_dma_setup(ide_drive_t *drive)
1845{
1846 ide_hwif_t *hwif = HWIF(drive);
1847 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1848 struct request *rq = HWGROUP(drive)->rq;
1849 u8 unit = (drive->select.b.unit & 0x01);
1850 u8 ata4;
1851
1852 if (pmif == NULL)
1853 return 1;
1854 ata4 = (pmif->kind == controller_kl_ata4);
1855
1856 if (!pmac_ide_build_dmatable(drive, rq)) {
1857 ide_map_sg(drive, rq);
1858 return 1;
1859 }
1860
1861 /* Apple adds 60ns to wrDataSetup on reads */
1862 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1863 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1864 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1865 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1866 }
1867
1868 drive->waiting_for_dma = 1;
1869
1870 return 0;
1871}
1872
aacaf9bd 1873static void
1da177e4
LT		 1874pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1875{
1876 /* issue cmd to drive */
1877 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1878}
1879
1880/*
1881 * Kick the DMA controller into life after the DMA command has been issued
1882 * to the drive.
1883 */
aacaf9bd 1884static void
1da177e4
LT		 1885pmac_ide_dma_start(ide_drive_t *drive)
1886{
1887 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1888 volatile struct dbdma_regs __iomem *dma;
1889
1890 dma = pmif->dma_regs;
1891
1892 writel((RUN << 16) | RUN, &dma->control);
1893 /* Make sure it gets to the controller right now */
1894 (void)readl(&dma->control);
1895}
1896
1897/*
1898 * After a DMA transfer, make sure the controller is stopped
1899 */
aacaf9bd 1900static int
1da177e4
LT		 1901pmac_ide_dma_end (ide_drive_t *drive)
1902{
1903 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1904 volatile struct dbdma_regs __iomem *dma;
1905 u32 dstat;
1906
1907 if (pmif == NULL)
1908 return 0;
1909 dma = pmif->dma_regs;
1910
1911 drive->waiting_for_dma = 0;
1912 dstat = readl(&dma->status);
1913 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1914 pmac_ide_destroy_dmatable(drive);
1915 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1916 * in theory, but with ATAPI decices doing buffer underruns, that would
1917 * cause us to disable DMA, which isn't what we want
1918 */
1919 return (dstat & (RUN|DEAD)) != RUN;
1920}
1921
1922/*
1923 * Check out that the interrupt we got was for us. We can't always know this
1924 * for sure with those Apple interfaces (well, we could on the recent ones but
1925 * that's not implemented yet), on the other hand, we don't have shared interrupts
1926 * so it's not really a problem
1927 */
aacaf9bd 1928static int
1da177e4
LT		 1929pmac_ide_dma_test_irq (ide_drive_t *drive)
1930{
1931 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1932 volatile struct dbdma_regs __iomem *dma;
1933 unsigned long status, timeout;
1934
1935 if (pmif == NULL)
1936 return 0;
1937 dma = pmif->dma_regs;
1938
1939 /* We have to things to deal with here:
1940 *
1941 * - The dbdma won't stop if the command was started
1942 * but completed with an error without transferring all
1943 * datas. This happens when bad blocks are met during
1944 * a multi-block transfer.
1945 *
1946 * - The dbdma fifo hasn't yet finished flushing to
1947 * to system memory when the disk interrupt occurs.
1948 *
1949 */
1950
1951 /* If ACTIVE is cleared, the STOP command have passed and
1952 * transfer is complete.
1953 */
1954 status = readl(&dma->status);
1955 if (!(status & ACTIVE))
1956 return 1;
1957 if (!drive->waiting_for_dma)
1958 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1959 called while not waiting\n", HWIF(drive)->index);
1960
1961 /* If dbdma didn't execute the STOP command yet, the
1962 * active bit is still set. We consider that we aren't
1963 * sharing interrupts (which is hopefully the case with
1964 * those controllers) and so we just try to flush the
1965 * channel for pending data in the fifo
1966 */
1967 udelay(1);
1968 writel((FLUSH << 16) | FLUSH, &dma->control);
1969 timeout = 0;
1970 for (;;) {
1971 udelay(1);
1972 status = readl(&dma->status);
1973 if ((status & FLUSH) == 0)
1974 break;
1975 if (++timeout > 100) {
1976 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1977 timeout flushing channel\n", HWIF(drive)->index);
1978 break;
1979 }
1980 }
1981 return 1;
1982}
1983
7469aaf6 1984static void pmac_ide_dma_host_off(ide_drive_t *drive)
1da177e4 1985{
1da177e4
LT		 1986}
1987
9e5755bc 1988static void pmac_ide_dma_host_on(ide_drive_t *drive)
1da177e4 1989{
1da177e4
LT		 1990}
1991
841d2a9b
SS		 1992static void
1993pmac_ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 1994{
1995 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1996 volatile struct dbdma_regs __iomem *dma;
1997 unsigned long status;
1998
1999 if (pmif == NULL)
841d2a9b 2000 return;
1da177e4
LT		 2001 dma = pmif->dma_regs;
2002
2003 status = readl(&dma->status);
2004 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1da177e4
LT		 2005}
2006
2007/*
2008 * Allocate the data structures needed for using DMA with an interface
2009 * and fill the proper list of functions pointers
2010 */
2011static void __init
2012pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2013{
2014 /* We won't need pci_dev if we switch to generic consistent
2015 * DMA routines ...
2016 */
2017 if (hwif->pci_dev == NULL)
2018 return;
2019 /*
2020 * Allocate space for the DBDMA commands.
2021 * The +2 is +1 for the stop command and +1 to allow for
2022 * aligning the start address to a multiple of 16 bytes.
2023 */
2024 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2025 hwif->pci_dev,
2026 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2027 &hwif->dmatable_dma);
2028 if (pmif->dma_table_cpu == NULL) {
2029 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2030 hwif->name);
2031 return;
2032 }
2033
7469aaf6 2034 hwif->dma_off_quietly = &ide_dma_off_quietly;
1da177e4
LT		 2035 hwif->ide_dma_on = &__ide_dma_on;
2036 hwif->ide_dma_check = &pmac_ide_dma_check;
2037 hwif->dma_setup = &pmac_ide_dma_setup;
2038 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2039 hwif->dma_start = &pmac_ide_dma_start;
2040 hwif->ide_dma_end = &pmac_ide_dma_end;
2041 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
7469aaf6 2042 hwif->dma_host_off = &pmac_ide_dma_host_off;
ccf35289 2043 hwif->dma_host_on = &pmac_ide_dma_host_on;
c283f5db 2044 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b 2045 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
1da177e4
LT		 2046
2047 hwif->atapi_dma = 1;
2048 switch(pmif->kind) {
2049 case controller_sh_ata6:
2050 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2051 hwif->mwdma_mask = 0x07;
2052 hwif->swdma_mask = 0x00;
2053 break;
2054 case controller_un_ata6:
2055 case controller_k2_ata6:
2056 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2057 hwif->mwdma_mask = 0x07;
2058 hwif->swdma_mask = 0x00;
2059 break;
2060 case controller_kl_ata4:
2061 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2062 hwif->mwdma_mask = 0x07;
2063 hwif->swdma_mask = 0x00;
2064 break;
2065 default:
2066 hwif->ultra_mask = 0x00;
2067 hwif->mwdma_mask = 0x07;
2068 hwif->swdma_mask = 0x00;
2069 break;
2070 }
2071}
2072
2073#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linux kernel - Deliverables
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