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xen: disable split pte locks for now
[deliverable/linux.git] / drivers / ide / ppc / pmac.c
CommitLineData
1da177e4 1/*
f30c2269 2 * linux/drivers/ide/ppc/pmac.c
1da177e4
LT		 3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
1da177e4
LT		 25#include <linux/types.h>
26#include <linux/kernel.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
9e5755bc 51#include "../ide-timing.h"
1da177e4
LT		 52
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78#endif
79
80} pmac_ide_hwif_t;
81
aacaf9bd 82static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
1da177e4
LT		 83static int pmac_ide_count;
84
85enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93};
94
95static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103};
104
105/*
106 * Extra registers, both 32-bit little-endian
107 */
108#define IDE_TIMING_CONFIG 0x200
109#define IDE_INTERRUPT 0x300
110
111/* Kauai (U2) ATA has different register setup */
112#define IDE_KAUAI_PIO_CONFIG 0x200
113#define IDE_KAUAI_ULTRA_CONFIG 0x210
114#define IDE_KAUAI_POLL_CONFIG 0x220
115
116/*
117 * Timing configuration register definitions
118 */
119
120/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126/* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130#define TR_133_PIOREG_PIO_MASK 0xff000fff
131#define TR_133_PIOREG_MDMA_MASK 0x00fff800
132#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133#define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151#define TR_100_PIOREG_PIO_MASK 0xff000fff
152#define TR_100_PIOREG_MDMA_MASK 0x00fff000
153#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154#define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173#define TR_66_UDMA_MASK 0xfff00000
174#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176#define TR_66_UDMA_ADDRSETUP_SHIFT 29
177#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178#define TR_66_UDMA_RDY2PAUS_SHIFT 25
179#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180#define TR_66_UDMA_WRDATASETUP_SHIFT 21
181#define TR_66_MDMA_MASK 0x000ffc00
182#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183#define TR_66_MDMA_RECOVERY_SHIFT 15
184#define TR_66_MDMA_ACCESS_MASK 0x00007c00
185#define TR_66_MDMA_ACCESS_SHIFT 10
186#define TR_66_PIO_MASK 0x000003ff
187#define TR_66_PIO_RECOVERY_MASK 0x000003e0
188#define TR_66_PIO_RECOVERY_SHIFT 5
189#define TR_66_PIO_ACCESS_MASK 0x0000001f
190#define TR_66_PIO_ACCESS_SHIFT 0
191
192/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203#define TR_33_MDMA_MASK 0x003ff800
204#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205#define TR_33_MDMA_RECOVERY_SHIFT 16
206#define TR_33_MDMA_ACCESS_MASK 0x0000f800
207#define TR_33_MDMA_ACCESS_SHIFT 11
208#define TR_33_MDMA_HALFTICK 0x00200000
209#define TR_33_PIO_MASK 0x000007ff
210#define TR_33_PIO_E 0x00000400
211#define TR_33_PIO_RECOVERY_MASK 0x000003e0
212#define TR_33_PIO_RECOVERY_SHIFT 5
213#define TR_33_PIO_ACCESS_MASK 0x0000001f
214#define TR_33_PIO_ACCESS_SHIFT 0
215
216/*
217 * Interrupt register definitions
218 */
219#define IDE_INTR_DMA 0x80000000
220#define IDE_INTR_DEVICE 0x40000000
221
222/*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225#define KAUAI_FCR_UATA_MAGIC 0x00000004
226#define KAUAI_FCR_UATA_RESET_N 0x00000002
227#define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231/* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241};
242
aacaf9bd 243struct mdma_timings_t mdma_timings_33[] =
1da177e4
LT		 244{
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254};
255
aacaf9bd 256struct mdma_timings_t mdma_timings_33k[] =
1da177e4
LT		 257{
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267};
268
aacaf9bd 269struct mdma_timings_t mdma_timings_66[] =
1da177e4
LT		 270{
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280};
281
282/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
aacaf9bd 287} kl66_udma_timings[] =
1da177e4
LT		 288{
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294};
295
296/* UniNorth 2 ATA/100 timings */
297struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300};
301
aacaf9bd 302static struct kauai_timing kauai_pio_timings[] =
1da177e4
LT		 303{
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
314 { 120 , 0x04000148 }
315};
316
aacaf9bd 317static struct kauai_timing kauai_mdma_timings[] =
1da177e4
LT		 318{
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329};
330
aacaf9bd 331static struct kauai_timing kauai_udma_timings[] =
1da177e4
LT		 332{
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340};
341
aacaf9bd 342static struct kauai_timing shasta_pio_timings[] =
1da177e4
LT		 343{
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
354 { 120 , 0x0400010a }
355};
356
aacaf9bd 357static struct kauai_timing shasta_mdma_timings[] =
1da177e4
LT		 358{
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
368 { 0 , 0 },
369};
370
aacaf9bd 371static struct kauai_timing shasta_udma133_timings[] =
1da177e4
LT		 372{
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
380 { 0 , 0 },
381};
382
383
384static inline u32
385kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
386{
387 int i;
388
389 for (i=0; table[i].cycle_time; i++)
390 if (cycle_time > table[i+1].cycle_time)
391 return table[i].timing_reg;
392 return 0;
393}
394
395/* allow up to 256 DBDMA commands per xfer */
396#define MAX_DCMDS 256
397
398/*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410#define IDE_WAKEUP_DELAY (1*HZ)
411
412static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
413static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
414static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
415static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
416static void pmac_ide_selectproc(ide_drive_t *drive);
417static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
418
419#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420
1da177e4
LT		 421/*
422 * N.B. this can't be an initfunc, because the media-bay task can
423 * call ide_[un]register at any time.
424 */
aacaf9bd 425void
1da177e4
LT		 426pmac_ide_init_hwif_ports(hw_regs_t *hw,
427 unsigned long data_port, unsigned long ctrl_port,
428 int *irq)
429{
430 int i, ix;
431
432 if (data_port == 0)
433 return;
434
435 for (ix = 0; ix < MAX_HWIFS; ++ix)
436 if (data_port == pmac_ide[ix].regbase)
437 break;
438
439 if (ix >= MAX_HWIFS) {
440 /* Probably a PCI interface... */
441 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
442 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
443 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
444 return;
445 }
446
447 for (i = 0; i < 8; ++i)
448 hw->io_ports[i] = data_port + i * 0x10;
449 hw->io_ports[8] = data_port + 0x160;
450
451 if (irq != NULL)
452 *irq = pmac_ide[ix].irq;
22192ccd
BH		 453
454 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
1da177e4
LT		 455}
456
457#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
458
459/*
460 * Apply the timings of the proper unit (master/slave) to the shared
461 * timing register when selecting that unit. This version is for
462 * ASICs with a single timing register
463 */
aacaf9bd 464static void
1da177e4
LT		 465pmac_ide_selectproc(ide_drive_t *drive)
466{
467 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
468
469 if (pmif == NULL)
470 return;
471
472 if (drive->select.b.unit & 0x01)
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
474 else
475 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
477}
478
479/*
480 * Apply the timings of the proper unit (master/slave) to the shared
481 * timing register when selecting that unit. This version is for
482 * ASICs with a dual timing register (Kauai)
483 */
aacaf9bd 484static void
1da177e4
LT		 485pmac_ide_kauai_selectproc(ide_drive_t *drive)
486{
487 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
488
489 if (pmif == NULL)
490 return;
491
492 if (drive->select.b.unit & 0x01) {
493 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
495 } else {
496 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
498 }
499 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
500}
501
502/*
503 * Force an update of controller timing values for a given drive
504 */
aacaf9bd 505static void
1da177e4
LT		 506pmac_ide_do_update_timings(ide_drive_t *drive)
507{
508 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
509
510 if (pmif == NULL)
511 return;
512
513 if (pmif->kind == controller_sh_ata6 ||
514 pmif->kind == controller_un_ata6 ||
515 pmif->kind == controller_k2_ata6)
516 pmac_ide_kauai_selectproc(drive);
517 else
518 pmac_ide_selectproc(drive);
519}
520
521static void
522pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
523{
524 u32 tmp;
525
526 writeb(value, (void __iomem *) port);
527 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
528}
529
530/*
531 * Send the SET_FEATURE IDE command to the drive and update drive->id with
532 * the new state. We currently don't use the generic routine as it used to
533 * cause various trouble, especially with older mediabays.
534 * This code is sometimes triggering a spurrious interrupt though, I need
535 * to sort that out sooner or later and see if I can finally get the
536 * common version to work properly in all cases
537 */
aacaf9bd 538static int
1da177e4
LT		 539pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
540{
541 ide_hwif_t *hwif = HWIF(drive);
542 int result = 1;
543
544 disable_irq_nosync(hwif->irq);
545 udelay(1);
546 SELECT_DRIVE(drive);
547 SELECT_MASK(drive, 0);
548 udelay(1);
549 /* Get rid of pending error state */
550 (void) hwif->INB(IDE_STATUS_REG);
551 /* Timeout bumped for some powerbooks */
552 if (wait_for_ready(drive, 2000)) {
553 /* Timeout bumped for some powerbooks */
554 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
555 "before SET_FEATURE!\n", drive->name);
556 goto out;
557 }
558 udelay(10);
559 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
560 hwif->OUTB(command, IDE_NSECTOR_REG);
561 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
562 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
563 udelay(1);
564 /* Timeout bumped for some powerbooks */
565 result = wait_for_ready(drive, 2000);
566 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
567 if (result)
568 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
569 "after SET_FEATURE !\n", drive->name);
570out:
571 SELECT_MASK(drive, 0);
572 if (result == 0) {
573 drive->id->dma_ultra &= ~0xFF00;
574 drive->id->dma_mword &= ~0x0F00;
575 drive->id->dma_1word &= ~0x0F00;
576 switch(command) {
577 case XFER_UDMA_7:
578 drive->id->dma_ultra |= 0x8080; break;
579 case XFER_UDMA_6:
580 drive->id->dma_ultra |= 0x4040; break;
581 case XFER_UDMA_5:
582 drive->id->dma_ultra |= 0x2020; break;
583 case XFER_UDMA_4:
584 drive->id->dma_ultra |= 0x1010; break;
585 case XFER_UDMA_3:
586 drive->id->dma_ultra |= 0x0808; break;
587 case XFER_UDMA_2:
588 drive->id->dma_ultra |= 0x0404; break;
589 case XFER_UDMA_1:
590 drive->id->dma_ultra |= 0x0202; break;
591 case XFER_UDMA_0:
592 drive->id->dma_ultra |= 0x0101; break;
593 case XFER_MW_DMA_2:
594 drive->id->dma_mword |= 0x0404; break;
595 case XFER_MW_DMA_1:
596 drive->id->dma_mword |= 0x0202; break;
597 case XFER_MW_DMA_0:
598 drive->id->dma_mword |= 0x0101; break;
599 case XFER_SW_DMA_2:
600 drive->id->dma_1word |= 0x0404; break;
601 case XFER_SW_DMA_1:
602 drive->id->dma_1word |= 0x0202; break;
603 case XFER_SW_DMA_0:
604 drive->id->dma_1word |= 0x0101; break;
605 default: break;
606 }
59785c8f
BZ		 607 if (!drive->init_speed)
608 drive->init_speed = command;
609 drive->current_speed = command;
1da177e4
LT		 610 }
611 enable_irq(hwif->irq);
612 return result;
613}
614
615/*
616 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
617 */
aacaf9bd 618static void
1da177e4
LT		 619pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
620{
1da177e4
LT		 621 u32 *timings;
622 unsigned accessTicks, recTicks;
623 unsigned accessTime, recTime;
624 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
7dd00083
BZ		 625 unsigned int cycle_time;
626
1da177e4
LT		 627 if (pmif == NULL)
628 return;
629
630 /* which drive is it ? */
631 timings = &pmif->timings[drive->select.b.unit & 0x01];
632
2134758d 633 pio = ide_get_best_pio_mode(drive, pio, 4);
7dd00083 634 cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4
LT		 635
636 switch (pmif->kind) {
637 case controller_sh_ata6: {
638 /* 133Mhz cell */
7dd00083 639 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
1da177e4
LT		 640 if (tr == 0)
641 return;
642 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
643 break;
644 }
645 case controller_un_ata6:
646 case controller_k2_ata6: {
647 /* 100Mhz cell */
7dd00083 648 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
1da177e4
LT		 649 if (tr == 0)
650 return;
651 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
652 break;
653 }
654 case controller_kl_ata4:
655 /* 66Mhz cell */
7dd00083 656 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 657 - ide_pio_timings[pio].setup_time;
658 recTime = max(recTime, 150U);
659 accessTime = ide_pio_timings[pio].active_time;
660 accessTime = max(accessTime, 150U);
661 accessTicks = SYSCLK_TICKS_66(accessTime);
662 accessTicks = min(accessTicks, 0x1fU);
663 recTicks = SYSCLK_TICKS_66(recTime);
664 recTicks = min(recTicks, 0x1fU);
665 *timings = ((*timings) & ~TR_66_PIO_MASK) |
666 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
667 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
668 break;
669 default: {
670 /* 33Mhz cell */
671 int ebit = 0;
7dd00083 672 recTime = cycle_time - ide_pio_timings[pio].active_time
1da177e4
LT		 673 - ide_pio_timings[pio].setup_time;
674 recTime = max(recTime, 150U);
675 accessTime = ide_pio_timings[pio].active_time;
676 accessTime = max(accessTime, 150U);
677 accessTicks = SYSCLK_TICKS(accessTime);
678 accessTicks = min(accessTicks, 0x1fU);
679 accessTicks = max(accessTicks, 4U);
680 recTicks = SYSCLK_TICKS(recTime);
681 recTicks = min(recTicks, 0x1fU);
682 recTicks = max(recTicks, 5U) - 4;
683 if (recTicks > 9) {
684 recTicks--; /* guess, but it's only for PIO0, so... */
685 ebit = 1;
686 }
687 *timings = ((*timings) & ~TR_33_PIO_MASK) |
688 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
689 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
690 if (ebit)
691 *timings |= TR_33_PIO_E;
692 break;
693 }
694 }
695
696#ifdef IDE_PMAC_DEBUG
697 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
698 drive->name, pio, *timings);
699#endif
700
701 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
702 pmac_ide_do_update_timings(drive);
703}
704
705#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
706
707/*
708 * Calculate KeyLargo ATA/66 UDMA timings
709 */
aacaf9bd 710static int
1da177e4
LT		 711set_timings_udma_ata4(u32 *timings, u8 speed)
712{
713 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
714
715 if (speed > XFER_UDMA_4)
716 return 1;
717
718 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
719 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
720 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
721
722 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
723 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
724 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
725 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
726 TR_66_UDMA_EN;
727#ifdef IDE_PMAC_DEBUG
728 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
729 speed & 0xf, *timings);
730#endif
731
732 return 0;
733}
734
735/*
736 * Calculate Kauai ATA/100 UDMA timings
737 */
aacaf9bd 738static int
1da177e4
LT		 739set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
740{
741 struct ide_timing *t = ide_timing_find_mode(speed);
742 u32 tr;
743
744 if (speed > XFER_UDMA_5 || t == NULL)
745 return 1;
746 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
747 if (tr == 0)
748 return 1;
749 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
750 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
751
752 return 0;
753}
754
755/*
756 * Calculate Shasta ATA/133 UDMA timings
757 */
aacaf9bd 758static int
1da177e4
LT		 759set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
760{
761 struct ide_timing *t = ide_timing_find_mode(speed);
762 u32 tr;
763
764 if (speed > XFER_UDMA_6 || t == NULL)
765 return 1;
766 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
767 if (tr == 0)
768 return 1;
769 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
770 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
771
772 return 0;
773}
774
775/*
776 * Calculate MDMA timings for all cells
777 */
aacaf9bd 778static int
1da177e4
LT		 779set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
780 u8 speed, int drive_cycle_time)
781{
782 int cycleTime, accessTime = 0, recTime = 0;
783 unsigned accessTicks, recTicks;
784 struct mdma_timings_t* tm = NULL;
785 int i;
786
787 /* Get default cycle time for mode */
788 switch(speed & 0xf) {
789 case 0: cycleTime = 480; break;
790 case 1: cycleTime = 150; break;
791 case 2: cycleTime = 120; break;
792 default:
793 return 1;
794 }
795 /* Adjust for drive */
796 if (drive_cycle_time && drive_cycle_time > cycleTime)
797 cycleTime = drive_cycle_time;
798 /* OHare limits according to some old Apple sources */
799 if ((intf_type == controller_ohare) && (cycleTime < 150))
800 cycleTime = 150;
801 /* Get the proper timing array for this controller */
802 switch(intf_type) {
803 case controller_sh_ata6:
804 case controller_un_ata6:
805 case controller_k2_ata6:
806 break;
807 case controller_kl_ata4:
808 tm = mdma_timings_66;
809 break;
810 case controller_kl_ata3:
811 tm = mdma_timings_33k;
812 break;
813 default:
814 tm = mdma_timings_33;
815 break;
816 }
817 if (tm != NULL) {
818 /* Lookup matching access & recovery times */
819 i = -1;
820 for (;;) {
821 if (tm[i+1].cycleTime < cycleTime)
822 break;
823 i++;
824 }
825 if (i < 0)
826 return 1;
827 cycleTime = tm[i].cycleTime;
828 accessTime = tm[i].accessTime;
829 recTime = tm[i].recoveryTime;
830
831#ifdef IDE_PMAC_DEBUG
832 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
833 drive->name, cycleTime, accessTime, recTime);
834#endif
835 }
836 switch(intf_type) {
837 case controller_sh_ata6: {
838 /* 133Mhz cell */
839 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
840 if (tr == 0)
841 return 1;
842 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
843 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
844 }
845 case controller_un_ata6:
846 case controller_k2_ata6: {
847 /* 100Mhz cell */
848 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
849 if (tr == 0)
850 return 1;
851 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
852 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
853 }
854 break;
855 case controller_kl_ata4:
856 /* 66Mhz cell */
857 accessTicks = SYSCLK_TICKS_66(accessTime);
858 accessTicks = min(accessTicks, 0x1fU);
859 accessTicks = max(accessTicks, 0x1U);
860 recTicks = SYSCLK_TICKS_66(recTime);
861 recTicks = min(recTicks, 0x1fU);
862 recTicks = max(recTicks, 0x3U);
863 /* Clear out mdma bits and disable udma */
864 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
865 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
866 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
867 break;
868 case controller_kl_ata3:
869 /* 33Mhz cell on KeyLargo */
870 accessTicks = SYSCLK_TICKS(accessTime);
871 accessTicks = max(accessTicks, 1U);
872 accessTicks = min(accessTicks, 0x1fU);
873 accessTime = accessTicks * IDE_SYSCLK_NS;
874 recTicks = SYSCLK_TICKS(recTime);
875 recTicks = max(recTicks, 1U);
876 recTicks = min(recTicks, 0x1fU);
877 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
878 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
879 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
880 break;
881 default: {
882 /* 33Mhz cell on others */
883 int halfTick = 0;
884 int origAccessTime = accessTime;
885 int origRecTime = recTime;
886
887 accessTicks = SYSCLK_TICKS(accessTime);
888 accessTicks = max(accessTicks, 1U);
889 accessTicks = min(accessTicks, 0x1fU);
890 accessTime = accessTicks * IDE_SYSCLK_NS;
891 recTicks = SYSCLK_TICKS(recTime);
892 recTicks = max(recTicks, 2U) - 1;
893 recTicks = min(recTicks, 0x1fU);
894 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
895 if ((accessTicks > 1) &&
896 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
897 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
898 halfTick = 1;
899 accessTicks--;
900 }
901 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
902 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
903 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
904 if (halfTick)
905 *timings |= TR_33_MDMA_HALFTICK;
906 }
907 }
908#ifdef IDE_PMAC_DEBUG
909 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
910 drive->name, speed & 0xf, *timings);
911#endif
912 return 0;
913}
914#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
915
916/*
917 * Speedproc. This function is called by the core to set any of the standard
918 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
919 * You may notice we don't use this function on normal "dma check" operation,
920 * our dedicated function is more precise as it uses the drive provided
921 * cycle time value. We should probably fix this one to deal with that too...
922 */
aacaf9bd 923static int
1da177e4
LT		 924pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
925{
926 int unit = (drive->select.b.unit & 0x01);
927 int ret = 0;
928 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
929 u32 *timings, *timings2;
930
931 if (pmif == NULL)
932 return 1;
933
934 timings = &pmif->timings[unit];
935 timings2 = &pmif->timings[unit+2];
936
937 switch(speed) {
938#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
939 case XFER_UDMA_6:
940 if (pmif->kind != controller_sh_ata6)
941 return 1;
942 case XFER_UDMA_5:
943 if (pmif->kind != controller_un_ata6 &&
944 pmif->kind != controller_k2_ata6 &&
945 pmif->kind != controller_sh_ata6)
946 return 1;
947 case XFER_UDMA_4:
948 case XFER_UDMA_3:
49521f97
BZ		 949 if (drive->hwif->cbl != ATA_CBL_PATA80)
950 return 1;
1da177e4
LT		 951 case XFER_UDMA_2:
952 case XFER_UDMA_1:
953 case XFER_UDMA_0:
954 if (pmif->kind == controller_kl_ata4)
955 ret = set_timings_udma_ata4(timings, speed);
956 else if (pmif->kind == controller_un_ata6
957 || pmif->kind == controller_k2_ata6)
958 ret = set_timings_udma_ata6(timings, timings2, speed);
959 else if (pmif->kind == controller_sh_ata6)
960 ret = set_timings_udma_shasta(timings, timings2, speed);
961 else
962 ret = 1;
963 break;
964 case XFER_MW_DMA_2:
965 case XFER_MW_DMA_1:
966 case XFER_MW_DMA_0:
967 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
968 break;
969 case XFER_SW_DMA_2:
970 case XFER_SW_DMA_1:
971 case XFER_SW_DMA_0:
972 return 1;
973#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
974 case XFER_PIO_4:
975 case XFER_PIO_3:
976 case XFER_PIO_2:
977 case XFER_PIO_1:
978 case XFER_PIO_0:
979 pmac_ide_tuneproc(drive, speed & 0x07);
980 break;
981 default:
982 ret = 1;
983 }
984 if (ret)
985 return ret;
986
987 ret = pmac_ide_do_setfeature(drive, speed);
988 if (ret)
989 return ret;
990
991 pmac_ide_do_update_timings(drive);
1da177e4
LT		 992
993 return 0;
994}
995
996/*
997 * Blast some well known "safe" values to the timing registers at init or
998 * wakeup from sleep time, before we do real calculation
999 */
aacaf9bd 1000static void
1da177e4
LT		 1001sanitize_timings(pmac_ide_hwif_t *pmif)
1002{
1003 unsigned int value, value2 = 0;
1004
1005 switch(pmif->kind) {
1006 case controller_sh_ata6:
1007 value = 0x0a820c97;
1008 value2 = 0x00033031;
1009 break;
1010 case controller_un_ata6:
1011 case controller_k2_ata6:
1012 value = 0x08618a92;
1013 value2 = 0x00002921;
1014 break;
1015 case controller_kl_ata4:
1016 value = 0x0008438c;
1017 break;
1018 case controller_kl_ata3:
1019 value = 0x00084526;
1020 break;
1021 case controller_heathrow:
1022 case controller_ohare:
1023 default:
1024 value = 0x00074526;
1025 break;
1026 }
1027 pmif->timings[0] = pmif->timings[1] = value;
1028 pmif->timings[2] = pmif->timings[3] = value2;
1029}
1030
aacaf9bd 1031unsigned long
1da177e4
LT		 1032pmac_ide_get_base(int index)
1033{
1034 return pmac_ide[index].regbase;
1035}
1036
aacaf9bd 1037int
1da177e4
LT		 1038pmac_ide_check_base(unsigned long base)
1039{
1040 int ix;
1041
1042 for (ix = 0; ix < MAX_HWIFS; ++ix)
1043 if (base == pmac_ide[ix].regbase)
1044 return ix;
1045 return -1;
1046}
1047
aacaf9bd 1048int
1da177e4
LT		 1049pmac_ide_get_irq(unsigned long base)
1050{
1051 int ix;
1052
1053 for (ix = 0; ix < MAX_HWIFS; ++ix)
1054 if (base == pmac_ide[ix].regbase)
1055 return pmac_ide[ix].irq;
1056 return 0;
1057}
1058
aacaf9bd 1059static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1da177e4
LT		 1060
1061dev_t __init
1062pmac_find_ide_boot(char *bootdevice, int n)
1063{
1064 int i;
1065
1066 /*
1067 * Look through the list of IDE interfaces for this one.
1068 */
1069 for (i = 0; i < pmac_ide_count; ++i) {
1070 char *name;
1071 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1072 continue;
1073 name = pmac_ide[i].node->full_name;
1074 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1075 /* XXX should cope with the 2nd drive as well... */
1076 return MKDEV(ide_majors[i], 0);
1077 }
1078 }
1079
1080 return 0;
1081}
1082
1083/* Suspend call back, should be called after the child devices
1084 * have actually been suspended
1085 */
1086static int
1087pmac_ide_do_suspend(ide_hwif_t *hwif)
1088{
1089 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1090
1091 /* We clear the timings */
1092 pmif->timings[0] = 0;
1093 pmif->timings[1] = 0;
1094
616299af
BH		 1095 disable_irq(pmif->irq);
1096
1da177e4
LT		 1097 /* The media bay will handle itself just fine */
1098 if (pmif->mediabay)
1099 return 0;
1100
1101 /* Kauai has bus control FCRs directly here */
1102 if (pmif->kauai_fcr) {
1103 u32 fcr = readl(pmif->kauai_fcr);
1104 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1105 writel(fcr, pmif->kauai_fcr);
1106 }
1107
1108 /* Disable the bus on older machines and the cell on kauai */
1109 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1110 0);
1111
1112 return 0;
1113}
1114
1115/* Resume call back, should be called before the child devices
1116 * are resumed
1117 */
1118static int
1119pmac_ide_do_resume(ide_hwif_t *hwif)
1120{
1121 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1122
1123 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1124 if (!pmif->mediabay) {
1125 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1126 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1127 msleep(10);
1128 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1da177e4
LT		 1129
1130 /* Kauai has it different */
1131 if (pmif->kauai_fcr) {
1132 u32 fcr = readl(pmif->kauai_fcr);
1133 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1134 writel(fcr, pmif->kauai_fcr);
1135 }
616299af
BH		 1136
1137 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1da177e4
LT		 1138 }
1139
1140 /* Sanitize drive timings */
1141 sanitize_timings(pmif);
1142
616299af
BH		 1143 enable_irq(pmif->irq);
1144
1da177e4
LT		 1145 return 0;
1146}
1147
1148/*
1149 * Setup, register & probe an IDE channel driven by this driver, this is
1150 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1151 * that ends up beeing free of any device is not kept around by this driver
1152 * (it is kept in 2.4). This introduce an interface numbering change on some
1153 * rare machines unfortunately, but it's better this way.
1154 */
1155static int
1156pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1157{
1158 struct device_node *np = pmif->node;
018a3d1d 1159 const int *bidp;
1da177e4
LT		 1160
1161 pmif->cable_80 = 0;
1162 pmif->broken_dma = pmif->broken_dma_warn = 0;
55b61fec 1163 if (of_device_is_compatible(np, "shasta-ata"))
1da177e4 1164 pmif->kind = controller_sh_ata6;
55b61fec 1165 else if (of_device_is_compatible(np, "kauai-ata"))
1da177e4 1166 pmif->kind = controller_un_ata6;
55b61fec 1167 else if (of_device_is_compatible(np, "K2-UATA"))
1da177e4 1168 pmif->kind = controller_k2_ata6;
55b61fec 1169 else if (of_device_is_compatible(np, "keylargo-ata")) {
1da177e4
LT		 1170 if (strcmp(np->name, "ata-4") == 0)
1171 pmif->kind = controller_kl_ata4;
1172 else
1173 pmif->kind = controller_kl_ata3;
55b61fec 1174 } else if (of_device_is_compatible(np, "heathrow-ata"))
1da177e4
LT		 1175 pmif->kind = controller_heathrow;
1176 else {
1177 pmif->kind = controller_ohare;
1178 pmif->broken_dma = 1;
1179 }
1180
40cd3a45 1181 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1da177e4
LT		 1182 pmif->aapl_bus_id = bidp ? *bidp : 0;
1183
1184 /* Get cable type from device-tree */
1185 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1186 || pmif->kind == controller_k2_ata6
1187 || pmif->kind == controller_sh_ata6) {
40cd3a45 1188 const char* cable = of_get_property(np, "cable-type", NULL);
1da177e4
LT		 1189 if (cable && !strncmp(cable, "80-", 3))
1190 pmif->cable_80 = 1;
1191 }
1192 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1193 * they have a 80 conductor cable, this seem to be always the case unless
1194 * the user mucked around
1195 */
55b61fec
SR		 1196 if (of_device_is_compatible(np, "K2-UATA") ||
1197 of_device_is_compatible(np, "shasta-ata"))
1da177e4
LT		 1198 pmif->cable_80 = 1;
1199
1200 /* On Kauai-type controllers, we make sure the FCR is correct */
1201 if (pmif->kauai_fcr)
1202 writel(KAUAI_FCR_UATA_MAGIC |
1203 KAUAI_FCR_UATA_RESET_N |
1204 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1205
1206 pmif->mediabay = 0;
1207
1208 /* Make sure we have sane timings */
1209 sanitize_timings(pmif);
1210
1211#ifndef CONFIG_PPC64
1212 /* XXX FIXME: Media bay stuff need re-organizing */
1213 if (np->parent && np->parent->name
1214 && strcasecmp(np->parent->name, "media-bay") == 0) {
8c870933 1215#ifdef CONFIG_PMAC_MEDIABAY
1da177e4 1216 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
8c870933 1217#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1218 pmif->mediabay = 1;
1219 if (!bidp)
1220 pmif->aapl_bus_id = 1;
1221 } else if (pmif->kind == controller_ohare) {
1222 /* The code below is having trouble on some ohare machines
1223 * (timing related ?). Until I can put my hand on one of these
1224 * units, I keep the old way
1225 */
1226 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1227 } else
1228#endif
1229 {
1230 /* This is necessary to enable IDE when net-booting */
1231 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1232 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1233 msleep(10);
1234 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1235 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1236 }
1237
1238 /* Setup MMIO ops */
1239 default_hwif_mmiops(hwif);
1240 hwif->OUTBSYNC = pmac_outbsync;
1241
1242 /* Tell common code _not_ to mess with resources */
2ad1e558 1243 hwif->mmio = 1;
1da177e4
LT		 1244 hwif->hwif_data = pmif;
1245 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1246 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1247 hwif->chipset = ide_pmac;
1248 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1249 hwif->hold = pmif->mediabay;
49521f97 1250 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 1251 hwif->drives[0].unmask = 1;
1252 hwif->drives[1].unmask = 1;
4099d143 1253 hwif->pio_mask = ATA_PIO4;
1da177e4
LT		 1254 hwif->tuneproc = pmac_ide_tuneproc;
1255 if (pmif->kind == controller_un_ata6
1256 || pmif->kind == controller_k2_ata6
1257 || pmif->kind == controller_sh_ata6)
1258 hwif->selectproc = pmac_ide_kauai_selectproc;
1259 else
1260 hwif->selectproc = pmac_ide_selectproc;
1261 hwif->speedproc = pmac_ide_tune_chipset;
1262
1da177e4
LT		 1263 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1264 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1265 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1266
8c870933 1267#ifdef CONFIG_PMAC_MEDIABAY
1da177e4
LT		 1268 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1269 hwif->noprobe = 0;
8c870933 1270#endif /* CONFIG_PMAC_MEDIABAY */
1da177e4
LT		 1271
1272 hwif->sg_max_nents = MAX_DCMDS;
1273
1274#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1275 /* has a DBDMA controller channel */
1276 if (pmif->dma_regs)
1277 pmac_ide_setup_dma(pmif, hwif);
1278#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1279
1280 /* We probe the hwif now */
1281 probe_hwif_init(hwif);
1282
5cbf79cd
BZ		 1283 ide_proc_register_port(hwif);
1284
1da177e4
LT		 1285 return 0;
1286}
1287
1288/*
1289 * Attach to a macio probed interface
1290 */
1291static int __devinit
5e655772 1292pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1293{
1294 void __iomem *base;
1295 unsigned long regbase;
1296 int irq;
1297 ide_hwif_t *hwif;
1298 pmac_ide_hwif_t *pmif;
1299 int i, rc;
1300
1301 i = 0;
1302 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1303 || pmac_ide[i].node != NULL))
1304 ++i;
1305 if (i >= MAX_HWIFS) {
1306 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1307 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1308 return -ENODEV;
1309 }
1310
1311 pmif = &pmac_ide[i];
1312 hwif = &ide_hwifs[i];
1313
cc5d0189 1314 if (macio_resource_count(mdev) == 0) {
1da177e4
LT		 1315 printk(KERN_WARNING "ide%d: no address for %s\n",
1316 i, mdev->ofdev.node->full_name);
1317 return -ENXIO;
1318 }
1319
1320 /* Request memory resource for IO ports */
1321 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1322 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1323 return -EBUSY;
1324 }
1325
1326 /* XXX This is bogus. Should be fixed in the registry by checking
1327 * the kind of host interrupt controller, a bit like gatwick
1328 * fixes in irq.c. That works well enough for the single case
1329 * where that happens though...
1330 */
1331 if (macio_irq_count(mdev) == 0) {
1332 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1333 i, mdev->ofdev.node->full_name);
69917c26 1334 irq = irq_create_mapping(NULL, 13);
1da177e4
LT		 1335 } else
1336 irq = macio_irq(mdev, 0);
1337
1338 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1339 regbase = (unsigned long) base;
1340
1341 hwif->pci_dev = mdev->bus->pdev;
1342 hwif->gendev.parent = &mdev->ofdev.dev;
1343
1344 pmif->mdev = mdev;
1345 pmif->node = mdev->ofdev.node;
1346 pmif->regbase = regbase;
1347 pmif->irq = irq;
1348 pmif->kauai_fcr = NULL;
1349#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1350 if (macio_resource_count(mdev) >= 2) {
1351 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1352 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1353 else
1354 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1355 } else
1356 pmif->dma_regs = NULL;
1357#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1358 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1359
1360 rc = pmac_ide_setup_device(pmif, hwif);
1361 if (rc != 0) {
1362 /* The inteface is released to the common IDE layer */
1363 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1364 iounmap(base);
1365 if (pmif->dma_regs)
1366 iounmap(pmif->dma_regs);
1367 memset(pmif, 0, sizeof(*pmif));
1368 macio_release_resource(mdev, 0);
1369 if (pmif->dma_regs)
1370 macio_release_resource(mdev, 1);
1371 }
1372
1373 return rc;
1374}
1375
1376static int
8b4b8a24 1377pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1da177e4
LT		 1378{
1379 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1380 int rc = 0;
1381
8b4b8a24
DB		 1382 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1383 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1384 rc = pmac_ide_do_suspend(hwif);
1385 if (rc == 0)
8b4b8a24 1386 mdev->ofdev.dev.power.power_state = mesg;
1da177e4
LT		 1387 }
1388
1389 return rc;
1390}
1391
1392static int
1393pmac_ide_macio_resume(struct macio_dev *mdev)
1394{
1395 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1396 int rc = 0;
1397
ca078bae 1398 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1399 rc = pmac_ide_do_resume(hwif);
1400 if (rc == 0)
829ca9a3 1401 mdev->ofdev.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1402 }
1403
1404 return rc;
1405}
1406
1407/*
1408 * Attach to a PCI probed interface
1409 */
1410static int __devinit
1411pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1412{
1413 ide_hwif_t *hwif;
1414 struct device_node *np;
1415 pmac_ide_hwif_t *pmif;
1416 void __iomem *base;
1417 unsigned long rbase, rlen;
1418 int i, rc;
1419
1420 np = pci_device_to_OF_node(pdev);
1421 if (np == NULL) {
1422 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1423 return -ENODEV;
1424 }
1425 i = 0;
1426 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1427 || pmac_ide[i].node != NULL))
1428 ++i;
1429 if (i >= MAX_HWIFS) {
1430 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1431 printk(KERN_ERR " %s\n", np->full_name);
1432 return -ENODEV;
1433 }
1434
1435 pmif = &pmac_ide[i];
1436 hwif = &ide_hwifs[i];
1437
1438 if (pci_enable_device(pdev)) {
1439 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1440 i, np->full_name);
1441 return -ENXIO;
1442 }
1443 pci_set_master(pdev);
1444
1445 if (pci_request_regions(pdev, "Kauai ATA")) {
1446 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1447 i, np->full_name);
1448 return -ENXIO;
1449 }
1450
1451 hwif->pci_dev = pdev;
1452 hwif->gendev.parent = &pdev->dev;
1453 pmif->mdev = NULL;
1454 pmif->node = np;
1455
1456 rbase = pci_resource_start(pdev, 0);
1457 rlen = pci_resource_len(pdev, 0);
1458
1459 base = ioremap(rbase, rlen);
1460 pmif->regbase = (unsigned long) base + 0x2000;
1461#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1462 pmif->dma_regs = base + 0x1000;
1463#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1464 pmif->kauai_fcr = base;
1465 pmif->irq = pdev->irq;
1466
1467 pci_set_drvdata(pdev, hwif);
1468
1469 rc = pmac_ide_setup_device(pmif, hwif);
1470 if (rc != 0) {
1471 /* The inteface is released to the common IDE layer */
1472 pci_set_drvdata(pdev, NULL);
1473 iounmap(base);
1474 memset(pmif, 0, sizeof(*pmif));
1475 pci_release_regions(pdev);
1476 }
1477
1478 return rc;
1479}
1480
1481static int
8b4b8a24 1482pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1da177e4
LT		 1483{
1484 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1485 int rc = 0;
1486
8b4b8a24
DB		 1487 if (mesg.event != pdev->dev.power.power_state.event
1488 && mesg.event == PM_EVENT_SUSPEND) {
1da177e4
LT		 1489 rc = pmac_ide_do_suspend(hwif);
1490 if (rc == 0)
8b4b8a24 1491 pdev->dev.power.power_state = mesg;
1da177e4
LT		 1492 }
1493
1494 return rc;
1495}
1496
1497static int
1498pmac_ide_pci_resume(struct pci_dev *pdev)
1499{
1500 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1501 int rc = 0;
1502
ca078bae 1503 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1da177e4
LT		 1504 rc = pmac_ide_do_resume(hwif);
1505 if (rc == 0)
829ca9a3 1506 pdev->dev.power.power_state = PMSG_ON;
1da177e4
LT		 1507 }
1508
1509 return rc;
1510}
1511
5e655772 1512static struct of_device_id pmac_ide_macio_match[] =
1da177e4
LT		 1513{
1514 {
1515 .name = "IDE",
1da177e4
LT		 1516 },
1517 {
1518 .name = "ATA",
1da177e4
LT		 1519 },
1520 {
1da177e4 1521 .type = "ide",
1da177e4
LT		 1522 },
1523 {
1da177e4 1524 .type = "ata",
1da177e4
LT		 1525 },
1526 {},
1527};
1528
1529static struct macio_driver pmac_ide_macio_driver =
1530{
1531 .name = "ide-pmac",
1532 .match_table = pmac_ide_macio_match,
1533 .probe = pmac_ide_macio_attach,
1534 .suspend = pmac_ide_macio_suspend,
1535 .resume = pmac_ide_macio_resume,
1536};
1537
1538static struct pci_device_id pmac_ide_pci_match[] = {
7fce260a
OJ		 1539 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1543 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1545 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
7fce260a
OJ		 1547 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 1549};
1550
1551static struct pci_driver pmac_ide_pci_driver = {
1552 .name = "ide-pmac",
1553 .id_table = pmac_ide_pci_match,
1554 .probe = pmac_ide_pci_attach,
1555 .suspend = pmac_ide_pci_suspend,
1556 .resume = pmac_ide_pci_resume,
1557};
1558MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1559
9e5755bc 1560int __init pmac_ide_probe(void)
1da177e4 1561{
9e5755bc
AM		 1562 int error;
1563
e8222502 1564 if (!machine_is(powermac))
9e5755bc 1565 return -ENODEV;
1da177e4
LT		 1566
1567#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
9e5755bc
AM		 1568 error = pci_register_driver(&pmac_ide_pci_driver);
1569 if (error)
1570 goto out;
1571 error = macio_register_driver(&pmac_ide_macio_driver);
1572 if (error) {
1573 pci_unregister_driver(&pmac_ide_pci_driver);
1574 goto out;
1575 }
1da177e4 1576#else
9e5755bc
AM		 1577 error = macio_register_driver(&pmac_ide_macio_driver);
1578 if (error)
1579 goto out;
1580 error = pci_register_driver(&pmac_ide_pci_driver);
1581 if (error) {
1582 macio_unregister_driver(&pmac_ide_macio_driver);
1583 goto out;
1584 }
1beb6a7d 1585#endif
9e5755bc
AM		 1586out:
1587 return error;
1da177e4
LT		 1588}
1589
1590#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1591
1592/*
1593 * pmac_ide_build_dmatable builds the DBDMA command list
1594 * for a transfer and sets the DBDMA channel to point to it.
1595 */
aacaf9bd 1596static int
1da177e4
LT		 1597pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1598{
1599 struct dbdma_cmd *table;
1600 int i, count = 0;
1601 ide_hwif_t *hwif = HWIF(drive);
1602 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1603 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1604 struct scatterlist *sg;
1605 int wr = (rq_data_dir(rq) == WRITE);
1606
1607 /* DMA table is already aligned */
1608 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1609
1610 /* Make sure DMA controller is stopped (necessary ?) */
1611 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1612 while (readl(&dma->status) & RUN)
1613 udelay(1);
1614
1615 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1616
1617 if (!i)
1618 return 0;
1619
1620 /* Build DBDMA commands list */
1621 sg = hwif->sg_table;
1622 while (i && sg_dma_len(sg)) {
1623 u32 cur_addr;
1624 u32 cur_len;
1625
1626 cur_addr = sg_dma_address(sg);
1627 cur_len = sg_dma_len(sg);
1628
1629 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1630 if (pmif->broken_dma_warn == 0) {
1631 printk(KERN_WARNING "%s: DMA on non aligned address,"
1632 "switching to PIO on Ohare chipset\n", drive->name);
1633 pmif->broken_dma_warn = 1;
1634 }
1635 goto use_pio_instead;
1636 }
1637 while (cur_len) {
1638 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1639
1640 if (count++ >= MAX_DCMDS) {
1641 printk(KERN_WARNING "%s: DMA table too small\n",
1642 drive->name);
1643 goto use_pio_instead;
1644 }
1645 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1646 st_le16(&table->req_count, tc);
1647 st_le32(&table->phy_addr, cur_addr);
1648 table->cmd_dep = 0;
1649 table->xfer_status = 0;
1650 table->res_count = 0;
1651 cur_addr += tc;
1652 cur_len -= tc;
1653 ++table;
1654 }
1655 sg++;
1656 i--;
1657 }
1658
1659 /* convert the last command to an input/output last command */
1660 if (count) {
1661 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1662 /* add the stop command to the end of the list */
1663 memset(table, 0, sizeof(struct dbdma_cmd));
1664 st_le16(&table->command, DBDMA_STOP);
1665 mb();
1666 writel(hwif->dmatable_dma, &dma->cmdptr);
1667 return 1;
1668 }
1669
1670 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1671 use_pio_instead:
1672 pci_unmap_sg(hwif->pci_dev,
1673 hwif->sg_table,
1674 hwif->sg_nents,
1675 hwif->sg_dma_direction);
1676 return 0; /* revert to PIO for this request */
1677}
1678
1679/* Teardown mappings after DMA has completed. */
aacaf9bd 1680static void
1da177e4
LT		 1681pmac_ide_destroy_dmatable (ide_drive_t *drive)
1682{
1683 ide_hwif_t *hwif = drive->hwif;
1684 struct pci_dev *dev = HWIF(drive)->pci_dev;
1685 struct scatterlist *sg = hwif->sg_table;
1686 int nents = hwif->sg_nents;
1687
1688 if (nents) {
1689 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1690 hwif->sg_nents = 0;
1691 }
1692}
1693
1694/*
1695 * Pick up best MDMA timing for the drive and apply it
1696 */
aacaf9bd 1697static int
1da177e4
LT		 1698pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1699{
1700 ide_hwif_t *hwif = HWIF(drive);
1701 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1702 int drive_cycle_time;
1703 struct hd_driveid *id = drive->id;
1704 u32 *timings, *timings2;
1705 u32 timing_local[2];
1706 int ret;
1707
1708 /* which drive is it ? */
1709 timings = &pmif->timings[drive->select.b.unit & 0x01];
1710 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1711
1712 /* Check if drive provide explicit cycle time */
1713 if ((id->field_valid & 2) && (id->eide_dma_time))
1714 drive_cycle_time = id->eide_dma_time;
1715 else
1716 drive_cycle_time = 0;
1717
1718 /* Copy timings to local image */
1719 timing_local[0] = *timings;
1720 timing_local[1] = *timings2;
1721
1722 /* Calculate controller timings */
1723 ret = set_timings_mdma( drive, pmif->kind,
1724 &timing_local[0],
1725 &timing_local[1],
1726 mode,
1727 drive_cycle_time);
1728 if (ret)
1729 return 0;
1730
1731 /* Set feature on drive */
1732 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1733 ret = pmac_ide_do_setfeature(drive, mode);
1734 if (ret) {
1735 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1736 return 0;
1737 }
1738
1739 /* Apply timings to controller */
1740 *timings = timing_local[0];
1741 *timings2 = timing_local[1];
1da177e4
LT		 1742
1743 return 1;
1744}
1745
1746/*
1747 * Pick up best UDMA timing for the drive and apply it
1748 */
aacaf9bd 1749static int
1da177e4
LT		 1750pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1751{
1752 ide_hwif_t *hwif = HWIF(drive);
1753 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1754 u32 *timings, *timings2;
1755 u32 timing_local[2];
1756 int ret;
1757
1758 /* which drive is it ? */
1759 timings = &pmif->timings[drive->select.b.unit & 0x01];
1760 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1761
1762 /* Copy timings to local image */
1763 timing_local[0] = *timings;
1764 timing_local[1] = *timings2;
1765
1766 /* Calculate timings for interface */
1767 if (pmif->kind == controller_un_ata6
1768 || pmif->kind == controller_k2_ata6)
1769 ret = set_timings_udma_ata6( &timing_local[0],
1770 &timing_local[1],
1771 mode);
1772 else if (pmif->kind == controller_sh_ata6)
1773 ret = set_timings_udma_shasta( &timing_local[0],
1774 &timing_local[1],
1775 mode);
1776 else
1777 ret = set_timings_udma_ata4(&timing_local[0], mode);
1778 if (ret)
1779 return 0;
1780
1781 /* Set feature on drive */
1782 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1783 ret = pmac_ide_do_setfeature(drive, mode);
1784 if (ret) {
1785 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1786 return 0;
1787 }
1788
1789 /* Apply timings to controller */
1790 *timings = timing_local[0];
1791 *timings2 = timing_local[1];
1792
1da177e4
LT		 1793 return 1;
1794}
1795
1796/*
1797 * Check what is the best DMA timing setting for the drive and
1798 * call appropriate functions to apply it.
1799 */
aacaf9bd 1800static int
1da177e4
LT		 1801pmac_ide_dma_check(ide_drive_t *drive)
1802{
1803 struct hd_driveid *id = drive->id;
1804 ide_hwif_t *hwif = HWIF(drive);
1da177e4 1805 int enable = 1;
1da177e4
LT		 1806 drive->using_dma = 0;
1807
1808 if (drive->media == ide_floppy)
1809 enable = 0;
1810 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1811 enable = 0;
1812 if (__ide_dma_bad_drive(drive))
1813 enable = 0;
1814
1815 if (enable) {
75b1d975
BZ		 1816 u8 mode = ide_max_dma_mode(drive);
1817
1818 if (mode >= XFER_UDMA_0)
1da177e4 1819 drive->using_dma = pmac_ide_udma_enable(drive, mode);
75b1d975 1820 else if (mode >= XFER_MW_DMA_0)
1da177e4
LT		 1821 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1822 hwif->OUTB(0, IDE_CONTROL_REG);
1823 /* Apply settings to controller */
1824 pmac_ide_do_update_timings(drive);
1825 }
1826 return 0;
1827}
1828
1829/*
1830 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1831 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1832 */
aacaf9bd 1833static int
1da177e4
LT		 1834pmac_ide_dma_setup(ide_drive_t *drive)
1835{
1836 ide_hwif_t *hwif = HWIF(drive);
1837 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1838 struct request *rq = HWGROUP(drive)->rq;
1839 u8 unit = (drive->select.b.unit & 0x01);
1840 u8 ata4;
1841
1842 if (pmif == NULL)
1843 return 1;
1844 ata4 = (pmif->kind == controller_kl_ata4);
1845
1846 if (!pmac_ide_build_dmatable(drive, rq)) {
1847 ide_map_sg(drive, rq);
1848 return 1;
1849 }
1850
1851 /* Apple adds 60ns to wrDataSetup on reads */
1852 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1853 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1854 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1855 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1856 }
1857
1858 drive->waiting_for_dma = 1;
1859
1860 return 0;
1861}
1862
aacaf9bd 1863static void
1da177e4
LT		 1864pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1865{
1866 /* issue cmd to drive */
1867 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1868}
1869
1870/*
1871 * Kick the DMA controller into life after the DMA command has been issued
1872 * to the drive.
1873 */
aacaf9bd 1874static void
1da177e4
LT		 1875pmac_ide_dma_start(ide_drive_t *drive)
1876{
1877 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1878 volatile struct dbdma_regs __iomem *dma;
1879
1880 dma = pmif->dma_regs;
1881
1882 writel((RUN << 16) | RUN, &dma->control);
1883 /* Make sure it gets to the controller right now */
1884 (void)readl(&dma->control);
1885}
1886
1887/*
1888 * After a DMA transfer, make sure the controller is stopped
1889 */
aacaf9bd 1890static int
1da177e4
LT		 1891pmac_ide_dma_end (ide_drive_t *drive)
1892{
1893 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1894 volatile struct dbdma_regs __iomem *dma;
1895 u32 dstat;
1896
1897 if (pmif == NULL)
1898 return 0;
1899 dma = pmif->dma_regs;
1900
1901 drive->waiting_for_dma = 0;
1902 dstat = readl(&dma->status);
1903 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1904 pmac_ide_destroy_dmatable(drive);
1905 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1906 * in theory, but with ATAPI decices doing buffer underruns, that would
1907 * cause us to disable DMA, which isn't what we want
1908 */
1909 return (dstat & (RUN|DEAD)) != RUN;
1910}
1911
1912/*
1913 * Check out that the interrupt we got was for us. We can't always know this
1914 * for sure with those Apple interfaces (well, we could on the recent ones but
1915 * that's not implemented yet), on the other hand, we don't have shared interrupts
1916 * so it's not really a problem
1917 */
aacaf9bd 1918static int
1da177e4
LT		 1919pmac_ide_dma_test_irq (ide_drive_t *drive)
1920{
1921 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1922 volatile struct dbdma_regs __iomem *dma;
1923 unsigned long status, timeout;
1924
1925 if (pmif == NULL)
1926 return 0;
1927 dma = pmif->dma_regs;
1928
1929 /* We have to things to deal with here:
1930 *
1931 * - The dbdma won't stop if the command was started
1932 * but completed with an error without transferring all
1933 * datas. This happens when bad blocks are met during
1934 * a multi-block transfer.
1935 *
1936 * - The dbdma fifo hasn't yet finished flushing to
1937 * to system memory when the disk interrupt occurs.
1938 *
1939 */
1940
1941 /* If ACTIVE is cleared, the STOP command have passed and
1942 * transfer is complete.
1943 */
1944 status = readl(&dma->status);
1945 if (!(status & ACTIVE))
1946 return 1;
1947 if (!drive->waiting_for_dma)
1948 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1949 called while not waiting\n", HWIF(drive)->index);
1950
1951 /* If dbdma didn't execute the STOP command yet, the
1952 * active bit is still set. We consider that we aren't
1953 * sharing interrupts (which is hopefully the case with
1954 * those controllers) and so we just try to flush the
1955 * channel for pending data in the fifo
1956 */
1957 udelay(1);
1958 writel((FLUSH << 16) | FLUSH, &dma->control);
1959 timeout = 0;
1960 for (;;) {
1961 udelay(1);
1962 status = readl(&dma->status);
1963 if ((status & FLUSH) == 0)
1964 break;
1965 if (++timeout > 100) {
1966 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1967 timeout flushing channel\n", HWIF(drive)->index);
1968 break;
1969 }
1970 }
1971 return 1;
1972}
1973
7469aaf6 1974static void pmac_ide_dma_host_off(ide_drive_t *drive)
1da177e4 1975{
1da177e4
LT		 1976}
1977
9e5755bc 1978static void pmac_ide_dma_host_on(ide_drive_t *drive)
1da177e4 1979{
1da177e4
LT		 1980}
1981
841d2a9b
SS		 1982static void
1983pmac_ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 1984{
1985 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1986 volatile struct dbdma_regs __iomem *dma;
1987 unsigned long status;
1988
1989 if (pmif == NULL)
841d2a9b 1990 return;
1da177e4
LT		 1991 dma = pmif->dma_regs;
1992
1993 status = readl(&dma->status);
1994 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1da177e4
LT		 1995}
1996
1997/*
1998 * Allocate the data structures needed for using DMA with an interface
1999 * and fill the proper list of functions pointers
2000 */
2001static void __init
2002pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2003{
2004 /* We won't need pci_dev if we switch to generic consistent
2005 * DMA routines ...
2006 */
2007 if (hwif->pci_dev == NULL)
2008 return;
2009 /*
2010 * Allocate space for the DBDMA commands.
2011 * The +2 is +1 for the stop command and +1 to allow for
2012 * aligning the start address to a multiple of 16 bytes.
2013 */
2014 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2015 hwif->pci_dev,
2016 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2017 &hwif->dmatable_dma);
2018 if (pmif->dma_table_cpu == NULL) {
2019 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2020 hwif->name);
2021 return;
2022 }
2023
7469aaf6 2024 hwif->dma_off_quietly = &ide_dma_off_quietly;
1da177e4
LT		 2025 hwif->ide_dma_on = &__ide_dma_on;
2026 hwif->ide_dma_check = &pmac_ide_dma_check;
2027 hwif->dma_setup = &pmac_ide_dma_setup;
2028 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2029 hwif->dma_start = &pmac_ide_dma_start;
2030 hwif->ide_dma_end = &pmac_ide_dma_end;
2031 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
7469aaf6 2032 hwif->dma_host_off = &pmac_ide_dma_host_off;
ccf35289 2033 hwif->dma_host_on = &pmac_ide_dma_host_on;
c283f5db 2034 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b 2035 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
1da177e4
LT		 2036
2037 hwif->atapi_dma = 1;
2038 switch(pmif->kind) {
2039 case controller_sh_ata6:
2040 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2041 hwif->mwdma_mask = 0x07;
2042 hwif->swdma_mask = 0x00;
2043 break;
2044 case controller_un_ata6:
2045 case controller_k2_ata6:
2046 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2047 hwif->mwdma_mask = 0x07;
2048 hwif->swdma_mask = 0x00;
2049 break;
2050 case controller_kl_ata4:
2051 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2052 hwif->mwdma_mask = 0x07;
2053 hwif->swdma_mask = 0x00;
2054 break;
2055 default:
2056 hwif->ultra_mask = 0x00;
2057 hwif->mwdma_mask = 0x07;
2058 hwif->swdma_mask = 0x00;
2059 break;
2060 }
2061}
2062
2063#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linux kernel - Deliverables
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