Commit | Line | Data |
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1da177e4 | 1 | /* |
f30c2269 | 2 | * linux/drivers/ide/ppc/pmac.c |
1da177e4 LT |
3 | * |
4 | * Support for IDE interfaces on PowerMacs. | |
5 | * These IDE interfaces are memory-mapped and have a DBDMA channel | |
6 | * for doing DMA. | |
7 | * | |
8 | * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt | |
c15d5d43 | 9 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * Some code taken from drivers/ide/ide-dma.c: | |
17 | * | |
18 | * Copyright (c) 1995-1998 Mark Lord | |
19 | * | |
20 | * TODO: - Use pre-calculated (kauai) timing tables all the time and | |
21 | * get rid of the "rounded" tables used previously, so we have the | |
22 | * same table format for all controllers and can then just have one | |
23 | * big table | |
24 | * | |
25 | */ | |
1da177e4 LT |
26 | #include <linux/types.h> |
27 | #include <linux/kernel.h> | |
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/delay.h> | |
30 | #include <linux/ide.h> | |
31 | #include <linux/notifier.h> | |
32 | #include <linux/reboot.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/adb.h> | |
35 | #include <linux/pmu.h> | |
36 | #include <linux/scatterlist.h> | |
37 | ||
38 | #include <asm/prom.h> | |
39 | #include <asm/io.h> | |
40 | #include <asm/dbdma.h> | |
41 | #include <asm/ide.h> | |
42 | #include <asm/pci-bridge.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/pmac_feature.h> | |
45 | #include <asm/sections.h> | |
46 | #include <asm/irq.h> | |
47 | ||
48 | #ifndef CONFIG_PPC64 | |
49 | #include <asm/mediabay.h> | |
50 | #endif | |
51 | ||
9e5755bc | 52 | #include "../ide-timing.h" |
1da177e4 LT |
53 | |
54 | #undef IDE_PMAC_DEBUG | |
55 | ||
56 | #define DMA_WAIT_TIMEOUT 50 | |
57 | ||
58 | typedef struct pmac_ide_hwif { | |
59 | unsigned long regbase; | |
60 | int irq; | |
61 | int kind; | |
62 | int aapl_bus_id; | |
63 | unsigned cable_80 : 1; | |
64 | unsigned mediabay : 1; | |
65 | unsigned broken_dma : 1; | |
66 | unsigned broken_dma_warn : 1; | |
67 | struct device_node* node; | |
68 | struct macio_dev *mdev; | |
69 | u32 timings[4]; | |
70 | volatile u32 __iomem * *kauai_fcr; | |
71 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
72 | /* Those fields are duplicating what is in hwif. We currently | |
73 | * can't use the hwif ones because of some assumptions that are | |
74 | * beeing done by the generic code about the kind of dma controller | |
75 | * and format of the dma table. This will have to be fixed though. | |
76 | */ | |
77 | volatile struct dbdma_regs __iomem * dma_regs; | |
78 | struct dbdma_cmd* dma_table_cpu; | |
79 | #endif | |
80 | ||
81 | } pmac_ide_hwif_t; | |
82 | ||
aacaf9bd | 83 | static pmac_ide_hwif_t pmac_ide[MAX_HWIFS]; |
1da177e4 LT |
84 | static int pmac_ide_count; |
85 | ||
86 | enum { | |
87 | controller_ohare, /* OHare based */ | |
88 | controller_heathrow, /* Heathrow/Paddington */ | |
89 | controller_kl_ata3, /* KeyLargo ATA-3 */ | |
90 | controller_kl_ata4, /* KeyLargo ATA-4 */ | |
91 | controller_un_ata6, /* UniNorth2 ATA-6 */ | |
92 | controller_k2_ata6, /* K2 ATA-6 */ | |
93 | controller_sh_ata6, /* Shasta ATA-6 */ | |
94 | }; | |
95 | ||
96 | static const char* model_name[] = { | |
97 | "OHare ATA", /* OHare based */ | |
98 | "Heathrow ATA", /* Heathrow/Paddington */ | |
99 | "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ | |
100 | "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ | |
101 | "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ | |
102 | "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ | |
103 | "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ | |
104 | }; | |
105 | ||
106 | /* | |
107 | * Extra registers, both 32-bit little-endian | |
108 | */ | |
109 | #define IDE_TIMING_CONFIG 0x200 | |
110 | #define IDE_INTERRUPT 0x300 | |
111 | ||
112 | /* Kauai (U2) ATA has different register setup */ | |
113 | #define IDE_KAUAI_PIO_CONFIG 0x200 | |
114 | #define IDE_KAUAI_ULTRA_CONFIG 0x210 | |
115 | #define IDE_KAUAI_POLL_CONFIG 0x220 | |
116 | ||
117 | /* | |
118 | * Timing configuration register definitions | |
119 | */ | |
120 | ||
121 | /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ | |
122 | #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) | |
123 | #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) | |
124 | #define IDE_SYSCLK_NS 30 /* 33Mhz cell */ | |
125 | #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ | |
126 | ||
127 | /* 133Mhz cell, found in shasta. | |
128 | * See comments about 100 Mhz Uninorth 2... | |
129 | * Note that PIO_MASK and MDMA_MASK seem to overlap | |
130 | */ | |
131 | #define TR_133_PIOREG_PIO_MASK 0xff000fff | |
132 | #define TR_133_PIOREG_MDMA_MASK 0x00fff800 | |
133 | #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff | |
134 | #define TR_133_UDMAREG_UDMA_EN 0x00000001 | |
135 | ||
136 | /* 100Mhz cell, found in Uninorth 2. I don't have much infos about | |
137 | * this one yet, it appears as a pci device (106b/0033) on uninorth | |
138 | * internal PCI bus and it's clock is controlled like gem or fw. It | |
139 | * appears to be an evolution of keylargo ATA4 with a timing register | |
140 | * extended to 2 32bits registers and a similar DBDMA channel. Other | |
141 | * registers seem to exist but I can't tell much about them. | |
142 | * | |
143 | * So far, I'm using pre-calculated tables for this extracted from | |
144 | * the values used by the MacOS X driver. | |
145 | * | |
146 | * The "PIO" register controls PIO and MDMA timings, the "ULTRA" | |
147 | * register controls the UDMA timings. At least, it seems bit 0 | |
148 | * of this one enables UDMA vs. MDMA, and bits 4..7 are the | |
149 | * cycle time in units of 10ns. Bits 8..15 are used by I don't | |
150 | * know their meaning yet | |
151 | */ | |
152 | #define TR_100_PIOREG_PIO_MASK 0xff000fff | |
153 | #define TR_100_PIOREG_MDMA_MASK 0x00fff000 | |
154 | #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff | |
155 | #define TR_100_UDMAREG_UDMA_EN 0x00000001 | |
156 | ||
157 | ||
158 | /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on | |
159 | * 40 connector cable and to 4 on 80 connector one. | |
160 | * Clock unit is 15ns (66Mhz) | |
161 | * | |
162 | * 3 Values can be programmed: | |
163 | * - Write data setup, which appears to match the cycle time. They | |
164 | * also call it DIOW setup. | |
165 | * - Ready to pause time (from spec) | |
166 | * - Address setup. That one is weird. I don't see where exactly | |
167 | * it fits in UDMA cycles, I got it's name from an obscure piece | |
168 | * of commented out code in Darwin. They leave it to 0, we do as | |
169 | * well, despite a comment that would lead to think it has a | |
170 | * min value of 45ns. | |
171 | * Apple also add 60ns to the write data setup (or cycle time ?) on | |
172 | * reads. | |
173 | */ | |
174 | #define TR_66_UDMA_MASK 0xfff00000 | |
175 | #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ | |
176 | #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */ | |
177 | #define TR_66_UDMA_ADDRSETUP_SHIFT 29 | |
178 | #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ | |
179 | #define TR_66_UDMA_RDY2PAUS_SHIFT 25 | |
180 | #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ | |
181 | #define TR_66_UDMA_WRDATASETUP_SHIFT 21 | |
182 | #define TR_66_MDMA_MASK 0x000ffc00 | |
183 | #define TR_66_MDMA_RECOVERY_MASK 0x000f8000 | |
184 | #define TR_66_MDMA_RECOVERY_SHIFT 15 | |
185 | #define TR_66_MDMA_ACCESS_MASK 0x00007c00 | |
186 | #define TR_66_MDMA_ACCESS_SHIFT 10 | |
187 | #define TR_66_PIO_MASK 0x000003ff | |
188 | #define TR_66_PIO_RECOVERY_MASK 0x000003e0 | |
189 | #define TR_66_PIO_RECOVERY_SHIFT 5 | |
190 | #define TR_66_PIO_ACCESS_MASK 0x0000001f | |
191 | #define TR_66_PIO_ACCESS_SHIFT 0 | |
192 | ||
193 | /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo | |
194 | * Can do pio & mdma modes, clock unit is 30ns (33Mhz) | |
195 | * | |
196 | * The access time and recovery time can be programmed. Some older | |
197 | * Darwin code base limit OHare to 150ns cycle time. I decided to do | |
198 | * the same here fore safety against broken old hardware ;) | |
199 | * The HalfTick bit, when set, adds half a clock (15ns) to the access | |
200 | * time and removes one from recovery. It's not supported on KeyLargo | |
201 | * implementation afaik. The E bit appears to be set for PIO mode 0 and | |
202 | * is used to reach long timings used in this mode. | |
203 | */ | |
204 | #define TR_33_MDMA_MASK 0x003ff800 | |
205 | #define TR_33_MDMA_RECOVERY_MASK 0x001f0000 | |
206 | #define TR_33_MDMA_RECOVERY_SHIFT 16 | |
207 | #define TR_33_MDMA_ACCESS_MASK 0x0000f800 | |
208 | #define TR_33_MDMA_ACCESS_SHIFT 11 | |
209 | #define TR_33_MDMA_HALFTICK 0x00200000 | |
210 | #define TR_33_PIO_MASK 0x000007ff | |
211 | #define TR_33_PIO_E 0x00000400 | |
212 | #define TR_33_PIO_RECOVERY_MASK 0x000003e0 | |
213 | #define TR_33_PIO_RECOVERY_SHIFT 5 | |
214 | #define TR_33_PIO_ACCESS_MASK 0x0000001f | |
215 | #define TR_33_PIO_ACCESS_SHIFT 0 | |
216 | ||
217 | /* | |
218 | * Interrupt register definitions | |
219 | */ | |
220 | #define IDE_INTR_DMA 0x80000000 | |
221 | #define IDE_INTR_DEVICE 0x40000000 | |
222 | ||
223 | /* | |
224 | * FCR Register on Kauai. Not sure what bit 0x4 is ... | |
225 | */ | |
226 | #define KAUAI_FCR_UATA_MAGIC 0x00000004 | |
227 | #define KAUAI_FCR_UATA_RESET_N 0x00000002 | |
228 | #define KAUAI_FCR_UATA_ENABLE 0x00000001 | |
229 | ||
230 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
231 | ||
232 | /* Rounded Multiword DMA timings | |
233 | * | |
234 | * I gave up finding a generic formula for all controller | |
235 | * types and instead, built tables based on timing values | |
236 | * used by Apple in Darwin's implementation. | |
237 | */ | |
238 | struct mdma_timings_t { | |
239 | int accessTime; | |
240 | int recoveryTime; | |
241 | int cycleTime; | |
242 | }; | |
243 | ||
aacaf9bd | 244 | struct mdma_timings_t mdma_timings_33[] = |
1da177e4 LT |
245 | { |
246 | { 240, 240, 480 }, | |
247 | { 180, 180, 360 }, | |
248 | { 135, 135, 270 }, | |
249 | { 120, 120, 240 }, | |
250 | { 105, 105, 210 }, | |
251 | { 90, 90, 180 }, | |
252 | { 75, 75, 150 }, | |
253 | { 75, 45, 120 }, | |
254 | { 0, 0, 0 } | |
255 | }; | |
256 | ||
aacaf9bd | 257 | struct mdma_timings_t mdma_timings_33k[] = |
1da177e4 LT |
258 | { |
259 | { 240, 240, 480 }, | |
260 | { 180, 180, 360 }, | |
261 | { 150, 150, 300 }, | |
262 | { 120, 120, 240 }, | |
263 | { 90, 120, 210 }, | |
264 | { 90, 90, 180 }, | |
265 | { 90, 60, 150 }, | |
266 | { 90, 30, 120 }, | |
267 | { 0, 0, 0 } | |
268 | }; | |
269 | ||
aacaf9bd | 270 | struct mdma_timings_t mdma_timings_66[] = |
1da177e4 LT |
271 | { |
272 | { 240, 240, 480 }, | |
273 | { 180, 180, 360 }, | |
274 | { 135, 135, 270 }, | |
275 | { 120, 120, 240 }, | |
276 | { 105, 105, 210 }, | |
277 | { 90, 90, 180 }, | |
278 | { 90, 75, 165 }, | |
279 | { 75, 45, 120 }, | |
280 | { 0, 0, 0 } | |
281 | }; | |
282 | ||
283 | /* KeyLargo ATA-4 Ultra DMA timings (rounded) */ | |
284 | struct { | |
285 | int addrSetup; /* ??? */ | |
286 | int rdy2pause; | |
287 | int wrDataSetup; | |
aacaf9bd | 288 | } kl66_udma_timings[] = |
1da177e4 LT |
289 | { |
290 | { 0, 180, 120 }, /* Mode 0 */ | |
291 | { 0, 150, 90 }, /* 1 */ | |
292 | { 0, 120, 60 }, /* 2 */ | |
293 | { 0, 90, 45 }, /* 3 */ | |
294 | { 0, 90, 30 } /* 4 */ | |
295 | }; | |
296 | ||
297 | /* UniNorth 2 ATA/100 timings */ | |
298 | struct kauai_timing { | |
299 | int cycle_time; | |
300 | u32 timing_reg; | |
301 | }; | |
302 | ||
aacaf9bd | 303 | static struct kauai_timing kauai_pio_timings[] = |
1da177e4 LT |
304 | { |
305 | { 930 , 0x08000fff }, | |
306 | { 600 , 0x08000a92 }, | |
307 | { 383 , 0x0800060f }, | |
308 | { 360 , 0x08000492 }, | |
309 | { 330 , 0x0800048f }, | |
310 | { 300 , 0x080003cf }, | |
311 | { 270 , 0x080003cc }, | |
312 | { 240 , 0x0800038b }, | |
313 | { 239 , 0x0800030c }, | |
314 | { 180 , 0x05000249 }, | |
c15d5d43 BZ |
315 | { 120 , 0x04000148 }, |
316 | { 0 , 0 }, | |
1da177e4 LT |
317 | }; |
318 | ||
aacaf9bd | 319 | static struct kauai_timing kauai_mdma_timings[] = |
1da177e4 LT |
320 | { |
321 | { 1260 , 0x00fff000 }, | |
322 | { 480 , 0x00618000 }, | |
323 | { 360 , 0x00492000 }, | |
324 | { 270 , 0x0038e000 }, | |
325 | { 240 , 0x0030c000 }, | |
326 | { 210 , 0x002cb000 }, | |
327 | { 180 , 0x00249000 }, | |
328 | { 150 , 0x00209000 }, | |
329 | { 120 , 0x00148000 }, | |
330 | { 0 , 0 }, | |
331 | }; | |
332 | ||
aacaf9bd | 333 | static struct kauai_timing kauai_udma_timings[] = |
1da177e4 LT |
334 | { |
335 | { 120 , 0x000070c0 }, | |
336 | { 90 , 0x00005d80 }, | |
337 | { 60 , 0x00004a60 }, | |
338 | { 45 , 0x00003a50 }, | |
339 | { 30 , 0x00002a30 }, | |
340 | { 20 , 0x00002921 }, | |
341 | { 0 , 0 }, | |
342 | }; | |
343 | ||
aacaf9bd | 344 | static struct kauai_timing shasta_pio_timings[] = |
1da177e4 LT |
345 | { |
346 | { 930 , 0x08000fff }, | |
347 | { 600 , 0x0A000c97 }, | |
348 | { 383 , 0x07000712 }, | |
349 | { 360 , 0x040003cd }, | |
350 | { 330 , 0x040003cd }, | |
351 | { 300 , 0x040003cd }, | |
352 | { 270 , 0x040003cd }, | |
353 | { 240 , 0x040003cd }, | |
354 | { 239 , 0x040003cd }, | |
355 | { 180 , 0x0400028b }, | |
c15d5d43 BZ |
356 | { 120 , 0x0400010a }, |
357 | { 0 , 0 }, | |
1da177e4 LT |
358 | }; |
359 | ||
aacaf9bd | 360 | static struct kauai_timing shasta_mdma_timings[] = |
1da177e4 LT |
361 | { |
362 | { 1260 , 0x00fff000 }, | |
363 | { 480 , 0x00820800 }, | |
364 | { 360 , 0x00820800 }, | |
365 | { 270 , 0x00820800 }, | |
366 | { 240 , 0x00820800 }, | |
367 | { 210 , 0x00820800 }, | |
368 | { 180 , 0x00820800 }, | |
369 | { 150 , 0x0028b000 }, | |
370 | { 120 , 0x001ca000 }, | |
371 | { 0 , 0 }, | |
372 | }; | |
373 | ||
aacaf9bd | 374 | static struct kauai_timing shasta_udma133_timings[] = |
1da177e4 LT |
375 | { |
376 | { 120 , 0x00035901, }, | |
377 | { 90 , 0x000348b1, }, | |
378 | { 60 , 0x00033881, }, | |
379 | { 45 , 0x00033861, }, | |
380 | { 30 , 0x00033841, }, | |
381 | { 20 , 0x00033031, }, | |
382 | { 15 , 0x00033021, }, | |
383 | { 0 , 0 }, | |
384 | }; | |
385 | ||
386 | ||
387 | static inline u32 | |
388 | kauai_lookup_timing(struct kauai_timing* table, int cycle_time) | |
389 | { | |
390 | int i; | |
391 | ||
392 | for (i=0; table[i].cycle_time; i++) | |
393 | if (cycle_time > table[i+1].cycle_time) | |
394 | return table[i].timing_reg; | |
90a87ea4 | 395 | BUG(); |
1da177e4 LT |
396 | return 0; |
397 | } | |
398 | ||
399 | /* allow up to 256 DBDMA commands per xfer */ | |
400 | #define MAX_DCMDS 256 | |
401 | ||
402 | /* | |
403 | * Wait 1s for disk to answer on IDE bus after a hard reset | |
404 | * of the device (via GPIO/FCR). | |
405 | * | |
406 | * Some devices seem to "pollute" the bus even after dropping | |
407 | * the BSY bit (typically some combo drives slave on the UDMA | |
408 | * bus) after a hard reset. Since we hard reset all drives on | |
409 | * KeyLargo ATA66, we have to keep that delay around. I may end | |
410 | * up not hard resetting anymore on these and keep the delay only | |
411 | * for older interfaces instead (we have to reset when coming | |
412 | * from MacOS...) --BenH. | |
413 | */ | |
414 | #define IDE_WAKEUP_DELAY (1*HZ) | |
415 | ||
416 | static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif); | |
417 | static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq); | |
1da177e4 LT |
418 | static void pmac_ide_selectproc(ide_drive_t *drive); |
419 | static void pmac_ide_kauai_selectproc(ide_drive_t *drive); | |
420 | ||
421 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
422 | ||
1da177e4 LT |
423 | /* |
424 | * N.B. this can't be an initfunc, because the media-bay task can | |
425 | * call ide_[un]register at any time. | |
426 | */ | |
aacaf9bd | 427 | void |
1da177e4 LT |
428 | pmac_ide_init_hwif_ports(hw_regs_t *hw, |
429 | unsigned long data_port, unsigned long ctrl_port, | |
430 | int *irq) | |
431 | { | |
432 | int i, ix; | |
433 | ||
434 | if (data_port == 0) | |
435 | return; | |
436 | ||
437 | for (ix = 0; ix < MAX_HWIFS; ++ix) | |
438 | if (data_port == pmac_ide[ix].regbase) | |
439 | break; | |
440 | ||
441 | if (ix >= MAX_HWIFS) { | |
442 | /* Probably a PCI interface... */ | |
443 | for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i) | |
444 | hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET; | |
445 | hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; | |
446 | return; | |
447 | } | |
448 | ||
449 | for (i = 0; i < 8; ++i) | |
450 | hw->io_ports[i] = data_port + i * 0x10; | |
451 | hw->io_ports[8] = data_port + 0x160; | |
452 | ||
453 | if (irq != NULL) | |
454 | *irq = pmac_ide[ix].irq; | |
22192ccd BH |
455 | |
456 | hw->dev = &pmac_ide[ix].mdev->ofdev.dev; | |
1da177e4 LT |
457 | } |
458 | ||
459 | #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x))) | |
460 | ||
461 | /* | |
462 | * Apply the timings of the proper unit (master/slave) to the shared | |
463 | * timing register when selecting that unit. This version is for | |
464 | * ASICs with a single timing register | |
465 | */ | |
aacaf9bd | 466 | static void |
1da177e4 LT |
467 | pmac_ide_selectproc(ide_drive_t *drive) |
468 | { | |
469 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
470 | ||
471 | if (pmif == NULL) | |
472 | return; | |
473 | ||
474 | if (drive->select.b.unit & 0x01) | |
475 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
476 | else | |
477 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
478 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
479 | } | |
480 | ||
481 | /* | |
482 | * Apply the timings of the proper unit (master/slave) to the shared | |
483 | * timing register when selecting that unit. This version is for | |
484 | * ASICs with a dual timing register (Kauai) | |
485 | */ | |
aacaf9bd | 486 | static void |
1da177e4 LT |
487 | pmac_ide_kauai_selectproc(ide_drive_t *drive) |
488 | { | |
489 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
490 | ||
491 | if (pmif == NULL) | |
492 | return; | |
493 | ||
494 | if (drive->select.b.unit & 0x01) { | |
495 | writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
496 | writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
497 | } else { | |
498 | writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
499 | writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG)); | |
500 | } | |
501 | (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG)); | |
502 | } | |
503 | ||
504 | /* | |
505 | * Force an update of controller timing values for a given drive | |
506 | */ | |
aacaf9bd | 507 | static void |
1da177e4 LT |
508 | pmac_ide_do_update_timings(ide_drive_t *drive) |
509 | { | |
510 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
511 | ||
512 | if (pmif == NULL) | |
513 | return; | |
514 | ||
515 | if (pmif->kind == controller_sh_ata6 || | |
516 | pmif->kind == controller_un_ata6 || | |
517 | pmif->kind == controller_k2_ata6) | |
518 | pmac_ide_kauai_selectproc(drive); | |
519 | else | |
520 | pmac_ide_selectproc(drive); | |
521 | } | |
522 | ||
523 | static void | |
524 | pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port) | |
525 | { | |
526 | u32 tmp; | |
527 | ||
528 | writeb(value, (void __iomem *) port); | |
529 | tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
530 | } | |
531 | ||
1da177e4 LT |
532 | /* |
533 | * Old tuning functions (called on hdparm -p), sets up drive PIO timings | |
534 | */ | |
aacaf9bd | 535 | static void |
26bcb879 | 536 | pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 537 | { |
0b46ff2e | 538 | u32 *timings, t; |
1da177e4 LT |
539 | unsigned accessTicks, recTicks; |
540 | unsigned accessTime, recTime; | |
541 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
7dd00083 BZ |
542 | unsigned int cycle_time; |
543 | ||
1da177e4 LT |
544 | if (pmif == NULL) |
545 | return; | |
546 | ||
547 | /* which drive is it ? */ | |
548 | timings = &pmif->timings[drive->select.b.unit & 0x01]; | |
0b46ff2e | 549 | t = *timings; |
1da177e4 | 550 | |
7dd00083 | 551 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 LT |
552 | |
553 | switch (pmif->kind) { | |
554 | case controller_sh_ata6: { | |
555 | /* 133Mhz cell */ | |
7dd00083 | 556 | u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time); |
0b46ff2e | 557 | t = (t & ~TR_133_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
558 | break; |
559 | } | |
560 | case controller_un_ata6: | |
561 | case controller_k2_ata6: { | |
562 | /* 100Mhz cell */ | |
7dd00083 | 563 | u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time); |
0b46ff2e | 564 | t = (t & ~TR_100_PIOREG_PIO_MASK) | tr; |
1da177e4 LT |
565 | break; |
566 | } | |
567 | case controller_kl_ata4: | |
568 | /* 66Mhz cell */ | |
7dd00083 | 569 | recTime = cycle_time - ide_pio_timings[pio].active_time |
1da177e4 LT |
570 | - ide_pio_timings[pio].setup_time; |
571 | recTime = max(recTime, 150U); | |
572 | accessTime = ide_pio_timings[pio].active_time; | |
573 | accessTime = max(accessTime, 150U); | |
574 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
575 | accessTicks = min(accessTicks, 0x1fU); | |
576 | recTicks = SYSCLK_TICKS_66(recTime); | |
577 | recTicks = min(recTicks, 0x1fU); | |
0b46ff2e BH |
578 | t = (t & ~TR_66_PIO_MASK) | |
579 | (accessTicks << TR_66_PIO_ACCESS_SHIFT) | | |
580 | (recTicks << TR_66_PIO_RECOVERY_SHIFT); | |
1da177e4 LT |
581 | break; |
582 | default: { | |
583 | /* 33Mhz cell */ | |
584 | int ebit = 0; | |
7dd00083 | 585 | recTime = cycle_time - ide_pio_timings[pio].active_time |
1da177e4 LT |
586 | - ide_pio_timings[pio].setup_time; |
587 | recTime = max(recTime, 150U); | |
588 | accessTime = ide_pio_timings[pio].active_time; | |
589 | accessTime = max(accessTime, 150U); | |
590 | accessTicks = SYSCLK_TICKS(accessTime); | |
591 | accessTicks = min(accessTicks, 0x1fU); | |
592 | accessTicks = max(accessTicks, 4U); | |
593 | recTicks = SYSCLK_TICKS(recTime); | |
594 | recTicks = min(recTicks, 0x1fU); | |
595 | recTicks = max(recTicks, 5U) - 4; | |
596 | if (recTicks > 9) { | |
597 | recTicks--; /* guess, but it's only for PIO0, so... */ | |
598 | ebit = 1; | |
599 | } | |
0b46ff2e | 600 | t = (t & ~TR_33_PIO_MASK) | |
1da177e4 LT |
601 | (accessTicks << TR_33_PIO_ACCESS_SHIFT) | |
602 | (recTicks << TR_33_PIO_RECOVERY_SHIFT); | |
603 | if (ebit) | |
0b46ff2e | 604 | t |= TR_33_PIO_E; |
1da177e4 LT |
605 | break; |
606 | } | |
607 | } | |
608 | ||
609 | #ifdef IDE_PMAC_DEBUG | |
610 | printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", | |
611 | drive->name, pio, *timings); | |
612 | #endif | |
613 | ||
aedea591 | 614 | if (ide_config_drive_speed(drive, XFER_PIO_0 + pio)) |
c15d5d43 BZ |
615 | return; |
616 | ||
0b46ff2e | 617 | *timings = t; |
c15d5d43 | 618 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
619 | } |
620 | ||
621 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
622 | ||
623 | /* | |
624 | * Calculate KeyLargo ATA/66 UDMA timings | |
625 | */ | |
aacaf9bd | 626 | static int |
1da177e4 LT |
627 | set_timings_udma_ata4(u32 *timings, u8 speed) |
628 | { | |
629 | unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; | |
630 | ||
631 | if (speed > XFER_UDMA_4) | |
632 | return 1; | |
633 | ||
634 | rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause); | |
635 | wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup); | |
636 | addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup); | |
637 | ||
638 | *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) | | |
639 | (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | | |
640 | (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) | | |
641 | (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) | | |
642 | TR_66_UDMA_EN; | |
643 | #ifdef IDE_PMAC_DEBUG | |
644 | printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", | |
645 | speed & 0xf, *timings); | |
646 | #endif | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /* | |
652 | * Calculate Kauai ATA/100 UDMA timings | |
653 | */ | |
aacaf9bd | 654 | static int |
1da177e4 LT |
655 | set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
656 | { | |
657 | struct ide_timing *t = ide_timing_find_mode(speed); | |
658 | u32 tr; | |
659 | ||
660 | if (speed > XFER_UDMA_5 || t == NULL) | |
661 | return 1; | |
662 | tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma); | |
1da177e4 LT |
663 | *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr; |
664 | *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN; | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | /* | |
670 | * Calculate Shasta ATA/133 UDMA timings | |
671 | */ | |
aacaf9bd | 672 | static int |
1da177e4 LT |
673 | set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) |
674 | { | |
675 | struct ide_timing *t = ide_timing_find_mode(speed); | |
676 | u32 tr; | |
677 | ||
678 | if (speed > XFER_UDMA_6 || t == NULL) | |
679 | return 1; | |
680 | tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma); | |
1da177e4 LT |
681 | *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr; |
682 | *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN; | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | /* | |
688 | * Calculate MDMA timings for all cells | |
689 | */ | |
90f72eca | 690 | static void |
1da177e4 | 691 | set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, |
90f72eca | 692 | u8 speed) |
1da177e4 LT |
693 | { |
694 | int cycleTime, accessTime = 0, recTime = 0; | |
695 | unsigned accessTicks, recTicks; | |
90f72eca | 696 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
697 | struct mdma_timings_t* tm = NULL; |
698 | int i; | |
699 | ||
700 | /* Get default cycle time for mode */ | |
701 | switch(speed & 0xf) { | |
702 | case 0: cycleTime = 480; break; | |
703 | case 1: cycleTime = 150; break; | |
704 | case 2: cycleTime = 120; break; | |
705 | default: | |
90f72eca BZ |
706 | BUG(); |
707 | break; | |
1da177e4 | 708 | } |
90f72eca BZ |
709 | |
710 | /* Check if drive provides explicit DMA cycle time */ | |
711 | if ((id->field_valid & 2) && id->eide_dma_time) | |
712 | cycleTime = max_t(int, id->eide_dma_time, cycleTime); | |
713 | ||
1da177e4 LT |
714 | /* OHare limits according to some old Apple sources */ |
715 | if ((intf_type == controller_ohare) && (cycleTime < 150)) | |
716 | cycleTime = 150; | |
717 | /* Get the proper timing array for this controller */ | |
718 | switch(intf_type) { | |
719 | case controller_sh_ata6: | |
720 | case controller_un_ata6: | |
721 | case controller_k2_ata6: | |
722 | break; | |
723 | case controller_kl_ata4: | |
724 | tm = mdma_timings_66; | |
725 | break; | |
726 | case controller_kl_ata3: | |
727 | tm = mdma_timings_33k; | |
728 | break; | |
729 | default: | |
730 | tm = mdma_timings_33; | |
731 | break; | |
732 | } | |
733 | if (tm != NULL) { | |
734 | /* Lookup matching access & recovery times */ | |
735 | i = -1; | |
736 | for (;;) { | |
737 | if (tm[i+1].cycleTime < cycleTime) | |
738 | break; | |
739 | i++; | |
740 | } | |
1da177e4 LT |
741 | cycleTime = tm[i].cycleTime; |
742 | accessTime = tm[i].accessTime; | |
743 | recTime = tm[i].recoveryTime; | |
744 | ||
745 | #ifdef IDE_PMAC_DEBUG | |
746 | printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", | |
747 | drive->name, cycleTime, accessTime, recTime); | |
748 | #endif | |
749 | } | |
750 | switch(intf_type) { | |
751 | case controller_sh_ata6: { | |
752 | /* 133Mhz cell */ | |
753 | u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime); | |
1da177e4 LT |
754 | *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr; |
755 | *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN; | |
756 | } | |
757 | case controller_un_ata6: | |
758 | case controller_k2_ata6: { | |
759 | /* 100Mhz cell */ | |
760 | u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime); | |
1da177e4 LT |
761 | *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr; |
762 | *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN; | |
763 | } | |
764 | break; | |
765 | case controller_kl_ata4: | |
766 | /* 66Mhz cell */ | |
767 | accessTicks = SYSCLK_TICKS_66(accessTime); | |
768 | accessTicks = min(accessTicks, 0x1fU); | |
769 | accessTicks = max(accessTicks, 0x1U); | |
770 | recTicks = SYSCLK_TICKS_66(recTime); | |
771 | recTicks = min(recTicks, 0x1fU); | |
772 | recTicks = max(recTicks, 0x3U); | |
773 | /* Clear out mdma bits and disable udma */ | |
774 | *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) | | |
775 | (accessTicks << TR_66_MDMA_ACCESS_SHIFT) | | |
776 | (recTicks << TR_66_MDMA_RECOVERY_SHIFT); | |
777 | break; | |
778 | case controller_kl_ata3: | |
779 | /* 33Mhz cell on KeyLargo */ | |
780 | accessTicks = SYSCLK_TICKS(accessTime); | |
781 | accessTicks = max(accessTicks, 1U); | |
782 | accessTicks = min(accessTicks, 0x1fU); | |
783 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
784 | recTicks = SYSCLK_TICKS(recTime); | |
785 | recTicks = max(recTicks, 1U); | |
786 | recTicks = min(recTicks, 0x1fU); | |
787 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
788 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
789 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
790 | break; | |
791 | default: { | |
792 | /* 33Mhz cell on others */ | |
793 | int halfTick = 0; | |
794 | int origAccessTime = accessTime; | |
795 | int origRecTime = recTime; | |
796 | ||
797 | accessTicks = SYSCLK_TICKS(accessTime); | |
798 | accessTicks = max(accessTicks, 1U); | |
799 | accessTicks = min(accessTicks, 0x1fU); | |
800 | accessTime = accessTicks * IDE_SYSCLK_NS; | |
801 | recTicks = SYSCLK_TICKS(recTime); | |
802 | recTicks = max(recTicks, 2U) - 1; | |
803 | recTicks = min(recTicks, 0x1fU); | |
804 | recTime = (recTicks + 1) * IDE_SYSCLK_NS; | |
805 | if ((accessTicks > 1) && | |
806 | ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) && | |
807 | ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) { | |
808 | halfTick = 1; | |
809 | accessTicks--; | |
810 | } | |
811 | *timings = ((*timings) & ~TR_33_MDMA_MASK) | | |
812 | (accessTicks << TR_33_MDMA_ACCESS_SHIFT) | | |
813 | (recTicks << TR_33_MDMA_RECOVERY_SHIFT); | |
814 | if (halfTick) | |
815 | *timings |= TR_33_MDMA_HALFTICK; | |
816 | } | |
817 | } | |
818 | #ifdef IDE_PMAC_DEBUG | |
819 | printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", | |
820 | drive->name, speed & 0xf, *timings); | |
821 | #endif | |
1da177e4 LT |
822 | } |
823 | #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
824 | ||
825 | /* | |
826 | * Speedproc. This function is called by the core to set any of the standard | |
8f4dd2e4 | 827 | * DMA timing (MDMA or UDMA) to both the drive and the controller. |
1da177e4 | 828 | */ |
f212ff28 | 829 | static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
830 | { |
831 | int unit = (drive->select.b.unit & 0x01); | |
832 | int ret = 0; | |
833 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
085798b1 | 834 | u32 *timings, *timings2, tl[2]; |
1da177e4 | 835 | |
1da177e4 LT |
836 | timings = &pmif->timings[unit]; |
837 | timings2 = &pmif->timings[unit+2]; | |
085798b1 BZ |
838 | |
839 | /* Copy timings to local image */ | |
840 | tl[0] = *timings; | |
841 | tl[1] = *timings2; | |
842 | ||
1da177e4 LT |
843 | switch(speed) { |
844 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
845 | case XFER_UDMA_6: | |
1da177e4 | 846 | case XFER_UDMA_5: |
1da177e4 LT |
847 | case XFER_UDMA_4: |
848 | case XFER_UDMA_3: | |
1da177e4 LT |
849 | case XFER_UDMA_2: |
850 | case XFER_UDMA_1: | |
851 | case XFER_UDMA_0: | |
852 | if (pmif->kind == controller_kl_ata4) | |
085798b1 | 853 | ret = set_timings_udma_ata4(&tl[0], speed); |
1da177e4 LT |
854 | else if (pmif->kind == controller_un_ata6 |
855 | || pmif->kind == controller_k2_ata6) | |
085798b1 | 856 | ret = set_timings_udma_ata6(&tl[0], &tl[1], speed); |
1da177e4 | 857 | else if (pmif->kind == controller_sh_ata6) |
085798b1 | 858 | ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); |
1da177e4 | 859 | else |
085798b1 | 860 | ret = 1; |
1da177e4 LT |
861 | break; |
862 | case XFER_MW_DMA_2: | |
863 | case XFER_MW_DMA_1: | |
864 | case XFER_MW_DMA_0: | |
90f72eca | 865 | set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); |
1da177e4 LT |
866 | break; |
867 | case XFER_SW_DMA_2: | |
868 | case XFER_SW_DMA_1: | |
869 | case XFER_SW_DMA_0: | |
870 | return 1; | |
871 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1da177e4 LT |
872 | default: |
873 | ret = 1; | |
874 | } | |
875 | if (ret) | |
876 | return ret; | |
877 | ||
aedea591 | 878 | ret = ide_config_drive_speed(drive, speed); |
1da177e4 LT |
879 | if (ret) |
880 | return ret; | |
085798b1 BZ |
881 | |
882 | /* Apply timings to controller */ | |
883 | *timings = tl[0]; | |
884 | *timings2 = tl[1]; | |
885 | ||
1da177e4 | 886 | pmac_ide_do_update_timings(drive); |
1da177e4 LT |
887 | |
888 | return 0; | |
889 | } | |
890 | ||
891 | /* | |
892 | * Blast some well known "safe" values to the timing registers at init or | |
893 | * wakeup from sleep time, before we do real calculation | |
894 | */ | |
aacaf9bd | 895 | static void |
1da177e4 LT |
896 | sanitize_timings(pmac_ide_hwif_t *pmif) |
897 | { | |
898 | unsigned int value, value2 = 0; | |
899 | ||
900 | switch(pmif->kind) { | |
901 | case controller_sh_ata6: | |
902 | value = 0x0a820c97; | |
903 | value2 = 0x00033031; | |
904 | break; | |
905 | case controller_un_ata6: | |
906 | case controller_k2_ata6: | |
907 | value = 0x08618a92; | |
908 | value2 = 0x00002921; | |
909 | break; | |
910 | case controller_kl_ata4: | |
911 | value = 0x0008438c; | |
912 | break; | |
913 | case controller_kl_ata3: | |
914 | value = 0x00084526; | |
915 | break; | |
916 | case controller_heathrow: | |
917 | case controller_ohare: | |
918 | default: | |
919 | value = 0x00074526; | |
920 | break; | |
921 | } | |
922 | pmif->timings[0] = pmif->timings[1] = value; | |
923 | pmif->timings[2] = pmif->timings[3] = value2; | |
924 | } | |
925 | ||
aacaf9bd | 926 | unsigned long |
1da177e4 LT |
927 | pmac_ide_get_base(int index) |
928 | { | |
929 | return pmac_ide[index].regbase; | |
930 | } | |
931 | ||
aacaf9bd | 932 | int |
1da177e4 LT |
933 | pmac_ide_check_base(unsigned long base) |
934 | { | |
935 | int ix; | |
936 | ||
937 | for (ix = 0; ix < MAX_HWIFS; ++ix) | |
938 | if (base == pmac_ide[ix].regbase) | |
939 | return ix; | |
940 | return -1; | |
941 | } | |
942 | ||
aacaf9bd | 943 | int |
1da177e4 LT |
944 | pmac_ide_get_irq(unsigned long base) |
945 | { | |
946 | int ix; | |
947 | ||
948 | for (ix = 0; ix < MAX_HWIFS; ++ix) | |
949 | if (base == pmac_ide[ix].regbase) | |
950 | return pmac_ide[ix].irq; | |
951 | return 0; | |
952 | } | |
953 | ||
aacaf9bd | 954 | static int ide_majors[] = { 3, 22, 33, 34, 56, 57 }; |
1da177e4 LT |
955 | |
956 | dev_t __init | |
957 | pmac_find_ide_boot(char *bootdevice, int n) | |
958 | { | |
959 | int i; | |
960 | ||
961 | /* | |
962 | * Look through the list of IDE interfaces for this one. | |
963 | */ | |
964 | for (i = 0; i < pmac_ide_count; ++i) { | |
965 | char *name; | |
966 | if (!pmac_ide[i].node || !pmac_ide[i].node->full_name) | |
967 | continue; | |
968 | name = pmac_ide[i].node->full_name; | |
969 | if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) { | |
970 | /* XXX should cope with the 2nd drive as well... */ | |
971 | return MKDEV(ide_majors[i], 0); | |
972 | } | |
973 | } | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | /* Suspend call back, should be called after the child devices | |
979 | * have actually been suspended | |
980 | */ | |
981 | static int | |
982 | pmac_ide_do_suspend(ide_hwif_t *hwif) | |
983 | { | |
984 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
985 | ||
986 | /* We clear the timings */ | |
987 | pmif->timings[0] = 0; | |
988 | pmif->timings[1] = 0; | |
989 | ||
616299af BH |
990 | disable_irq(pmif->irq); |
991 | ||
1da177e4 LT |
992 | /* The media bay will handle itself just fine */ |
993 | if (pmif->mediabay) | |
994 | return 0; | |
995 | ||
996 | /* Kauai has bus control FCRs directly here */ | |
997 | if (pmif->kauai_fcr) { | |
998 | u32 fcr = readl(pmif->kauai_fcr); | |
999 | fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); | |
1000 | writel(fcr, pmif->kauai_fcr); | |
1001 | } | |
1002 | ||
1003 | /* Disable the bus on older machines and the cell on kauai */ | |
1004 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, | |
1005 | 0); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | /* Resume call back, should be called before the child devices | |
1011 | * are resumed | |
1012 | */ | |
1013 | static int | |
1014 | pmac_ide_do_resume(ide_hwif_t *hwif) | |
1015 | { | |
1016 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
1017 | ||
1018 | /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ | |
1019 | if (!pmif->mediabay) { | |
1020 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); | |
1021 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); | |
1022 | msleep(10); | |
1023 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0); | |
1da177e4 LT |
1024 | |
1025 | /* Kauai has it different */ | |
1026 | if (pmif->kauai_fcr) { | |
1027 | u32 fcr = readl(pmif->kauai_fcr); | |
1028 | fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; | |
1029 | writel(fcr, pmif->kauai_fcr); | |
1030 | } | |
616299af BH |
1031 | |
1032 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1da177e4 LT |
1033 | } |
1034 | ||
1035 | /* Sanitize drive timings */ | |
1036 | sanitize_timings(pmif); | |
1037 | ||
616299af BH |
1038 | enable_irq(pmif->irq); |
1039 | ||
1da177e4 LT |
1040 | return 0; |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Setup, register & probe an IDE channel driven by this driver, this is | |
1045 | * called by one of the 2 probe functions (macio or PCI). Note that a channel | |
1046 | * that ends up beeing free of any device is not kept around by this driver | |
1047 | * (it is kept in 2.4). This introduce an interface numbering change on some | |
1048 | * rare machines unfortunately, but it's better this way. | |
1049 | */ | |
1050 | static int | |
1051 | pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif) | |
1052 | { | |
1053 | struct device_node *np = pmif->node; | |
018a3d1d | 1054 | const int *bidp; |
1da177e4 LT |
1055 | |
1056 | pmif->cable_80 = 0; | |
1057 | pmif->broken_dma = pmif->broken_dma_warn = 0; | |
55b61fec | 1058 | if (of_device_is_compatible(np, "shasta-ata")) |
1da177e4 | 1059 | pmif->kind = controller_sh_ata6; |
55b61fec | 1060 | else if (of_device_is_compatible(np, "kauai-ata")) |
1da177e4 | 1061 | pmif->kind = controller_un_ata6; |
55b61fec | 1062 | else if (of_device_is_compatible(np, "K2-UATA")) |
1da177e4 | 1063 | pmif->kind = controller_k2_ata6; |
55b61fec | 1064 | else if (of_device_is_compatible(np, "keylargo-ata")) { |
1da177e4 LT |
1065 | if (strcmp(np->name, "ata-4") == 0) |
1066 | pmif->kind = controller_kl_ata4; | |
1067 | else | |
1068 | pmif->kind = controller_kl_ata3; | |
55b61fec | 1069 | } else if (of_device_is_compatible(np, "heathrow-ata")) |
1da177e4 LT |
1070 | pmif->kind = controller_heathrow; |
1071 | else { | |
1072 | pmif->kind = controller_ohare; | |
1073 | pmif->broken_dma = 1; | |
1074 | } | |
1075 | ||
40cd3a45 | 1076 | bidp = of_get_property(np, "AAPL,bus-id", NULL); |
1da177e4 LT |
1077 | pmif->aapl_bus_id = bidp ? *bidp : 0; |
1078 | ||
1079 | /* Get cable type from device-tree */ | |
1080 | if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6 | |
1081 | || pmif->kind == controller_k2_ata6 | |
1082 | || pmif->kind == controller_sh_ata6) { | |
40cd3a45 | 1083 | const char* cable = of_get_property(np, "cable-type", NULL); |
1da177e4 LT |
1084 | if (cable && !strncmp(cable, "80-", 3)) |
1085 | pmif->cable_80 = 1; | |
1086 | } | |
1087 | /* G5's seem to have incorrect cable type in device-tree. Let's assume | |
1088 | * they have a 80 conductor cable, this seem to be always the case unless | |
1089 | * the user mucked around | |
1090 | */ | |
55b61fec SR |
1091 | if (of_device_is_compatible(np, "K2-UATA") || |
1092 | of_device_is_compatible(np, "shasta-ata")) | |
1da177e4 LT |
1093 | pmif->cable_80 = 1; |
1094 | ||
1095 | /* On Kauai-type controllers, we make sure the FCR is correct */ | |
1096 | if (pmif->kauai_fcr) | |
1097 | writel(KAUAI_FCR_UATA_MAGIC | | |
1098 | KAUAI_FCR_UATA_RESET_N | | |
1099 | KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); | |
1100 | ||
1101 | pmif->mediabay = 0; | |
1102 | ||
1103 | /* Make sure we have sane timings */ | |
1104 | sanitize_timings(pmif); | |
1105 | ||
1106 | #ifndef CONFIG_PPC64 | |
1107 | /* XXX FIXME: Media bay stuff need re-organizing */ | |
1108 | if (np->parent && np->parent->name | |
1109 | && strcasecmp(np->parent->name, "media-bay") == 0) { | |
8c870933 | 1110 | #ifdef CONFIG_PMAC_MEDIABAY |
1da177e4 | 1111 | media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index); |
8c870933 | 1112 | #endif /* CONFIG_PMAC_MEDIABAY */ |
1da177e4 LT |
1113 | pmif->mediabay = 1; |
1114 | if (!bidp) | |
1115 | pmif->aapl_bus_id = 1; | |
1116 | } else if (pmif->kind == controller_ohare) { | |
1117 | /* The code below is having trouble on some ohare machines | |
1118 | * (timing related ?). Until I can put my hand on one of these | |
1119 | * units, I keep the old way | |
1120 | */ | |
1121 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); | |
1122 | } else | |
1123 | #endif | |
1124 | { | |
1125 | /* This is necessary to enable IDE when net-booting */ | |
1126 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); | |
1127 | ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); | |
1128 | msleep(10); | |
1129 | ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0); | |
1130 | msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY)); | |
1131 | } | |
1132 | ||
1133 | /* Setup MMIO ops */ | |
1134 | default_hwif_mmiops(hwif); | |
1135 | hwif->OUTBSYNC = pmac_outbsync; | |
1136 | ||
1137 | /* Tell common code _not_ to mess with resources */ | |
2ad1e558 | 1138 | hwif->mmio = 1; |
1da177e4 LT |
1139 | hwif->hwif_data = pmif; |
1140 | pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq); | |
1141 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); | |
1142 | hwif->chipset = ide_pmac; | |
1143 | hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay; | |
1144 | hwif->hold = pmif->mediabay; | |
49521f97 | 1145 | hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
1146 | hwif->drives[0].unmask = 1; |
1147 | hwif->drives[1].unmask = 1; | |
0b46ff2e BH |
1148 | hwif->drives[0].autotune = IDE_TUNE_AUTO; |
1149 | hwif->drives[1].autotune = IDE_TUNE_AUTO; | |
aedea591 | 1150 | hwif->host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA; |
4099d143 | 1151 | hwif->pio_mask = ATA_PIO4; |
26bcb879 | 1152 | hwif->set_pio_mode = pmac_ide_set_pio_mode; |
1da177e4 LT |
1153 | if (pmif->kind == controller_un_ata6 |
1154 | || pmif->kind == controller_k2_ata6 | |
1155 | || pmif->kind == controller_sh_ata6) | |
1156 | hwif->selectproc = pmac_ide_kauai_selectproc; | |
1157 | else | |
1158 | hwif->selectproc = pmac_ide_selectproc; | |
1159 | hwif->speedproc = pmac_ide_tune_chipset; | |
1160 | ||
1da177e4 LT |
1161 | printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", |
1162 | hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, | |
1163 | pmif->mediabay ? " (mediabay)" : "", hwif->irq); | |
1164 | ||
8c870933 | 1165 | #ifdef CONFIG_PMAC_MEDIABAY |
1da177e4 LT |
1166 | if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0) |
1167 | hwif->noprobe = 0; | |
8c870933 | 1168 | #endif /* CONFIG_PMAC_MEDIABAY */ |
1da177e4 LT |
1169 | |
1170 | hwif->sg_max_nents = MAX_DCMDS; | |
1171 | ||
1172 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1173 | /* has a DBDMA controller channel */ | |
1174 | if (pmif->dma_regs) | |
1175 | pmac_ide_setup_dma(pmif, hwif); | |
1176 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1177 | ||
1178 | /* We probe the hwif now */ | |
1179 | probe_hwif_init(hwif); | |
1180 | ||
5cbf79cd BZ |
1181 | ide_proc_register_port(hwif); |
1182 | ||
1da177e4 LT |
1183 | return 0; |
1184 | } | |
1185 | ||
1186 | /* | |
1187 | * Attach to a macio probed interface | |
1188 | */ | |
1189 | static int __devinit | |
5e655772 | 1190 | pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
1191 | { |
1192 | void __iomem *base; | |
1193 | unsigned long regbase; | |
1194 | int irq; | |
1195 | ide_hwif_t *hwif; | |
1196 | pmac_ide_hwif_t *pmif; | |
1197 | int i, rc; | |
1198 | ||
1199 | i = 0; | |
1200 | while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0 | |
1201 | || pmac_ide[i].node != NULL)) | |
1202 | ++i; | |
1203 | if (i >= MAX_HWIFS) { | |
1204 | printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n"); | |
1205 | printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name); | |
1206 | return -ENODEV; | |
1207 | } | |
1208 | ||
1209 | pmif = &pmac_ide[i]; | |
1210 | hwif = &ide_hwifs[i]; | |
1211 | ||
cc5d0189 | 1212 | if (macio_resource_count(mdev) == 0) { |
1da177e4 LT |
1213 | printk(KERN_WARNING "ide%d: no address for %s\n", |
1214 | i, mdev->ofdev.node->full_name); | |
1215 | return -ENXIO; | |
1216 | } | |
1217 | ||
1218 | /* Request memory resource for IO ports */ | |
1219 | if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) { | |
1220 | printk(KERN_ERR "ide%d: can't request mmio resource !\n", i); | |
1221 | return -EBUSY; | |
1222 | } | |
1223 | ||
1224 | /* XXX This is bogus. Should be fixed in the registry by checking | |
1225 | * the kind of host interrupt controller, a bit like gatwick | |
1226 | * fixes in irq.c. That works well enough for the single case | |
1227 | * where that happens though... | |
1228 | */ | |
1229 | if (macio_irq_count(mdev) == 0) { | |
1230 | printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n", | |
1231 | i, mdev->ofdev.node->full_name); | |
69917c26 | 1232 | irq = irq_create_mapping(NULL, 13); |
1da177e4 LT |
1233 | } else |
1234 | irq = macio_irq(mdev, 0); | |
1235 | ||
1236 | base = ioremap(macio_resource_start(mdev, 0), 0x400); | |
1237 | regbase = (unsigned long) base; | |
1238 | ||
1239 | hwif->pci_dev = mdev->bus->pdev; | |
1240 | hwif->gendev.parent = &mdev->ofdev.dev; | |
1241 | ||
1242 | pmif->mdev = mdev; | |
1243 | pmif->node = mdev->ofdev.node; | |
1244 | pmif->regbase = regbase; | |
1245 | pmif->irq = irq; | |
1246 | pmif->kauai_fcr = NULL; | |
1247 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1248 | if (macio_resource_count(mdev) >= 2) { | |
1249 | if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) | |
1250 | printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i); | |
1251 | else | |
1252 | pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); | |
1253 | } else | |
1254 | pmif->dma_regs = NULL; | |
1255 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1256 | dev_set_drvdata(&mdev->ofdev.dev, hwif); | |
1257 | ||
1258 | rc = pmac_ide_setup_device(pmif, hwif); | |
1259 | if (rc != 0) { | |
1260 | /* The inteface is released to the common IDE layer */ | |
1261 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1262 | iounmap(base); | |
1263 | if (pmif->dma_regs) | |
1264 | iounmap(pmif->dma_regs); | |
1265 | memset(pmif, 0, sizeof(*pmif)); | |
1266 | macio_release_resource(mdev, 0); | |
1267 | if (pmif->dma_regs) | |
1268 | macio_release_resource(mdev, 1); | |
1269 | } | |
1270 | ||
1271 | return rc; | |
1272 | } | |
1273 | ||
1274 | static int | |
8b4b8a24 | 1275 | pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) |
1da177e4 LT |
1276 | { |
1277 | ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1278 | int rc = 0; | |
1279 | ||
8b4b8a24 DB |
1280 | if (mesg.event != mdev->ofdev.dev.power.power_state.event |
1281 | && mesg.event == PM_EVENT_SUSPEND) { | |
1da177e4 LT |
1282 | rc = pmac_ide_do_suspend(hwif); |
1283 | if (rc == 0) | |
8b4b8a24 | 1284 | mdev->ofdev.dev.power.power_state = mesg; |
1da177e4 LT |
1285 | } |
1286 | ||
1287 | return rc; | |
1288 | } | |
1289 | ||
1290 | static int | |
1291 | pmac_ide_macio_resume(struct macio_dev *mdev) | |
1292 | { | |
1293 | ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); | |
1294 | int rc = 0; | |
1295 | ||
ca078bae | 1296 | if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) { |
1da177e4 LT |
1297 | rc = pmac_ide_do_resume(hwif); |
1298 | if (rc == 0) | |
829ca9a3 | 1299 | mdev->ofdev.dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1300 | } |
1301 | ||
1302 | return rc; | |
1303 | } | |
1304 | ||
1305 | /* | |
1306 | * Attach to a PCI probed interface | |
1307 | */ | |
1308 | static int __devinit | |
1309 | pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) | |
1310 | { | |
1311 | ide_hwif_t *hwif; | |
1312 | struct device_node *np; | |
1313 | pmac_ide_hwif_t *pmif; | |
1314 | void __iomem *base; | |
1315 | unsigned long rbase, rlen; | |
1316 | int i, rc; | |
1317 | ||
1318 | np = pci_device_to_OF_node(pdev); | |
1319 | if (np == NULL) { | |
1320 | printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n"); | |
1321 | return -ENODEV; | |
1322 | } | |
1323 | i = 0; | |
1324 | while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0 | |
1325 | || pmac_ide[i].node != NULL)) | |
1326 | ++i; | |
1327 | if (i >= MAX_HWIFS) { | |
1328 | printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n"); | |
1329 | printk(KERN_ERR " %s\n", np->full_name); | |
1330 | return -ENODEV; | |
1331 | } | |
1332 | ||
1333 | pmif = &pmac_ide[i]; | |
1334 | hwif = &ide_hwifs[i]; | |
1335 | ||
1336 | if (pci_enable_device(pdev)) { | |
1337 | printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n", | |
1338 | i, np->full_name); | |
1339 | return -ENXIO; | |
1340 | } | |
1341 | pci_set_master(pdev); | |
1342 | ||
1343 | if (pci_request_regions(pdev, "Kauai ATA")) { | |
1344 | printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n", | |
1345 | i, np->full_name); | |
1346 | return -ENXIO; | |
1347 | } | |
1348 | ||
1349 | hwif->pci_dev = pdev; | |
1350 | hwif->gendev.parent = &pdev->dev; | |
1351 | pmif->mdev = NULL; | |
1352 | pmif->node = np; | |
1353 | ||
1354 | rbase = pci_resource_start(pdev, 0); | |
1355 | rlen = pci_resource_len(pdev, 0); | |
1356 | ||
1357 | base = ioremap(rbase, rlen); | |
1358 | pmif->regbase = (unsigned long) base + 0x2000; | |
1359 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1360 | pmif->dma_regs = base + 0x1000; | |
1361 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ | |
1362 | pmif->kauai_fcr = base; | |
1363 | pmif->irq = pdev->irq; | |
1364 | ||
1365 | pci_set_drvdata(pdev, hwif); | |
1366 | ||
1367 | rc = pmac_ide_setup_device(pmif, hwif); | |
1368 | if (rc != 0) { | |
1369 | /* The inteface is released to the common IDE layer */ | |
1370 | pci_set_drvdata(pdev, NULL); | |
1371 | iounmap(base); | |
1372 | memset(pmif, 0, sizeof(*pmif)); | |
1373 | pci_release_regions(pdev); | |
1374 | } | |
1375 | ||
1376 | return rc; | |
1377 | } | |
1378 | ||
1379 | static int | |
8b4b8a24 | 1380 | pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1da177e4 LT |
1381 | { |
1382 | ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev); | |
1383 | int rc = 0; | |
1384 | ||
8b4b8a24 DB |
1385 | if (mesg.event != pdev->dev.power.power_state.event |
1386 | && mesg.event == PM_EVENT_SUSPEND) { | |
1da177e4 LT |
1387 | rc = pmac_ide_do_suspend(hwif); |
1388 | if (rc == 0) | |
8b4b8a24 | 1389 | pdev->dev.power.power_state = mesg; |
1da177e4 LT |
1390 | } |
1391 | ||
1392 | return rc; | |
1393 | } | |
1394 | ||
1395 | static int | |
1396 | pmac_ide_pci_resume(struct pci_dev *pdev) | |
1397 | { | |
1398 | ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev); | |
1399 | int rc = 0; | |
1400 | ||
ca078bae | 1401 | if (pdev->dev.power.power_state.event != PM_EVENT_ON) { |
1da177e4 LT |
1402 | rc = pmac_ide_do_resume(hwif); |
1403 | if (rc == 0) | |
829ca9a3 | 1404 | pdev->dev.power.power_state = PMSG_ON; |
1da177e4 LT |
1405 | } |
1406 | ||
1407 | return rc; | |
1408 | } | |
1409 | ||
5e655772 | 1410 | static struct of_device_id pmac_ide_macio_match[] = |
1da177e4 LT |
1411 | { |
1412 | { | |
1413 | .name = "IDE", | |
1da177e4 LT |
1414 | }, |
1415 | { | |
1416 | .name = "ATA", | |
1da177e4 LT |
1417 | }, |
1418 | { | |
1da177e4 | 1419 | .type = "ide", |
1da177e4 LT |
1420 | }, |
1421 | { | |
1da177e4 | 1422 | .type = "ata", |
1da177e4 LT |
1423 | }, |
1424 | {}, | |
1425 | }; | |
1426 | ||
1427 | static struct macio_driver pmac_ide_macio_driver = | |
1428 | { | |
1429 | .name = "ide-pmac", | |
1430 | .match_table = pmac_ide_macio_match, | |
1431 | .probe = pmac_ide_macio_attach, | |
1432 | .suspend = pmac_ide_macio_suspend, | |
1433 | .resume = pmac_ide_macio_resume, | |
1434 | }; | |
1435 | ||
1436 | static struct pci_device_id pmac_ide_pci_match[] = { | |
7fce260a OJ |
1437 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, |
1438 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1439 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, | |
1440 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1441 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, | |
1442 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 LT |
1443 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA, |
1444 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
7fce260a OJ |
1445 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA, |
1446 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
71e4eda8 | 1447 | {}, |
1da177e4 LT |
1448 | }; |
1449 | ||
1450 | static struct pci_driver pmac_ide_pci_driver = { | |
1451 | .name = "ide-pmac", | |
1452 | .id_table = pmac_ide_pci_match, | |
1453 | .probe = pmac_ide_pci_attach, | |
1454 | .suspend = pmac_ide_pci_suspend, | |
1455 | .resume = pmac_ide_pci_resume, | |
1456 | }; | |
1457 | MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match); | |
1458 | ||
9e5755bc | 1459 | int __init pmac_ide_probe(void) |
1da177e4 | 1460 | { |
9e5755bc AM |
1461 | int error; |
1462 | ||
e8222502 | 1463 | if (!machine_is(powermac)) |
9e5755bc | 1464 | return -ENODEV; |
1da177e4 LT |
1465 | |
1466 | #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST | |
9e5755bc AM |
1467 | error = pci_register_driver(&pmac_ide_pci_driver); |
1468 | if (error) | |
1469 | goto out; | |
1470 | error = macio_register_driver(&pmac_ide_macio_driver); | |
1471 | if (error) { | |
1472 | pci_unregister_driver(&pmac_ide_pci_driver); | |
1473 | goto out; | |
1474 | } | |
1da177e4 | 1475 | #else |
9e5755bc AM |
1476 | error = macio_register_driver(&pmac_ide_macio_driver); |
1477 | if (error) | |
1478 | goto out; | |
1479 | error = pci_register_driver(&pmac_ide_pci_driver); | |
1480 | if (error) { | |
1481 | macio_unregister_driver(&pmac_ide_macio_driver); | |
1482 | goto out; | |
1483 | } | |
1beb6a7d | 1484 | #endif |
9e5755bc AM |
1485 | out: |
1486 | return error; | |
1da177e4 LT |
1487 | } |
1488 | ||
1489 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | |
1490 | ||
1491 | /* | |
1492 | * pmac_ide_build_dmatable builds the DBDMA command list | |
1493 | * for a transfer and sets the DBDMA channel to point to it. | |
1494 | */ | |
aacaf9bd | 1495 | static int |
1da177e4 LT |
1496 | pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) |
1497 | { | |
1498 | struct dbdma_cmd *table; | |
1499 | int i, count = 0; | |
1500 | ide_hwif_t *hwif = HWIF(drive); | |
1501 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
1502 | volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; | |
1503 | struct scatterlist *sg; | |
1504 | int wr = (rq_data_dir(rq) == WRITE); | |
1505 | ||
1506 | /* DMA table is already aligned */ | |
1507 | table = (struct dbdma_cmd *) pmif->dma_table_cpu; | |
1508 | ||
1509 | /* Make sure DMA controller is stopped (necessary ?) */ | |
1510 | writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); | |
1511 | while (readl(&dma->status) & RUN) | |
1512 | udelay(1); | |
1513 | ||
1514 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
1515 | ||
1516 | if (!i) | |
1517 | return 0; | |
1518 | ||
1519 | /* Build DBDMA commands list */ | |
1520 | sg = hwif->sg_table; | |
1521 | while (i && sg_dma_len(sg)) { | |
1522 | u32 cur_addr; | |
1523 | u32 cur_len; | |
1524 | ||
1525 | cur_addr = sg_dma_address(sg); | |
1526 | cur_len = sg_dma_len(sg); | |
1527 | ||
1528 | if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) { | |
1529 | if (pmif->broken_dma_warn == 0) { | |
1530 | printk(KERN_WARNING "%s: DMA on non aligned address," | |
1531 | "switching to PIO on Ohare chipset\n", drive->name); | |
1532 | pmif->broken_dma_warn = 1; | |
1533 | } | |
1534 | goto use_pio_instead; | |
1535 | } | |
1536 | while (cur_len) { | |
1537 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
1538 | ||
1539 | if (count++ >= MAX_DCMDS) { | |
1540 | printk(KERN_WARNING "%s: DMA table too small\n", | |
1541 | drive->name); | |
1542 | goto use_pio_instead; | |
1543 | } | |
1544 | st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE); | |
1545 | st_le16(&table->req_count, tc); | |
1546 | st_le32(&table->phy_addr, cur_addr); | |
1547 | table->cmd_dep = 0; | |
1548 | table->xfer_status = 0; | |
1549 | table->res_count = 0; | |
1550 | cur_addr += tc; | |
1551 | cur_len -= tc; | |
1552 | ++table; | |
1553 | } | |
1554 | sg++; | |
1555 | i--; | |
1556 | } | |
1557 | ||
1558 | /* convert the last command to an input/output last command */ | |
1559 | if (count) { | |
1560 | st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST); | |
1561 | /* add the stop command to the end of the list */ | |
1562 | memset(table, 0, sizeof(struct dbdma_cmd)); | |
1563 | st_le16(&table->command, DBDMA_STOP); | |
1564 | mb(); | |
1565 | writel(hwif->dmatable_dma, &dma->cmdptr); | |
1566 | return 1; | |
1567 | } | |
1568 | ||
1569 | printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name); | |
1570 | use_pio_instead: | |
1571 | pci_unmap_sg(hwif->pci_dev, | |
1572 | hwif->sg_table, | |
1573 | hwif->sg_nents, | |
1574 | hwif->sg_dma_direction); | |
1575 | return 0; /* revert to PIO for this request */ | |
1576 | } | |
1577 | ||
1578 | /* Teardown mappings after DMA has completed. */ | |
aacaf9bd | 1579 | static void |
1da177e4 LT |
1580 | pmac_ide_destroy_dmatable (ide_drive_t *drive) |
1581 | { | |
1582 | ide_hwif_t *hwif = drive->hwif; | |
1583 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
1584 | struct scatterlist *sg = hwif->sg_table; | |
1585 | int nents = hwif->sg_nents; | |
1586 | ||
1587 | if (nents) { | |
1588 | pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction); | |
1589 | hwif->sg_nents = 0; | |
1590 | } | |
1591 | } | |
1592 | ||
1da177e4 LT |
1593 | /* |
1594 | * Check what is the best DMA timing setting for the drive and | |
1595 | * call appropriate functions to apply it. | |
1596 | */ | |
aacaf9bd | 1597 | static int |
1da177e4 LT |
1598 | pmac_ide_dma_check(ide_drive_t *drive) |
1599 | { | |
254bb550 BZ |
1600 | if (ide_tune_dma(drive)) |
1601 | return 0; | |
fd553ce8 | 1602 | |
254bb550 | 1603 | return -1; |
1da177e4 LT |
1604 | } |
1605 | ||
1606 | /* | |
1607 | * Prepare a DMA transfer. We build the DMA table, adjust the timings for | |
1608 | * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion | |
1609 | */ | |
aacaf9bd | 1610 | static int |
1da177e4 LT |
1611 | pmac_ide_dma_setup(ide_drive_t *drive) |
1612 | { | |
1613 | ide_hwif_t *hwif = HWIF(drive); | |
1614 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data; | |
1615 | struct request *rq = HWGROUP(drive)->rq; | |
1616 | u8 unit = (drive->select.b.unit & 0x01); | |
1617 | u8 ata4; | |
1618 | ||
1619 | if (pmif == NULL) | |
1620 | return 1; | |
1621 | ata4 = (pmif->kind == controller_kl_ata4); | |
1622 | ||
1623 | if (!pmac_ide_build_dmatable(drive, rq)) { | |
1624 | ide_map_sg(drive, rq); | |
1625 | return 1; | |
1626 | } | |
1627 | ||
1628 | /* Apple adds 60ns to wrDataSetup on reads */ | |
1629 | if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { | |
1630 | writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0), | |
1631 | PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1632 | (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); | |
1633 | } | |
1634 | ||
1635 | drive->waiting_for_dma = 1; | |
1636 | ||
1637 | return 0; | |
1638 | } | |
1639 | ||
aacaf9bd | 1640 | static void |
1da177e4 LT |
1641 | pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1642 | { | |
1643 | /* issue cmd to drive */ | |
1644 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL); | |
1645 | } | |
1646 | ||
1647 | /* | |
1648 | * Kick the DMA controller into life after the DMA command has been issued | |
1649 | * to the drive. | |
1650 | */ | |
aacaf9bd | 1651 | static void |
1da177e4 LT |
1652 | pmac_ide_dma_start(ide_drive_t *drive) |
1653 | { | |
1654 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1655 | volatile struct dbdma_regs __iomem *dma; | |
1656 | ||
1657 | dma = pmif->dma_regs; | |
1658 | ||
1659 | writel((RUN << 16) | RUN, &dma->control); | |
1660 | /* Make sure it gets to the controller right now */ | |
1661 | (void)readl(&dma->control); | |
1662 | } | |
1663 | ||
1664 | /* | |
1665 | * After a DMA transfer, make sure the controller is stopped | |
1666 | */ | |
aacaf9bd | 1667 | static int |
1da177e4 LT |
1668 | pmac_ide_dma_end (ide_drive_t *drive) |
1669 | { | |
1670 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1671 | volatile struct dbdma_regs __iomem *dma; | |
1672 | u32 dstat; | |
1673 | ||
1674 | if (pmif == NULL) | |
1675 | return 0; | |
1676 | dma = pmif->dma_regs; | |
1677 | ||
1678 | drive->waiting_for_dma = 0; | |
1679 | dstat = readl(&dma->status); | |
1680 | writel(((RUN|WAKE|DEAD) << 16), &dma->control); | |
1681 | pmac_ide_destroy_dmatable(drive); | |
1682 | /* verify good dma status. we don't check for ACTIVE beeing 0. We should... | |
1683 | * in theory, but with ATAPI decices doing buffer underruns, that would | |
1684 | * cause us to disable DMA, which isn't what we want | |
1685 | */ | |
1686 | return (dstat & (RUN|DEAD)) != RUN; | |
1687 | } | |
1688 | ||
1689 | /* | |
1690 | * Check out that the interrupt we got was for us. We can't always know this | |
1691 | * for sure with those Apple interfaces (well, we could on the recent ones but | |
1692 | * that's not implemented yet), on the other hand, we don't have shared interrupts | |
1693 | * so it's not really a problem | |
1694 | */ | |
aacaf9bd | 1695 | static int |
1da177e4 LT |
1696 | pmac_ide_dma_test_irq (ide_drive_t *drive) |
1697 | { | |
1698 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1699 | volatile struct dbdma_regs __iomem *dma; | |
1700 | unsigned long status, timeout; | |
1701 | ||
1702 | if (pmif == NULL) | |
1703 | return 0; | |
1704 | dma = pmif->dma_regs; | |
1705 | ||
1706 | /* We have to things to deal with here: | |
1707 | * | |
1708 | * - The dbdma won't stop if the command was started | |
1709 | * but completed with an error without transferring all | |
1710 | * datas. This happens when bad blocks are met during | |
1711 | * a multi-block transfer. | |
1712 | * | |
1713 | * - The dbdma fifo hasn't yet finished flushing to | |
1714 | * to system memory when the disk interrupt occurs. | |
1715 | * | |
1716 | */ | |
1717 | ||
1718 | /* If ACTIVE is cleared, the STOP command have passed and | |
1719 | * transfer is complete. | |
1720 | */ | |
1721 | status = readl(&dma->status); | |
1722 | if (!(status & ACTIVE)) | |
1723 | return 1; | |
1724 | if (!drive->waiting_for_dma) | |
1725 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1726 | called while not waiting\n", HWIF(drive)->index); | |
1727 | ||
1728 | /* If dbdma didn't execute the STOP command yet, the | |
1729 | * active bit is still set. We consider that we aren't | |
1730 | * sharing interrupts (which is hopefully the case with | |
1731 | * those controllers) and so we just try to flush the | |
1732 | * channel for pending data in the fifo | |
1733 | */ | |
1734 | udelay(1); | |
1735 | writel((FLUSH << 16) | FLUSH, &dma->control); | |
1736 | timeout = 0; | |
1737 | for (;;) { | |
1738 | udelay(1); | |
1739 | status = readl(&dma->status); | |
1740 | if ((status & FLUSH) == 0) | |
1741 | break; | |
1742 | if (++timeout > 100) { | |
1743 | printk(KERN_WARNING "ide%d, ide_dma_test_irq \ | |
1744 | timeout flushing channel\n", HWIF(drive)->index); | |
1745 | break; | |
1746 | } | |
1747 | } | |
1748 | return 1; | |
1749 | } | |
1750 | ||
7469aaf6 | 1751 | static void pmac_ide_dma_host_off(ide_drive_t *drive) |
1da177e4 | 1752 | { |
1da177e4 LT |
1753 | } |
1754 | ||
9e5755bc | 1755 | static void pmac_ide_dma_host_on(ide_drive_t *drive) |
1da177e4 | 1756 | { |
1da177e4 LT |
1757 | } |
1758 | ||
841d2a9b SS |
1759 | static void |
1760 | pmac_ide_dma_lost_irq (ide_drive_t *drive) | |
1da177e4 LT |
1761 | { |
1762 | pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; | |
1763 | volatile struct dbdma_regs __iomem *dma; | |
1764 | unsigned long status; | |
1765 | ||
1766 | if (pmif == NULL) | |
841d2a9b | 1767 | return; |
1da177e4 LT |
1768 | dma = pmif->dma_regs; |
1769 | ||
1770 | status = readl(&dma->status); | |
1771 | printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status); | |
1da177e4 LT |
1772 | } |
1773 | ||
1774 | /* | |
1775 | * Allocate the data structures needed for using DMA with an interface | |
1776 | * and fill the proper list of functions pointers | |
1777 | */ | |
1778 | static void __init | |
1779 | pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif) | |
1780 | { | |
1781 | /* We won't need pci_dev if we switch to generic consistent | |
1782 | * DMA routines ... | |
1783 | */ | |
1784 | if (hwif->pci_dev == NULL) | |
1785 | return; | |
1786 | /* | |
1787 | * Allocate space for the DBDMA commands. | |
1788 | * The +2 is +1 for the stop command and +1 to allow for | |
1789 | * aligning the start address to a multiple of 16 bytes. | |
1790 | */ | |
1791 | pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent( | |
1792 | hwif->pci_dev, | |
1793 | (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), | |
1794 | &hwif->dmatable_dma); | |
1795 | if (pmif->dma_table_cpu == NULL) { | |
1796 | printk(KERN_ERR "%s: unable to allocate DMA command list\n", | |
1797 | hwif->name); | |
1798 | return; | |
1799 | } | |
1800 | ||
7469aaf6 | 1801 | hwif->dma_off_quietly = &ide_dma_off_quietly; |
1da177e4 LT |
1802 | hwif->ide_dma_on = &__ide_dma_on; |
1803 | hwif->ide_dma_check = &pmac_ide_dma_check; | |
1804 | hwif->dma_setup = &pmac_ide_dma_setup; | |
1805 | hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd; | |
1806 | hwif->dma_start = &pmac_ide_dma_start; | |
1807 | hwif->ide_dma_end = &pmac_ide_dma_end; | |
1808 | hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq; | |
7469aaf6 | 1809 | hwif->dma_host_off = &pmac_ide_dma_host_off; |
ccf35289 | 1810 | hwif->dma_host_on = &pmac_ide_dma_host_on; |
c283f5db | 1811 | hwif->dma_timeout = &ide_dma_timeout; |
841d2a9b | 1812 | hwif->dma_lost_irq = &pmac_ide_dma_lost_irq; |
1da177e4 LT |
1813 | |
1814 | hwif->atapi_dma = 1; | |
1815 | switch(pmif->kind) { | |
1816 | case controller_sh_ata6: | |
1817 | hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07; | |
1818 | hwif->mwdma_mask = 0x07; | |
1819 | hwif->swdma_mask = 0x00; | |
1820 | break; | |
1821 | case controller_un_ata6: | |
1822 | case controller_k2_ata6: | |
1823 | hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07; | |
1824 | hwif->mwdma_mask = 0x07; | |
1825 | hwif->swdma_mask = 0x00; | |
1826 | break; | |
1827 | case controller_kl_ata4: | |
1828 | hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07; | |
1829 | hwif->mwdma_mask = 0x07; | |
1830 | hwif->swdma_mask = 0x00; | |
1831 | break; | |
1832 | default: | |
1833 | hwif->ultra_mask = 0x00; | |
1834 | hwif->mwdma_mask = 0x07; | |
1835 | hwif->swdma_mask = 0x00; | |
1836 | break; | |
254bb550 BZ |
1837 | } |
1838 | ||
1839 | hwif->autodma = 1; | |
1840 | hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma; | |
1da177e4 LT |
1841 | } |
1842 | ||
1843 | #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ |