[deliverable/linux.git] / drivers / ide / q40ide.c

/*
 *  Q40 I/O port IDE Driver
 *
 *     (c) Richard Zidlicky
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive for
 *  more details.
 *
 *
 */

#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/ide.h>

#include <asm/ide.h>

    /*
     *  Bases of the IDE interfaces
     */

#define Q40IDE_NUM_HWIFS	2

#define PCIDE_BASE1	0x1f0
#define PCIDE_BASE2	0x170
#define PCIDE_BASE3	0x1e8
#define PCIDE_BASE4	0x168
#define PCIDE_BASE5	0x1e0
#define PCIDE_BASE6	0x160

static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
    PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
    PCIDE_BASE6 */
};

static int q40ide_default_irq(unsigned long base)
{
           switch (base) {
	            case 0x1f0: return 14;
		    case 0x170: return 15;
		    case 0x1e8: return 11;
		    default:
			return 0;
	   }
}


/*
 * Addresses are pretranslated for Q40 ISA access.
 */
static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
			ide_ack_intr_t *ack_intr,
			int irq)
{
	memset(hw, 0, sizeof(hw_regs_t));
	/* BIG FAT WARNING: 
	   assumption: only DATA port is ever used in 16 bit mode */
	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);

	hw->irq = irq;
	hw->ack_intr = ack_intr;

	hw->chipset = ide_generic;
}

static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
			      void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
		__ide_mm_insw(data_addr, buf, (len + 1) / 2);
		return;
	}

	raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
}

static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
			       void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
		__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
		return;
	}

	raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
}

/* Q40 has a byte-swapped IDE interface */
static const struct ide_tp_ops q40ide_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ide_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= q40ide_input_data,
	.output_data		= q40ide_output_data,
};

static const struct ide_port_info q40ide_port_info = {
	.tp_ops			= &q40ide_tp_ops,
	.host_flags		= IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
	.irq_flags		= IRQF_SHARED,
};

/* 
 * the static array is needed to have the name reported in /proc/ioports,
 * hwif->name unfortunately isn't available yet
 */
static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	"ide0", "ide1"
};

/*
 *  Probe for Q40 IDE interfaces
 */

static int __init q40ide_init(void)
{
    int i;
    hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };

    if (!MACH_IS_Q40)
      return -ENODEV;

    printk(KERN_INFO "ide: Q40 IDE controller\n");

    for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
	const char *name = q40_ide_names[i];

	if (!request_region(pcide_bases[i], 8, name)) {
		printk("could not reserve ports %lx-%lx for %s\n",
		       pcide_bases[i],pcide_bases[i]+8,name);
		continue;
	}
	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
		printk("could not reserve port %lx for %s\n",
		       pcide_bases[i]+0x206,name);
		release_region(pcide_bases[i], 8);
		continue;
	}
	q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
			q40ide_default_irq(pcide_bases[i]));

	hws[i] = &hw[i];
    }

    return ide_host_add(&q40ide_port_info, hws, NULL);
}

module_init(q40ide_init);

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
58f189fc	2	* Q40 I/O port IDE Driver
1da177e4 LT	3	*
	4	* (c) Richard Zidlicky
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file COPYING in the main directory of this archive for
	8	* more details.
	9	*
	10	*
	11	*/
	12
	13	#include <linux/types.h>
	14	#include <linux/mm.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/blkdev.h>
1da177e4 LT	17	#include <linux/ide.h>
1da177e4 LT	18
d1881207 GU	19	#include <asm/ide.h>
d1881207 GU	20
1da177e4 LT	21	/*
	22	* Bases of the IDE interfaces
	23	*/
	24
	25	#define Q40IDE_NUM_HWIFS 2
	26
	27	#define PCIDE_BASE1 0x1f0
	28	#define PCIDE_BASE2 0x170
	29	#define PCIDE_BASE3 0x1e8
	30	#define PCIDE_BASE4 0x168
	31	#define PCIDE_BASE5 0x1e0
	32	#define PCIDE_BASE6 0x160
	33
	34	static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
	35	PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
	36	PCIDE_BASE6 */
	37	};
	38
1da177e4 LT	39	static int q40ide_default_irq(unsigned long base)
	40	{
	41	switch (base) {
	42	case 0x1f0: return 14;
	43	case 0x170: return 15;
	44	case 0x1e8: return 11;
	45	default:
	46	return 0;
	47	}
	48	}
	49
	50
	51	/*
29dd5975	52	* Addresses are pretranslated for Q40 ISA access.
1da177e4	53	*/
d28aa3ac	54	static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
1da177e4	55	ide_ack_intr_t *ack_intr,
1da177e4 LT	56	int irq)
1da177e4 LT	57	{
2c3e0262	58	memset(hw, 0, sizeof(hw_regs_t));
d28aa3ac AV	59	/* BIG FAT WARNING:
	60	assumption: only DATA port is ever used in 16 bit mode */
	61	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	62	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	63	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	64	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	65	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	66	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	67	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	68	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	69	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
86f3a492	70
1da177e4	71	hw->irq = irq;
1da177e4	72	hw->ack_intr = ack_intr;
d427e836 BZ	73
d427e836 BZ	74	hw->chipset = ide_generic;
1da177e4 LT	75	}
1da177e4 LT	76
adb1af98	77	static void q40ide_input_data(ide_drive_t drive, struct ide_cmd cmd,
9567b349	78	void *buf, unsigned int len)
92d3ab27	79	{
9567b349	80	unsigned long data_addr = drive->hwif->io_ports.data_addr;
92d3ab27	81
d1881207 GU	82	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
	83	__ide_mm_insw(data_addr, buf, (len + 1) / 2);
	84	return;
	85	}
92d3ab27	86
f94116ae	87	raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
92d3ab27 BZ	88	}
92d3ab27 BZ	89
adb1af98	90	static void q40ide_output_data(ide_drive_t drive, struct ide_cmd cmd,
9567b349	91	void *buf, unsigned int len)
92d3ab27	92	{
9567b349 BZ	93	unsigned long data_addr = drive->hwif->io_ports.data_addr;
9567b349 BZ	94
d1881207 GU	95	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
	96	__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
	97	return;
	98	}
92d3ab27	99
f94116ae	100	raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
92d3ab27	101	}
1da177e4	102
374e042c BZ	103	/* Q40 has a byte-swapped IDE interface */
	104	static const struct ide_tp_ops q40ide_tp_ops = {
	105	.exec_command = ide_exec_command,
	106	.read_status = ide_read_status,
	107	.read_altstatus = ide_read_altstatus,
ecf3a31d	108	.write_devctl = ide_write_devctl,
374e042c	109
abb596b2	110	.dev_select = ide_dev_select,
374e042c BZ	111	.tf_load = ide_tf_load,
	112	.tf_read = ide_tf_read,
	113
	114	.input_data = q40ide_input_data,
	115	.output_data = q40ide_output_data,
	116	};
	117
	118	static const struct ide_port_info q40ide_port_info = {
	119	.tp_ops = &q40ide_tp_ops,
09a3e791	120	.host_flags = IDE_HFLAG_MMIO \| IDE_HFLAG_NO_DMA,
255115fb	121	.irq_flags = IRQF_SHARED,
374e042c BZ	122	};
374e042c BZ	123
1da177e4 LT	124	/*
1da177e4 LT	125	* the static array is needed to have the name reported in /proc/ioports,
96de0e25	126	* hwif->name unfortunately isn't available yet
1da177e4 LT	127	*/
	128	static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	129	"ide0", "ide1"
	130	};
	131
	132	/*
	133	* Probe for Q40 IDE interfaces
	134	*/
	135
ade2daf9	136	static int __init q40ide_init(void)
1da177e4 LT	137	{
1da177e4 LT	138	int i;
c97c6aca	139	hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
1da177e4 LT	140
1da177e4 LT	141	if (!MACH_IS_Q40)
ade2daf9	142	return -ENODEV;
1da177e4	143
c99c92c5 BZ	144	printk(KERN_INFO "ide: Q40 IDE controller\n");
c99c92c5 BZ	145
1da177e4	146	for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
c97c6aca	147	const char *name = q40_ide_names[i];
1da177e4	148
1da177e4 LT	149	if (!request_region(pcide_bases[i], 8, name)) {
	150	printk("could not reserve ports %lx-%lx for %s\n",
	151	pcide_bases[i],pcide_bases[i]+8,name);
	152	continue;
	153	}
	154	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
	155	printk("could not reserve port %lx for %s\n",
	156	pcide_bases[i]+0x206,name);
	157	release_region(pcide_bases[i], 8);
	158	continue;
	159	}
c97c6aca	160	q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
1da177e4	161	q40ide_default_irq(pcide_bases[i]));
cbb010c1	162
48c3c107	163	hws[i] = &hw[i];
1da177e4	164	}
8ac4ce74	165
6f904d01	166	return ide_host_add(&q40ide_port_info, hws, NULL);
1da177e4 LT	167	}
1da177e4 LT	168
ade2daf9	169	module_init(q40ide_init);
f743d04d AB	170
f743d04d AB	171	MODULE_LICENSE("GPL");