Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/irq.h> | |
22 | ||
1da177e4 LT |
23 | /** |
24 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
25 | * @dev: PCI device of interface to switch native | |
26 | * @name: Name of interface | |
27 | * | |
28 | * We attempt to place the PCI interface into PCI native mode. If | |
29 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 30 | * Returns 0 on success or an errno code. |
1da177e4 LT |
31 | * |
32 | * FIXME: if we program the interface and then fail to set the BARS | |
33 | * we don't switch it back to legacy mode. Do we actually care ?? | |
34 | */ | |
846bb88a PC |
35 | |
36 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
37 | { |
38 | u8 progif = 0; | |
39 | ||
40 | /* | |
41 | * Place both IDE interfaces into PCI "native" mode: | |
42 | */ | |
43 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
44 | (progif & 5) != 5) { | |
45 | if ((progif & 0xa) != 0xa) { | |
46 | printk(KERN_INFO "%s: device not capable of full " | |
47 | "native PCI mode\n", name); | |
48 | return -EOPNOTSUPP; | |
49 | } | |
50 | printk("%s: placing both ports into native PCI mode\n", name); | |
51 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
52 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
53 | (progif & 5) != 5) { | |
54 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
55 | "0x%04x, got 0x%04x\n", | |
56 | name, progif|5, progif); | |
57 | return -EOPNOTSUPP; | |
58 | } | |
59 | } | |
60 | return 0; | |
61 | } | |
62 | ||
63 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
64 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
65 | { | |
66 | u8 dma_stat = inb(dma_base + 2); | |
67 | ||
68 | outb(dma_stat & 0x60, dma_base + 2); | |
69 | dma_stat = inb(dma_base + 2); | |
70 | if (dma_stat & 0x80) | |
71 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /** |
75 | * ide_get_or_set_dma_base - setup BMIBA | |
039788e1 BZ |
76 | * @d: IDE port info |
77 | * @hwif: IDE interface | |
1da177e4 | 78 | * |
c58e79dd BZ |
79 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
80 | * Where a device has a partner that is already in DMA mode we check | |
81 | * and enforce IDE simplex rules. | |
1da177e4 LT |
82 | */ |
83 | ||
85620436 | 84 | static unsigned long ide_get_or_set_dma_base(const struct ide_port_info *d, ide_hwif_t *hwif) |
1da177e4 | 85 | { |
36501650 BZ |
86 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
87 | unsigned long dma_base = 0; | |
8ac2b42a | 88 | u8 dma_stat = 0; |
1da177e4 | 89 | |
1da177e4 LT |
90 | if (hwif->mmio) |
91 | return hwif->dma_base; | |
92 | ||
93 | if (hwif->mate && hwif->mate->dma_base) { | |
94 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
95 | } else { | |
9ffcf364 BZ |
96 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
97 | ||
98 | dma_base = pci_resource_start(dev, baridx); | |
99 | ||
aea5d375 | 100 | if (dma_base == 0) { |
9ffcf364 | 101 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
102 | return 0; |
103 | } | |
1da177e4 LT |
104 | } |
105 | ||
aea5d375 BZ |
106 | if (hwif->channel) |
107 | dma_base += 8; | |
108 | ||
8ac2b42a BZ |
109 | if (d->host_flags & IDE_HFLAG_CS5520) |
110 | goto out; | |
111 | ||
112 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
113 | ide_pci_clear_simplex(dma_base, d->name); | |
114 | goto out; | |
115 | } | |
116 | ||
117 | /* | |
118 | * If the device claims "simplex" DMA, this means that only one of | |
119 | * the two interfaces can be trusted with DMA at any point in time | |
120 | * (so we should enable DMA only on one of the two interfaces). | |
121 | * | |
122 | * FIXME: At this point we haven't probed the drives so we can't make | |
123 | * the appropriate decision. Really we should defer this problem until | |
124 | * we tune the drive then try to grab DMA ownership if we want to be | |
125 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
126 | */ | |
127 | dma_stat = hwif->INB(dma_base + 2); | |
128 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
129 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
130 | dma_base = 0; | |
1da177e4 | 131 | } |
8ac2b42a | 132 | out: |
1da177e4 LT |
133 | return dma_base; |
134 | } | |
135 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
136 | ||
85620436 | 137 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 138 | { |
bde07e5e BZ |
139 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
140 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
141 | dev->revision, pci_name(dev)); | |
1da177e4 | 142 | } |
1da177e4 LT |
143 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
144 | ||
145 | ||
146 | /** | |
147 | * ide_pci_enable - do PCI enables | |
148 | * @dev: PCI device | |
039788e1 | 149 | * @d: IDE port info |
1da177e4 LT |
150 | * |
151 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
152 | * but if that fails then we only need IO space. The PCI code should |
153 | * have setup the proper resources for us already for controllers in | |
154 | * legacy mode. | |
846bb88a | 155 | * |
1da177e4 LT |
156 | * Returns zero on success or an error code |
157 | */ | |
039788e1 | 158 | |
85620436 | 159 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 160 | { |
0d1bad21 | 161 | int ret, bars; |
1da177e4 LT |
162 | |
163 | if (pci_enable_device(dev)) { | |
09483916 | 164 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
165 | if (ret < 0) { |
166 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
167 | "Could not enable device.\n", d->name); | |
168 | goto out; | |
169 | } | |
170 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
171 | } | |
172 | ||
173 | /* | |
039788e1 BZ |
174 | * assume all devices can do 32-bit DMA for now, we can add |
175 | * a DMA mask field to the struct ide_port_info if we need it | |
176 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
177 | */ |
178 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
179 | if (ret < 0) { | |
180 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
181 | goto out; | |
182 | } | |
183 | ||
0d1bad21 BZ |
184 | if (d->host_flags & IDE_HFLAG_SINGLE) |
185 | bars = (1 << 2) - 1; | |
186 | else | |
187 | bars = (1 << 4) - 1; | |
1da177e4 | 188 | |
0d1bad21 BZ |
189 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
190 | if (d->host_flags & IDE_HFLAG_CS5520) | |
191 | bars |= (1 << 2); | |
192 | else | |
193 | bars |= (1 << 4); | |
194 | } | |
195 | ||
196 | ret = pci_request_selected_regions(dev, bars, d->name); | |
197 | if (ret < 0) | |
198 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
199 | out: |
200 | return ret; | |
201 | } | |
202 | ||
203 | /** | |
204 | * ide_pci_configure - configure an unconfigured device | |
205 | * @dev: PCI device | |
039788e1 | 206 | * @d: IDE port info |
1da177e4 LT |
207 | * |
208 | * Enable and configure the PCI device we have been passed. | |
209 | * Returns zero on success or an error code. | |
210 | */ | |
039788e1 | 211 | |
85620436 | 212 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
213 | { |
214 | u16 pcicmd = 0; | |
215 | /* | |
216 | * PnP BIOS was *supposed* to have setup this device, but we | |
217 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
218 | * (or possibly the device is using a "legacy header" for IRQs). | |
219 | * Maybe the user deliberately *disabled* the device, | |
220 | * but we'll eventually ignore it again if no drives respond. | |
221 | */ | |
846bb88a PC |
222 | if (ide_setup_pci_baseregs(dev, d->name) || |
223 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
224 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
225 | return -ENODEV; | |
226 | } | |
227 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
228 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
229 | return -EIO; | |
230 | } | |
231 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
232 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
233 | return -ENXIO; | |
234 | } | |
235 | return 0; | |
236 | } | |
237 | ||
238 | /** | |
239 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
240 | * @dev: PCI device |
241 | * @d: IDE port info | |
242 | * @bar: BAR number | |
1da177e4 | 243 | * |
1baccff8 SS |
244 | * Checks if a BAR is configured and points to MMIO space. If so, |
245 | * return an error code. Otherwise return 0 | |
1da177e4 | 246 | */ |
039788e1 | 247 | |
1baccff8 SS |
248 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
249 | int bar) | |
1da177e4 LT |
250 | { |
251 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 252 | |
1da177e4 LT |
253 | /* Unconfigured ? */ |
254 | if (!flags || pci_resource_len(dev, bar) == 0) | |
255 | return 0; | |
256 | ||
1baccff8 SS |
257 | /* I/O space */ |
258 | if (flags & IORESOURCE_IO) | |
1da177e4 | 259 | return 0; |
846bb88a | 260 | |
1da177e4 | 261 | /* Bad */ |
1da177e4 LT |
262 | return -EINVAL; |
263 | } | |
264 | ||
265 | /** | |
266 | * ide_hwif_configure - configure an IDE interface | |
267 | * @dev: PCI device holding interface | |
039788e1 | 268 | * @d: IDE port info |
1ebf7493 BZ |
269 | * @port: port number |
270 | * @irq: PCI IRQ | |
1da177e4 LT |
271 | * |
272 | * Perform the initial set up for the hardware interface structure. This | |
273 | * is done per interface port rather than per PCI device. There may be | |
274 | * more than one port per device. | |
275 | * | |
276 | * Returns the new hardware interface structure, or NULL on a failure | |
277 | */ | |
039788e1 | 278 | |
1ebf7493 BZ |
279 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
280 | const struct ide_port_info *d, | |
281 | unsigned int port, int irq) | |
1da177e4 LT |
282 | { |
283 | unsigned long ctl = 0, base = 0; | |
284 | ide_hwif_t *hwif; | |
79127c37 | 285 | struct hw_regs_s hw; |
1da177e4 | 286 | |
a5d8c5c8 | 287 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
288 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
289 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
290 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
291 | "as MEM for port %d!\n", d->name, port); | |
292 | return NULL; | |
293 | } | |
846bb88a | 294 | |
1da177e4 LT |
295 | ctl = pci_resource_start(dev, 2*port+1); |
296 | base = pci_resource_start(dev, 2*port); | |
297 | if ((ctl && !base) || (base && !ctl)) { | |
298 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
299 | "for port %d, skipping\n", d->name, port); | |
300 | return NULL; | |
301 | } | |
302 | } | |
846bb88a | 303 | if (!ctl) { |
1da177e4 LT |
304 | /* Use default values */ |
305 | ctl = port ? 0x374 : 0x3f4; | |
306 | base = port ? 0x170 : 0x1f0; | |
307 | } | |
bad7c825 | 308 | |
fe80b937 | 309 | hwif = ide_find_port_slot(d); |
bad7c825 BZ |
310 | if (hwif == NULL) { |
311 | printk(KERN_ERR "%s: too many IDE interfaces, no room in " | |
312 | "table\n", d->name); | |
313 | return NULL; | |
314 | } | |
79127c37 BZ |
315 | |
316 | memset(&hw, 0, sizeof(hw)); | |
aab8ad9e | 317 | hw.irq = irq; |
79127c37 BZ |
318 | hw.dev = &dev->dev; |
319 | hw.chipset = d->chipset ? d->chipset : ide_pci; | |
320 | ide_std_init_ports(&hw, base, ctl | 2); | |
321 | ||
79127c37 BZ |
322 | ide_init_port_hw(hwif, &hw); |
323 | ||
36501650 | 324 | hwif->dev = &dev->dev; |
1da177e4 | 325 | |
1da177e4 LT |
326 | return hwif; |
327 | } | |
328 | ||
c413b9b9 | 329 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
330 | /** |
331 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 332 | * @hwif: IDE interface |
c413b9b9 | 333 | * @d: IDE port info |
1da177e4 LT |
334 | * |
335 | * Set up the DMA base for the interface. Enable the master bits as | |
336 | * necessary and attempt to bring the device DMA into a ready to use | |
337 | * state | |
338 | */ | |
039788e1 | 339 | |
c413b9b9 | 340 | void ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 341 | { |
c413b9b9 | 342 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 343 | u16 pcicmd; |
47b68788 | 344 | |
1da177e4 LT |
345 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); |
346 | ||
47b68788 | 347 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
348 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
349 | (dev->class & 0x80))) { | |
9ffcf364 | 350 | unsigned long dma_base = ide_get_or_set_dma_base(d, hwif); |
1da177e4 LT |
351 | if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { |
352 | /* | |
846bb88a | 353 | * Set up BM-DMA capability |
1da177e4 | 354 | * (PnP BIOS should have done this) |
846bb88a | 355 | */ |
1da177e4 LT |
356 | pci_set_master(dev); |
357 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { | |
358 | printk(KERN_ERR "%s: %s error updating PCICMD\n", | |
359 | hwif->name, d->name); | |
360 | dma_base = 0; | |
361 | } | |
362 | } | |
363 | if (dma_base) { | |
23658f8a | 364 | if (d->init_dma) |
1da177e4 | 365 | d->init_dma(hwif, dma_base); |
23658f8a BZ |
366 | |
367 | ide_setup_dma(hwif, dma_base); | |
1da177e4 LT |
368 | } else { |
369 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled " | |
370 | "(BIOS)\n", hwif->name, d->name); | |
371 | } | |
372 | } | |
039788e1 | 373 | } |
c413b9b9 | 374 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
375 | |
376 | /** | |
377 | * ide_setup_pci_controller - set up IDE PCI | |
378 | * @dev: PCI device | |
039788e1 | 379 | * @d: IDE port info |
1da177e4 LT |
380 | * @noisy: verbose flag |
381 | * @config: returned as 1 if we configured the hardware | |
382 | * | |
383 | * Set up the PCI and controller side of the IDE interface. This brings | |
384 | * up the PCI side of the device, checks that the device is enabled | |
385 | * and enables it if need be | |
386 | */ | |
039788e1 | 387 | |
85620436 | 388 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
389 | { |
390 | int ret; | |
1da177e4 LT |
391 | u16 pcicmd; |
392 | ||
393 | if (noisy) | |
394 | ide_setup_pci_noise(dev, d); | |
395 | ||
396 | ret = ide_pci_enable(dev, d); | |
397 | if (ret < 0) | |
398 | goto out; | |
399 | ||
400 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
401 | if (ret < 0) { | |
402 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
403 | goto out; | |
404 | } | |
405 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
406 | ret = ide_pci_configure(dev, d); | |
407 | if (ret < 0) | |
408 | goto out; | |
409 | *config = 1; | |
410 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
411 | } | |
412 | ||
1da177e4 LT |
413 | out: |
414 | return ret; | |
415 | } | |
416 | ||
417 | /** | |
418 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
419 | * @dev: PCI device | |
039788e1 | 420 | * @d: IDE port info |
1da177e4 | 421 | * @pciirq: IRQ line |
8447d9d5 | 422 | * @idx: ATA index table to update |
1da177e4 LT |
423 | * |
424 | * Scan the interfaces attached to this device and do any | |
425 | * necessary per port setup. Attach the devices and ask the | |
426 | * generic DMA layer to do its work for us. | |
427 | * | |
428 | * Normally called automaticall from do_ide_pci_setup_device, | |
429 | * but is also used directly as a helper function by some controllers | |
430 | * where the chipset setup is not the default PCI IDE one. | |
431 | */ | |
8447d9d5 | 432 | |
85620436 | 433 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx) |
1da177e4 | 434 | { |
a5d8c5c8 | 435 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 436 | ide_hwif_t *hwif; |
1da177e4 LT |
437 | u8 tmp; |
438 | ||
1da177e4 LT |
439 | /* |
440 | * Set up the IDE ports | |
441 | */ | |
cf6e854e | 442 | |
a5d8c5c8 | 443 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
444 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
445 | ||
1da177e4 | 446 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
447 | (tmp & e->mask) != e->val)) { |
448 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 449 | continue; /* port not enabled */ |
cf6e854e | 450 | } |
1da177e4 | 451 | |
1ebf7493 BZ |
452 | hwif = ide_hwif_configure(dev, d, port, pciirq); |
453 | if (hwif == NULL) | |
1da177e4 LT |
454 | continue; |
455 | ||
8447d9d5 | 456 | *(idx + port) = hwif->index; |
1ebf7493 | 457 | } |
1da177e4 | 458 | } |
1da177e4 LT |
459 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
460 | ||
461 | /* | |
462 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
463 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
464 | * for use with them. This generic code works for most PCI chipsets. | |
465 | * | |
466 | * One thing that is not standardized is the location of the | |
467 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 468 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
469 | * for all other chipsets, we just assume both interfaces are enabled. |
470 | */ | |
039788e1 | 471 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 472 | const struct ide_port_info *d, |
8447d9d5 | 473 | u8 *idx, u8 noisy) |
1da177e4 | 474 | { |
1da177e4 LT |
475 | int tried_config = 0; |
476 | int pciirq, ret; | |
477 | ||
478 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
479 | if (ret < 0) | |
480 | goto out; | |
481 | ||
482 | /* | |
483 | * Can we trust the reported IRQ? | |
484 | */ | |
485 | pciirq = dev->irq; | |
486 | ||
487 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
488 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
489 | if (noisy) | |
490 | printk(KERN_INFO "%s: not 100%% native mode: " | |
491 | "will probe irqs later\n", d->name); | |
492 | /* | |
493 | * This allows offboard ide-pci cards the enable a BIOS, | |
494 | * verify interrupt settings of split-mirror pci-config | |
495 | * space, place chipset into init-mode, and/or preserve | |
496 | * an interrupt if the card is not native ide support. | |
497 | */ | |
498 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
499 | if (ret < 0) | |
500 | goto out; | |
501 | pciirq = ret; | |
502 | } else if (tried_config) { | |
503 | if (noisy) | |
504 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
505 | pciirq = 0; | |
506 | } else if (!pciirq) { | |
507 | if (noisy) | |
508 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
509 | d->name, pciirq); | |
510 | pciirq = 0; | |
511 | } else { | |
512 | if (d->init_chipset) { | |
513 | ret = d->init_chipset(dev, d->name); | |
514 | if (ret < 0) | |
515 | goto out; | |
516 | } | |
517 | if (noisy) | |
1da177e4 LT |
518 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
519 | d->name, pciirq); | |
1da177e4 LT |
520 | } |
521 | ||
522 | /* FIXME: silent failure can happen */ | |
523 | ||
8447d9d5 | 524 | ide_pci_setup_ports(dev, d, pciirq, idx); |
1da177e4 LT |
525 | out: |
526 | return ret; | |
527 | } | |
528 | ||
85620436 | 529 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 530 | { |
8447d9d5 | 531 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
532 | int ret; |
533 | ||
8447d9d5 | 534 | ret = do_ide_setup_pci_device(dev, d, &idx[0], 1); |
1da177e4 | 535 | |
8447d9d5 | 536 | if (ret >= 0) |
c413b9b9 | 537 | ide_device_add(idx, d); |
1da177e4 | 538 | |
1da177e4 LT |
539 | return ret; |
540 | } | |
1da177e4 LT |
541 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
542 | ||
543 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 544 | const struct ide_port_info *d) |
1da177e4 LT |
545 | { |
546 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 547 | int ret, i; |
8447d9d5 | 548 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
549 | |
550 | for (i = 0; i < 2; i++) { | |
8447d9d5 | 551 | ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i); |
1da177e4 LT |
552 | /* |
553 | * FIXME: Mom, mom, they stole me the helper function to undo | |
554 | * do_ide_setup_pci_device() on the first device! | |
555 | */ | |
556 | if (ret < 0) | |
557 | goto out; | |
558 | } | |
559 | ||
c413b9b9 | 560 | ide_device_add(idx, d); |
1da177e4 LT |
561 | out: |
562 | return ret; | |
563 | } | |
1da177e4 | 564 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |