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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/setup-pci.c Version 1.10 2002/08/19 | |
3 | * | |
4 | * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * | |
6 | * Copyright (c) 1995-1998 Mark Lord | |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
9 | * Recent Changes | |
10 | * Split the set up function into multiple functions | |
11 | * Use pci_set_master | |
12 | * Fix misreporting of I/O v MMIO problems | |
13 | * Initial fixups for simplex devices | |
14 | */ | |
15 | ||
16 | /* | |
17 | * This module provides support for automatic detection and | |
18 | * configuration of all PCI IDE interfaces present in a system. | |
19 | */ | |
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/timer.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ide.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | ||
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | ||
36 | ||
37 | /** | |
38 | * ide_match_hwif - match a PCI IDE against an ide_hwif | |
39 | * @io_base: I/O base of device | |
40 | * @bootable: set if its bootable | |
41 | * @name: name of device | |
42 | * | |
43 | * Match a PCI IDE port against an entry in ide_hwifs[], | |
44 | * based on io_base port if possible. Return the matching hwif, | |
45 | * or a new hwif. If we find an error (clashing, out of devices, etc) | |
46 | * return NULL | |
47 | * | |
48 | * FIXME: we need to handle mmio matches here too | |
49 | */ | |
50 | ||
51 | static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name) | |
52 | { | |
53 | int h; | |
54 | ide_hwif_t *hwif; | |
55 | ||
56 | /* | |
57 | * Look for a hwif with matching io_base specified using | |
58 | * parameters to ide_setup(). | |
59 | */ | |
60 | for (h = 0; h < MAX_HWIFS; ++h) { | |
61 | hwif = &ide_hwifs[h]; | |
62 | if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { | |
63 | if (hwif->chipset == ide_forced) | |
64 | return hwif; /* a perfect match */ | |
65 | } | |
66 | } | |
67 | /* | |
68 | * Look for a hwif with matching io_base default value. | |
69 | * If chipset is "ide_unknown", then claim that hwif slot. | |
70 | * Otherwise, some other chipset has already claimed it.. :( | |
71 | */ | |
72 | for (h = 0; h < MAX_HWIFS; ++h) { | |
73 | hwif = &ide_hwifs[h]; | |
74 | if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { | |
75 | if (hwif->chipset == ide_unknown) | |
76 | return hwif; /* match */ | |
77 | printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n", | |
78 | name, io_base, hwif->name); | |
79 | return NULL; /* already claimed */ | |
80 | } | |
81 | } | |
82 | /* | |
83 | * Okay, there is no hwif matching our io_base, | |
84 | * so we'll just claim an unassigned slot. | |
85 | * Give preference to claiming other slots before claiming ide0/ide1, | |
86 | * just in case there's another interface yet-to-be-scanned | |
87 | * which uses ports 1f0/170 (the ide0/ide1 defaults). | |
88 | * | |
89 | * Unless there is a bootable card that does not use the standard | |
90 | * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag. | |
91 | */ | |
92 | if (bootable) { | |
93 | for (h = 0; h < MAX_HWIFS; ++h) { | |
94 | hwif = &ide_hwifs[h]; | |
95 | if (hwif->chipset == ide_unknown) | |
96 | return hwif; /* pick an unused entry */ | |
97 | } | |
98 | } else { | |
99 | for (h = 2; h < MAX_HWIFS; ++h) { | |
100 | hwif = ide_hwifs + h; | |
101 | if (hwif->chipset == ide_unknown) | |
102 | return hwif; /* pick an unused entry */ | |
103 | } | |
104 | } | |
105 | for (h = 0; h < 2; ++h) { | |
106 | hwif = ide_hwifs + h; | |
107 | if (hwif->chipset == ide_unknown) | |
108 | return hwif; /* pick an unused entry */ | |
109 | } | |
110 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name); | |
111 | return NULL; | |
112 | } | |
113 | ||
114 | /** | |
115 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
116 | * @dev: PCI device of interface to switch native | |
117 | * @name: Name of interface | |
118 | * | |
119 | * We attempt to place the PCI interface into PCI native mode. If | |
120 | * we succeed the BARs are ok and the controller is in PCI mode. | |
121 | * Returns 0 on success or an errno code. | |
122 | * | |
123 | * FIXME: if we program the interface and then fail to set the BARS | |
124 | * we don't switch it back to legacy mode. Do we actually care ?? | |
125 | */ | |
126 | ||
127 | static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name) | |
128 | { | |
129 | u8 progif = 0; | |
130 | ||
131 | /* | |
132 | * Place both IDE interfaces into PCI "native" mode: | |
133 | */ | |
134 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
135 | (progif & 5) != 5) { | |
136 | if ((progif & 0xa) != 0xa) { | |
137 | printk(KERN_INFO "%s: device not capable of full " | |
138 | "native PCI mode\n", name); | |
139 | return -EOPNOTSUPP; | |
140 | } | |
141 | printk("%s: placing both ports into native PCI mode\n", name); | |
142 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
143 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
144 | (progif & 5) != 5) { | |
145 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
146 | "0x%04x, got 0x%04x\n", | |
147 | name, progif|5, progif); | |
148 | return -EOPNOTSUPP; | |
149 | } | |
150 | } | |
151 | return 0; | |
152 | } | |
153 | ||
154 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
155 | ||
156 | #ifdef CONFIG_BLK_DEV_IDEDMA_FORCED | |
157 | /* | |
158 | * Long lost data from 2.0.34 that is now in 2.0.39 | |
159 | * | |
160 | * This was used in ./drivers/block/triton.c to do DMA Base address setup | |
161 | * when PnP failed. Oh the things we forget. I believe this was part | |
162 | * of SFF-8038i that has been withdrawn from public access... :-(( | |
163 | */ | |
164 | #define DEFAULT_BMIBA 0xe800 /* in case BIOS did not init it */ | |
165 | #define DEFAULT_BMCRBA 0xcc00 /* VIA's default value */ | |
166 | #define DEFAULT_BMALIBA 0xd400 /* ALI's default value */ | |
167 | #endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */ | |
168 | ||
169 | /** | |
170 | * ide_get_or_set_dma_base - setup BMIBA | |
171 | * @hwif: Interface | |
172 | * | |
173 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space: | |
174 | * If need be we set up the DMA base. Where a device has a partner that | |
175 | * is already in DMA mode we check and enforce IDE simplex rules. | |
176 | */ | |
177 | ||
178 | static unsigned long ide_get_or_set_dma_base (ide_hwif_t *hwif) | |
179 | { | |
180 | unsigned long dma_base = 0; | |
181 | struct pci_dev *dev = hwif->pci_dev; | |
182 | ||
183 | #ifdef CONFIG_BLK_DEV_IDEDMA_FORCED | |
184 | int second_chance = 0; | |
185 | ||
186 | second_chance_to_dma: | |
187 | #endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */ | |
188 | ||
189 | if (hwif->mmio) | |
190 | return hwif->dma_base; | |
191 | ||
192 | if (hwif->mate && hwif->mate->dma_base) { | |
193 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
194 | } else { | |
195 | dma_base = pci_resource_start(dev, 4); | |
196 | if (!dma_base) { | |
197 | printk(KERN_ERR "%s: dma_base is invalid\n", | |
198 | hwif->cds->name); | |
199 | } | |
200 | } | |
201 | ||
202 | #ifdef CONFIG_BLK_DEV_IDEDMA_FORCED | |
203 | /* FIXME - should use pci_assign_resource surely */ | |
204 | if ((!dma_base) && (!second_chance)) { | |
205 | unsigned long set_bmiba = 0; | |
206 | second_chance++; | |
207 | switch(dev->vendor) { | |
208 | case PCI_VENDOR_ID_AL: | |
209 | set_bmiba = DEFAULT_BMALIBA; break; | |
210 | case PCI_VENDOR_ID_VIA: | |
211 | set_bmiba = DEFAULT_BMCRBA; break; | |
212 | case PCI_VENDOR_ID_INTEL: | |
213 | set_bmiba = DEFAULT_BMIBA; break; | |
214 | default: | |
215 | return dma_base; | |
216 | } | |
217 | pci_write_config_dword(dev, 0x20, set_bmiba|1); | |
218 | goto second_chance_to_dma; | |
219 | } | |
220 | #endif /* CONFIG_BLK_DEV_IDEDMA_FORCED */ | |
221 | ||
222 | if (dma_base) { | |
223 | u8 simplex_stat = 0; | |
224 | dma_base += hwif->channel ? 8 : 0; | |
225 | ||
226 | switch(dev->device) { | |
227 | case PCI_DEVICE_ID_AL_M5219: | |
228 | case PCI_DEVICE_ID_AL_M5229: | |
229 | case PCI_DEVICE_ID_AMD_VIPER_7409: | |
230 | case PCI_DEVICE_ID_CMD_643: | |
231 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
2f09a7f4 | 232 | case PCI_DEVICE_ID_REVOLUTION: |
1da177e4 LT |
233 | simplex_stat = hwif->INB(dma_base + 2); |
234 | hwif->OUTB((simplex_stat&0x60),(dma_base + 2)); | |
235 | simplex_stat = hwif->INB(dma_base + 2); | |
236 | if (simplex_stat & 0x80) { | |
237 | printk(KERN_INFO "%s: simplex device: " | |
238 | "DMA forced\n", | |
239 | hwif->cds->name); | |
240 | } | |
241 | break; | |
242 | default: | |
243 | /* | |
244 | * If the device claims "simplex" DMA, | |
245 | * this means only one of the two interfaces | |
246 | * can be trusted with DMA at any point in time. | |
247 | * So we should enable DMA only on one of the | |
248 | * two interfaces. | |
249 | */ | |
250 | simplex_stat = hwif->INB(dma_base + 2); | |
251 | if (simplex_stat & 0x80) { | |
252 | /* simplex device? */ | |
253 | /* | |
254 | * At this point we haven't probed the drives so we can't make the | |
255 | * appropriate decision. Really we should defer this problem | |
256 | * until we tune the drive then try to grab DMA ownership if we want | |
257 | * to be the DMA end. This has to be become dynamic to handle hot | |
258 | * plug. | |
259 | */ | |
260 | if (hwif->mate && hwif->mate->dma_base) { | |
261 | printk(KERN_INFO "%s: simplex device: " | |
262 | "DMA disabled\n", | |
263 | hwif->cds->name); | |
264 | dma_base = 0; | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | return dma_base; | |
270 | } | |
271 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
272 | ||
273 | void ide_setup_pci_noise (struct pci_dev *dev, ide_pci_device_t *d) | |
274 | { | |
275 | printk(KERN_INFO "%s: IDE controller at PCI slot %s\n", | |
276 | d->name, pci_name(dev)); | |
277 | } | |
278 | ||
279 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); | |
280 | ||
281 | ||
282 | /** | |
283 | * ide_pci_enable - do PCI enables | |
284 | * @dev: PCI device | |
285 | * @d: IDE pci device data | |
286 | * | |
287 | * Enable the IDE PCI device. We attempt to enable the device in full | |
288 | * but if that fails then we only need BAR4 so we will enable that. | |
289 | * | |
290 | * Returns zero on success or an error code | |
291 | */ | |
292 | ||
293 | static int ide_pci_enable(struct pci_dev *dev, ide_pci_device_t *d) | |
294 | { | |
295 | int ret; | |
296 | ||
297 | if (pci_enable_device(dev)) { | |
298 | ret = pci_enable_device_bars(dev, 1 << 4); | |
299 | if (ret < 0) { | |
300 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
301 | "Could not enable device.\n", d->name); | |
302 | goto out; | |
303 | } | |
304 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
305 | } | |
306 | ||
307 | /* | |
308 | * assume all devices can do 32-bit dma for now. we can add a | |
309 | * dma mask field to the ide_pci_device_t if we need it (or let | |
310 | * lower level driver set the dma mask) | |
311 | */ | |
312 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
313 | if (ret < 0) { | |
314 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
315 | goto out; | |
316 | } | |
317 | ||
318 | /* FIXME: Temporary - until we put in the hotplug interface logic | |
319 | Check that the bits we want are not in use by someone else. */ | |
320 | ret = pci_request_region(dev, 4, "ide_tmp"); | |
321 | if (ret < 0) | |
322 | goto out; | |
323 | ||
324 | pci_release_region(dev, 4); | |
325 | out: | |
326 | return ret; | |
327 | } | |
328 | ||
329 | /** | |
330 | * ide_pci_configure - configure an unconfigured device | |
331 | * @dev: PCI device | |
332 | * @d: IDE pci device data | |
333 | * | |
334 | * Enable and configure the PCI device we have been passed. | |
335 | * Returns zero on success or an error code. | |
336 | */ | |
337 | ||
338 | static int ide_pci_configure(struct pci_dev *dev, ide_pci_device_t *d) | |
339 | { | |
340 | u16 pcicmd = 0; | |
341 | /* | |
342 | * PnP BIOS was *supposed* to have setup this device, but we | |
343 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
344 | * (or possibly the device is using a "legacy header" for IRQs). | |
345 | * Maybe the user deliberately *disabled* the device, | |
346 | * but we'll eventually ignore it again if no drives respond. | |
347 | */ | |
348 | if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO)) | |
349 | { | |
350 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); | |
351 | return -ENODEV; | |
352 | } | |
353 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
354 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
355 | return -EIO; | |
356 | } | |
357 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
358 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
359 | return -ENXIO; | |
360 | } | |
361 | return 0; | |
362 | } | |
363 | ||
364 | /** | |
365 | * ide_pci_check_iomem - check a register is I/O | |
366 | * @dev: pci device | |
367 | * @d: ide_pci_device | |
368 | * @bar: bar number | |
369 | * | |
370 | * Checks if a BAR is configured and points to MMIO space. If so | |
371 | * print an error and return an error code. Otherwise return 0 | |
372 | */ | |
373 | ||
374 | static int ide_pci_check_iomem(struct pci_dev *dev, ide_pci_device_t *d, int bar) | |
375 | { | |
376 | ulong flags = pci_resource_flags(dev, bar); | |
377 | ||
378 | /* Unconfigured ? */ | |
379 | if (!flags || pci_resource_len(dev, bar) == 0) | |
380 | return 0; | |
381 | ||
382 | /* I/O space */ | |
383 | if(flags & PCI_BASE_ADDRESS_IO_MASK) | |
384 | return 0; | |
385 | ||
386 | /* Bad */ | |
387 | printk(KERN_ERR "%s: IO baseregs (BIOS) are reported " | |
388 | "as MEM, report to " | |
389 | "<andre@linux-ide.org>.\n", d->name); | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
393 | /** | |
394 | * ide_hwif_configure - configure an IDE interface | |
395 | * @dev: PCI device holding interface | |
396 | * @d: IDE pci data | |
397 | * @mate: Paired interface if any | |
398 | * | |
399 | * Perform the initial set up for the hardware interface structure. This | |
400 | * is done per interface port rather than per PCI device. There may be | |
401 | * more than one port per device. | |
402 | * | |
403 | * Returns the new hardware interface structure, or NULL on a failure | |
404 | */ | |
405 | ||
406 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *mate, int port, int irq) | |
407 | { | |
408 | unsigned long ctl = 0, base = 0; | |
409 | ide_hwif_t *hwif; | |
410 | ||
411 | if ((d->flags & IDEPCI_FLAG_ISA_PORTS) == 0) { | |
412 | /* Possibly we should fail if these checks report true */ | |
413 | ide_pci_check_iomem(dev, d, 2*port); | |
414 | ide_pci_check_iomem(dev, d, 2*port+1); | |
415 | ||
416 | ctl = pci_resource_start(dev, 2*port+1); | |
417 | base = pci_resource_start(dev, 2*port); | |
418 | if ((ctl && !base) || (base && !ctl)) { | |
419 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
420 | "for port %d, skipping\n", d->name, port); | |
421 | return NULL; | |
422 | } | |
423 | } | |
424 | if (!ctl) | |
425 | { | |
426 | /* Use default values */ | |
427 | ctl = port ? 0x374 : 0x3f4; | |
428 | base = port ? 0x170 : 0x1f0; | |
429 | } | |
430 | if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL) | |
431 | return NULL; /* no room in ide_hwifs[] */ | |
432 | if (hwif->io_ports[IDE_DATA_OFFSET] != base || | |
433 | hwif->io_ports[IDE_CONTROL_OFFSET] != (ctl | 2)) { | |
434 | memset(&hwif->hw, 0, sizeof(hwif->hw)); | |
435 | #ifndef IDE_ARCH_OBSOLETE_INIT | |
436 | ide_std_init_ports(&hwif->hw, base, (ctl | 2)); | |
437 | hwif->hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
438 | #else | |
439 | ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL); | |
440 | #endif | |
441 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); | |
442 | hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; | |
443 | } | |
444 | hwif->chipset = ide_pci; | |
445 | hwif->pci_dev = dev; | |
446 | hwif->cds = (struct ide_pci_device_s *) d; | |
447 | hwif->channel = port; | |
448 | ||
449 | if (!hwif->irq) | |
450 | hwif->irq = irq; | |
451 | if (mate) { | |
452 | hwif->mate = mate; | |
453 | mate->mate = hwif; | |
454 | } | |
455 | return hwif; | |
456 | } | |
457 | ||
458 | /** | |
459 | * ide_hwif_setup_dma - configure DMA interface | |
460 | * @dev: PCI device | |
461 | * @d: IDE pci data | |
462 | * @hwif: Hardware interface we are configuring | |
463 | * | |
464 | * Set up the DMA base for the interface. Enable the master bits as | |
465 | * necessary and attempt to bring the device DMA into a ready to use | |
466 | * state | |
467 | */ | |
468 | ||
469 | #ifndef CONFIG_BLK_DEV_IDEDMA_PCI | |
470 | static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) | |
471 | { | |
472 | } | |
473 | #else | |
474 | static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) | |
475 | { | |
476 | u16 pcicmd; | |
477 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
478 | ||
479 | if ((d->autodma == AUTODMA) || | |
480 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && | |
481 | (dev->class & 0x80))) { | |
482 | unsigned long dma_base = ide_get_or_set_dma_base(hwif); | |
483 | if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { | |
484 | /* | |
485 | * Set up BM-DMA capability | |
486 | * (PnP BIOS should have done this) | |
487 | */ | |
488 | /* default DMA off if we had to configure it here */ | |
489 | hwif->autodma = 0; | |
490 | pci_set_master(dev); | |
491 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { | |
492 | printk(KERN_ERR "%s: %s error updating PCICMD\n", | |
493 | hwif->name, d->name); | |
494 | dma_base = 0; | |
495 | } | |
496 | } | |
497 | if (dma_base) { | |
498 | if (d->init_dma) { | |
499 | d->init_dma(hwif, dma_base); | |
500 | } else { | |
501 | ide_setup_dma(hwif, dma_base, 8); | |
502 | } | |
503 | } else { | |
504 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled " | |
505 | "(BIOS)\n", hwif->name, d->name); | |
506 | } | |
507 | } | |
508 | } | |
509 | ||
510 | #ifndef CONFIG_IDEDMA_PCI_AUTO | |
511 | #warning CONFIG_IDEDMA_PCI_AUTO=n support is obsolete, and will be removed soon. | |
512 | #endif | |
513 | ||
514 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/ | |
515 | ||
516 | /** | |
517 | * ide_setup_pci_controller - set up IDE PCI | |
518 | * @dev: PCI device | |
519 | * @d: IDE PCI data | |
520 | * @noisy: verbose flag | |
521 | * @config: returned as 1 if we configured the hardware | |
522 | * | |
523 | * Set up the PCI and controller side of the IDE interface. This brings | |
524 | * up the PCI side of the device, checks that the device is enabled | |
525 | * and enables it if need be | |
526 | */ | |
527 | ||
528 | static int ide_setup_pci_controller(struct pci_dev *dev, ide_pci_device_t *d, int noisy, int *config) | |
529 | { | |
530 | int ret; | |
531 | u32 class_rev; | |
532 | u16 pcicmd; | |
533 | ||
534 | if (noisy) | |
535 | ide_setup_pci_noise(dev, d); | |
536 | ||
537 | ret = ide_pci_enable(dev, d); | |
538 | if (ret < 0) | |
539 | goto out; | |
540 | ||
541 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
542 | if (ret < 0) { | |
543 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
544 | goto out; | |
545 | } | |
546 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
547 | ret = ide_pci_configure(dev, d); | |
548 | if (ret < 0) | |
549 | goto out; | |
550 | *config = 1; | |
551 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
552 | } | |
553 | ||
554 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
555 | class_rev &= 0xff; | |
556 | if (noisy) | |
557 | printk(KERN_INFO "%s: chipset revision %d\n", d->name, class_rev); | |
558 | out: | |
559 | return ret; | |
560 | } | |
561 | ||
562 | /** | |
563 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
564 | * @dev: PCI device | |
565 | * @d: IDE pci device info | |
566 | * @pciirq: IRQ line | |
567 | * @index: ata index to update | |
568 | * | |
569 | * Scan the interfaces attached to this device and do any | |
570 | * necessary per port setup. Attach the devices and ask the | |
571 | * generic DMA layer to do its work for us. | |
572 | * | |
573 | * Normally called automaticall from do_ide_pci_setup_device, | |
574 | * but is also used directly as a helper function by some controllers | |
575 | * where the chipset setup is not the default PCI IDE one. | |
576 | */ | |
577 | ||
578 | void ide_pci_setup_ports(struct pci_dev *dev, ide_pci_device_t *d, int pciirq, ata_index_t *index) | |
579 | { | |
580 | int port; | |
581 | int at_least_one_hwif_enabled = 0; | |
582 | ide_hwif_t *hwif, *mate = NULL; | |
583 | static int secondpdc = 0; | |
584 | u8 tmp; | |
585 | ||
586 | index->all = 0xf0f0; | |
587 | ||
588 | /* | |
589 | * Set up the IDE ports | |
590 | */ | |
591 | ||
592 | for (port = 0; port <= 1; ++port) { | |
593 | ide_pci_enablebit_t *e = &(d->enablebits[port]); | |
594 | ||
595 | /* | |
596 | * If this is a Promise FakeRaid controller, | |
597 | * the 2nd controller will be marked as | |
598 | * disabled while it is actually there and enabled | |
599 | * by the bios for raid purposes. | |
600 | * Skip the normal "is it enabled" test for those. | |
601 | */ | |
602 | if ((d->flags & IDEPCI_FLAG_FORCE_PDC) && | |
603 | (secondpdc++==1) && (port==1)) | |
604 | goto controller_ok; | |
605 | ||
606 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || | |
607 | (tmp & e->mask) != e->val)) | |
608 | continue; /* port not enabled */ | |
609 | controller_ok: | |
610 | ||
611 | if (d->channels <= port) | |
612 | break; | |
613 | ||
614 | if ((hwif = ide_hwif_configure(dev, d, mate, port, pciirq)) == NULL) | |
615 | continue; | |
616 | ||
617 | /* setup proper ancestral information */ | |
618 | hwif->gendev.parent = &dev->dev; | |
619 | ||
620 | if (hwif->channel) { | |
621 | index->b.high = hwif->index; | |
622 | } else { | |
623 | index->b.low = hwif->index; | |
624 | } | |
625 | ||
626 | ||
627 | if (d->init_iops) | |
628 | d->init_iops(hwif); | |
629 | ||
630 | if (d->autodma == NODMA) | |
631 | goto bypass_legacy_dma; | |
632 | ||
633 | if(d->init_setup_dma) | |
634 | d->init_setup_dma(dev, d, hwif); | |
635 | else | |
636 | ide_hwif_setup_dma(dev, d, hwif); | |
637 | bypass_legacy_dma: | |
638 | if (d->init_hwif) | |
639 | /* Call chipset-specific routine | |
640 | * for each enabled hwif | |
641 | */ | |
642 | d->init_hwif(hwif); | |
643 | ||
644 | mate = hwif; | |
645 | at_least_one_hwif_enabled = 1; | |
646 | } | |
647 | if (!at_least_one_hwif_enabled) | |
648 | printk(KERN_INFO "%s: neither IDE port enabled (BIOS)\n", d->name); | |
649 | } | |
650 | ||
651 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); | |
652 | ||
653 | /* | |
654 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
655 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
656 | * for use with them. This generic code works for most PCI chipsets. | |
657 | * | |
658 | * One thing that is not standardized is the location of the | |
659 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
660 | * we "know" about, this information is in the ide_pci_device_t struct; | |
661 | * for all other chipsets, we just assume both interfaces are enabled. | |
662 | */ | |
663 | static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d, | |
664 | ata_index_t *index, u8 noisy) | |
665 | { | |
666 | static ata_index_t ata_index = { .b = { .low = 0xff, .high = 0xff } }; | |
667 | int tried_config = 0; | |
668 | int pciirq, ret; | |
669 | ||
670 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
671 | if (ret < 0) | |
672 | goto out; | |
673 | ||
674 | /* | |
675 | * Can we trust the reported IRQ? | |
676 | */ | |
677 | pciirq = dev->irq; | |
678 | ||
679 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
680 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
681 | if (noisy) | |
682 | printk(KERN_INFO "%s: not 100%% native mode: " | |
683 | "will probe irqs later\n", d->name); | |
684 | /* | |
685 | * This allows offboard ide-pci cards the enable a BIOS, | |
686 | * verify interrupt settings of split-mirror pci-config | |
687 | * space, place chipset into init-mode, and/or preserve | |
688 | * an interrupt if the card is not native ide support. | |
689 | */ | |
690 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
691 | if (ret < 0) | |
692 | goto out; | |
693 | pciirq = ret; | |
694 | } else if (tried_config) { | |
695 | if (noisy) | |
696 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
697 | pciirq = 0; | |
698 | } else if (!pciirq) { | |
699 | if (noisy) | |
700 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
701 | d->name, pciirq); | |
702 | pciirq = 0; | |
703 | } else { | |
704 | if (d->init_chipset) { | |
705 | ret = d->init_chipset(dev, d->name); | |
706 | if (ret < 0) | |
707 | goto out; | |
708 | } | |
709 | if (noisy) | |
710 | #ifdef __sparc__ | |
711 | printk(KERN_INFO "%s: 100%% native mode on irq %s\n", | |
712 | d->name, __irq_itoa(pciirq)); | |
713 | #else | |
714 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", | |
715 | d->name, pciirq); | |
716 | #endif | |
717 | } | |
718 | ||
719 | /* FIXME: silent failure can happen */ | |
720 | ||
721 | *index = ata_index; | |
722 | ide_pci_setup_ports(dev, d, pciirq, index); | |
723 | out: | |
724 | return ret; | |
725 | } | |
726 | ||
727 | int ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d) | |
728 | { | |
729 | ata_index_t index_list; | |
730 | int ret; | |
731 | ||
732 | ret = do_ide_setup_pci_device(dev, d, &index_list, 1); | |
733 | if (ret < 0) | |
734 | goto out; | |
735 | ||
736 | if ((index_list.b.low & 0xf0) != 0xf0) | |
737 | probe_hwif_init_with_fixup(&ide_hwifs[index_list.b.low], d->fixup); | |
738 | if ((index_list.b.high & 0xf0) != 0xf0) | |
739 | probe_hwif_init_with_fixup(&ide_hwifs[index_list.b.high], d->fixup); | |
740 | ||
741 | create_proc_ide_interfaces(); | |
742 | out: | |
743 | return ret; | |
744 | } | |
745 | ||
746 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); | |
747 | ||
748 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
749 | ide_pci_device_t *d) | |
750 | { | |
751 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
752 | ata_index_t index_list[2]; | |
753 | int ret, i; | |
754 | ||
755 | for (i = 0; i < 2; i++) { | |
756 | ret = do_ide_setup_pci_device(pdev[i], d, index_list + i, !i); | |
757 | /* | |
758 | * FIXME: Mom, mom, they stole me the helper function to undo | |
759 | * do_ide_setup_pci_device() on the first device! | |
760 | */ | |
761 | if (ret < 0) | |
762 | goto out; | |
763 | } | |
764 | ||
765 | for (i = 0; i < 2; i++) { | |
766 | u8 idx[2] = { index_list[i].b.low, index_list[i].b.high }; | |
767 | int j; | |
768 | ||
769 | for (j = 0; j < 2; j++) { | |
770 | if ((idx[j] & 0xf0) != 0xf0) | |
771 | probe_hwif_init(ide_hwifs + idx[j]); | |
772 | } | |
773 | } | |
774 | ||
775 | create_proc_ide_interfaces(); | |
776 | out: | |
777 | return ret; | |
778 | } | |
779 | ||
780 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); | |
781 | ||
782 | /* | |
783 | * Module interfaces | |
784 | */ | |
785 | ||
786 | static int pre_init = 1; /* Before first ordered IDE scan */ | |
787 | static LIST_HEAD(ide_pci_drivers); | |
788 | ||
789 | /* | |
790 | * ide_register_pci_driver - attach IDE driver | |
791 | * @driver: pci driver | |
792 | * | |
793 | * Registers a driver with the IDE layer. The IDE layer arranges that | |
794 | * boot time setup is done in the expected device order and then | |
795 | * hands the controllers off to the core PCI code to do the rest of | |
796 | * the work. | |
797 | * | |
798 | * The driver_data of the driver table must point to an ide_pci_device_t | |
799 | * describing the interface. | |
800 | * | |
801 | * Returns are the same as for pci_register_driver | |
802 | */ | |
803 | ||
804 | int ide_pci_register_driver(struct pci_driver *driver) | |
805 | { | |
806 | if(!pre_init) | |
807 | return pci_module_init(driver); | |
808 | list_add_tail(&driver->node, &ide_pci_drivers); | |
809 | return 0; | |
810 | } | |
811 | ||
812 | EXPORT_SYMBOL_GPL(ide_pci_register_driver); | |
813 | ||
814 | /** | |
815 | * ide_unregister_pci_driver - unregister an IDE driver | |
816 | * @driver: driver to remove | |
817 | * | |
818 | * Unregister a currently installed IDE driver. Returns are the same | |
819 | * as for pci_unregister_driver | |
820 | */ | |
821 | ||
822 | void ide_pci_unregister_driver(struct pci_driver *driver) | |
823 | { | |
824 | if(!pre_init) | |
825 | pci_unregister_driver(driver); | |
826 | else | |
827 | list_del(&driver->node); | |
828 | } | |
829 | ||
830 | EXPORT_SYMBOL_GPL(ide_pci_unregister_driver); | |
831 | ||
832 | /** | |
833 | * ide_scan_pcidev - find an IDE driver for a device | |
834 | * @dev: PCI device to check | |
835 | * | |
836 | * Look for an IDE driver to handle the device we are considering. | |
837 | * This is only used during boot up to get the ordering correct. After | |
838 | * boot up the pci layer takes over the job. | |
839 | */ | |
840 | ||
841 | static int __init ide_scan_pcidev(struct pci_dev *dev) | |
842 | { | |
843 | struct list_head *l; | |
844 | struct pci_driver *d; | |
845 | ||
846 | list_for_each(l, &ide_pci_drivers) | |
847 | { | |
848 | d = list_entry(l, struct pci_driver, node); | |
849 | if(d->id_table) | |
850 | { | |
75865858 | 851 | const struct pci_device_id *id = pci_match_id(d->id_table, dev); |
1da177e4 LT |
852 | if(id != NULL) |
853 | { | |
854 | if(d->probe(dev, id) >= 0) | |
855 | { | |
856 | dev->driver = d; | |
857 | return 1; | |
858 | } | |
859 | } | |
860 | } | |
861 | } | |
862 | return 0; | |
863 | } | |
864 | ||
865 | /** | |
866 | * ide_scan_pcibus - perform the initial IDE driver scan | |
867 | * @scan_direction: set for reverse order scanning | |
868 | * | |
869 | * Perform the initial bus rather than driver ordered scan of the | |
870 | * PCI drivers. After this all IDE pci handling becomes standard | |
871 | * module ordering not traditionally ordered. | |
872 | */ | |
873 | ||
874 | void __init ide_scan_pcibus (int scan_direction) | |
875 | { | |
876 | struct pci_dev *dev = NULL; | |
877 | struct pci_driver *d; | |
878 | struct list_head *l, *n; | |
879 | ||
880 | pre_init = 0; | |
881 | if (!scan_direction) { | |
882 | while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
883 | ide_scan_pcidev(dev); | |
884 | } | |
885 | } else { | |
886 | while ((dev = pci_find_device_reverse(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
887 | ide_scan_pcidev(dev); | |
888 | } | |
889 | } | |
890 | ||
891 | /* | |
892 | * Hand the drivers over to the PCI layer now we | |
893 | * are post init. | |
894 | */ | |
895 | ||
896 | list_for_each_safe(l, n, &ide_pci_drivers) | |
897 | { | |
898 | list_del(l); | |
899 | d = list_entry(l, struct pci_driver, node); | |
900 | pci_register_driver(d); | |
901 | } | |
902 | } |