Commit | Line | Data |
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37897989 AN |
1 | /* |
2 | * TX4939 internal IDE driver | |
3 | * Based on RBTX49xx patch from CELF patch archive. | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file "COPYING" in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * (C) Copyright TOSHIBA CORPORATION 2005-2007 | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ide.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/scatterlist.h> | |
20 | ||
21 | #define MODNAME "tx4939ide" | |
22 | ||
23 | /* ATA Shadow Registers (8-bit except for Data which is 16-bit) */ | |
24 | #define TX4939IDE_Data 0x000 | |
25 | #define TX4939IDE_Error_Feature 0x001 | |
26 | #define TX4939IDE_Sec 0x002 | |
27 | #define TX4939IDE_LBA0 0x003 | |
28 | #define TX4939IDE_LBA1 0x004 | |
29 | #define TX4939IDE_LBA2 0x005 | |
30 | #define TX4939IDE_DevHead 0x006 | |
31 | #define TX4939IDE_Stat_Cmd 0x007 | |
32 | #define TX4939IDE_AltStat_DevCtl 0x402 | |
33 | /* H/W DMA Registers */ | |
34 | #define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */ | |
35 | #define TX4939IDE_DMA_Stat 0x802 /* 8-bit */ | |
36 | #define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */ | |
37 | /* ATA100 CORE Registers (16-bit) */ | |
38 | #define TX4939IDE_Sys_Ctl 0xc00 | |
39 | #define TX4939IDE_Xfer_Cnt_1 0xc08 | |
40 | #define TX4939IDE_Xfer_Cnt_2 0xc0a | |
41 | #define TX4939IDE_Sec_Cnt 0xc10 | |
42 | #define TX4939IDE_Start_Lo_Addr 0xc18 | |
43 | #define TX4939IDE_Start_Up_Addr 0xc20 | |
44 | #define TX4939IDE_Add_Ctl 0xc28 | |
45 | #define TX4939IDE_Lo_Burst_Cnt 0xc30 | |
46 | #define TX4939IDE_Up_Burst_Cnt 0xc38 | |
47 | #define TX4939IDE_PIO_Addr 0xc88 | |
48 | #define TX4939IDE_H_Rst_Tim 0xc90 | |
49 | #define TX4939IDE_Int_Ctl 0xc98 | |
50 | #define TX4939IDE_Pkt_Cmd 0xcb8 | |
51 | #define TX4939IDE_Bxfer_Cnt_Hi 0xcc0 | |
52 | #define TX4939IDE_Bxfer_Cnt_Lo 0xcc8 | |
53 | #define TX4939IDE_Dev_TErr 0xcd0 | |
54 | #define TX4939IDE_Pkt_Xfer_Ctl 0xcd8 | |
55 | #define TX4939IDE_Start_TAddr 0xce0 | |
56 | ||
57 | /* bits for Int_Ctl */ | |
58 | #define TX4939IDE_INT_ADDRERR 0x80 | |
59 | #define TX4939IDE_INT_REACHMUL 0x40 | |
60 | #define TX4939IDE_INT_DEVTIMING 0x20 | |
61 | #define TX4939IDE_INT_UDMATERM 0x10 | |
62 | #define TX4939IDE_INT_TIMER 0x08 | |
63 | #define TX4939IDE_INT_BUSERR 0x04 | |
64 | #define TX4939IDE_INT_XFEREND 0x02 | |
65 | #define TX4939IDE_INT_HOST 0x01 | |
66 | ||
67 | #define TX4939IDE_IGNORE_INTS \ | |
68 | (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \ | |
69 | TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \ | |
70 | TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND) | |
71 | ||
72 | #ifdef __BIG_ENDIAN | |
73 | #define tx4939ide_swizzlel(a) ((a) ^ 4) | |
74 | #define tx4939ide_swizzlew(a) ((a) ^ 6) | |
75 | #define tx4939ide_swizzleb(a) ((a) ^ 7) | |
76 | #else | |
77 | #define tx4939ide_swizzlel(a) (a) | |
78 | #define tx4939ide_swizzlew(a) (a) | |
79 | #define tx4939ide_swizzleb(a) (a) | |
80 | #endif | |
81 | ||
82 | static u16 tx4939ide_readw(void __iomem *base, u32 reg) | |
83 | { | |
84 | return __raw_readw(base + tx4939ide_swizzlew(reg)); | |
85 | } | |
86 | static u8 tx4939ide_readb(void __iomem *base, u32 reg) | |
87 | { | |
88 | return __raw_readb(base + tx4939ide_swizzleb(reg)); | |
89 | } | |
90 | static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) | |
91 | { | |
92 | __raw_writel(val, base + tx4939ide_swizzlel(reg)); | |
93 | } | |
94 | static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) | |
95 | { | |
96 | __raw_writew(val, base + tx4939ide_swizzlew(reg)); | |
97 | } | |
98 | static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) | |
99 | { | |
100 | __raw_writeb(val, base + tx4939ide_swizzleb(reg)); | |
101 | } | |
102 | ||
103 | #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base) | |
104 | ||
105 | static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
106 | { | |
107 | ide_hwif_t *hwif = drive->hwif; | |
108 | int is_slave = drive->dn; | |
109 | u32 mask, val; | |
110 | u8 safe = pio; | |
111 | ide_drive_t *pair; | |
112 | ||
113 | pair = ide_get_pair_dev(drive); | |
114 | if (pair) | |
115 | safe = min(safe, ide_get_best_pio_mode(pair, 255, 4)); | |
116 | /* | |
117 | * Update Command Transfer Mode for master/slave and Data | |
118 | * Transfer Mode for this drive. | |
119 | */ | |
120 | mask = is_slave ? 0x07f00000 : 0x000007f0; | |
121 | val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0); | |
122 | hwif->select_data = (hwif->select_data & ~mask) | val; | |
123 | /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ | |
124 | } | |
125 | ||
126 | static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode) | |
127 | { | |
128 | ide_hwif_t *hwif = drive->hwif; | |
129 | u32 mask, val; | |
130 | ||
131 | /* Update Data Transfer Mode for this drive. */ | |
132 | if (mode >= XFER_UDMA_0) | |
133 | val = mode - XFER_UDMA_0 + 8; | |
134 | else | |
135 | val = mode - XFER_MW_DMA_0 + 5; | |
136 | if (drive->dn) { | |
137 | mask = 0x00f00000; | |
138 | val <<= 20; | |
139 | } else { | |
140 | mask = 0x000000f0; | |
141 | val <<= 4; | |
142 | } | |
143 | hwif->select_data = (hwif->select_data & ~mask) | val; | |
144 | /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ | |
145 | } | |
146 | ||
147 | static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif) | |
148 | { | |
149 | void __iomem *base = TX4939IDE_BASE(hwif); | |
150 | u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); | |
151 | ||
152 | if (ctl & TX4939IDE_INT_BUSERR) { | |
153 | /* reset FIFO */ | |
154 | u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl); | |
155 | ||
156 | tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl); | |
157 | mmiowb(); | |
158 | /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */ | |
159 | ndelay(270); | |
160 | tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); | |
161 | } | |
162 | if (ctl & (TX4939IDE_INT_ADDRERR | | |
163 | TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR)) | |
164 | pr_err("%s: Error interrupt %#x (%s%s%s )\n", | |
165 | hwif->name, ctl, | |
166 | ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "", | |
167 | ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "", | |
168 | ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : ""); | |
169 | return ctl; | |
170 | } | |
171 | ||
172 | static void tx4939ide_clear_irq(ide_drive_t *drive) | |
173 | { | |
174 | ide_hwif_t *hwif; | |
175 | void __iomem *base; | |
176 | u16 ctl; | |
177 | ||
178 | /* | |
179 | * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job | |
180 | * for DMA case. | |
181 | */ | |
182 | if (drive->waiting_for_dma) | |
183 | return; | |
184 | hwif = drive->hwif; | |
185 | base = TX4939IDE_BASE(hwif); | |
186 | ctl = tx4939ide_check_error_ints(hwif); | |
187 | tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); | |
188 | } | |
189 | ||
190 | static u8 tx4939ide_cable_detect(ide_hwif_t *hwif) | |
191 | { | |
192 | void __iomem *base = TX4939IDE_BASE(hwif); | |
193 | ||
194 | return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ? | |
195 | ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
196 | } | |
197 | ||
198 | #ifdef __BIG_ENDIAN | |
199 | static void tx4939ide_dma_host_set(ide_drive_t *drive, int on) | |
200 | { | |
201 | ide_hwif_t *hwif = drive->hwif; | |
202 | u8 unit = drive->dn; | |
203 | void __iomem *base = TX4939IDE_BASE(hwif); | |
204 | u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); | |
205 | ||
206 | if (on) | |
207 | dma_stat |= (1 << (5 + unit)); | |
208 | else | |
209 | dma_stat &= ~(1 << (5 + unit)); | |
210 | ||
211 | tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat); | |
212 | } | |
213 | #else | |
214 | #define tx4939ide_dma_host_set ide_dma_host_set | |
215 | #endif | |
216 | ||
217 | static u8 tx4939ide_clear_dma_status(void __iomem *base) | |
218 | { | |
219 | u8 dma_stat; | |
220 | ||
221 | /* read DMA status for INTR & ERROR flags */ | |
222 | dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); | |
223 | /* clear INTR & ERROR flags */ | |
224 | tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base, | |
225 | TX4939IDE_DMA_Stat); | |
226 | /* recover intmask cleared by writing to bit2 of DMA_Stat */ | |
227 | tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl); | |
228 | return dma_stat; | |
229 | } | |
230 | ||
231 | #ifdef __BIG_ENDIAN | |
232 | /* custom ide_build_dmatable to handle swapped layout */ | |
233 | static int tx4939ide_build_dmatable(ide_drive_t *drive, struct request *rq) | |
234 | { | |
235 | ide_hwif_t *hwif = drive->hwif; | |
236 | u32 *table = (u32 *)hwif->dmatable_cpu; | |
237 | unsigned int count = 0; | |
238 | int i; | |
239 | struct scatterlist *sg; | |
240 | ||
241 | hwif->sg_nents = ide_build_sglist(drive, rq); | |
242 | if (hwif->sg_nents == 0) | |
243 | return 0; | |
244 | ||
245 | for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) { | |
246 | u32 cur_addr, cur_len, bcount; | |
247 | ||
248 | cur_addr = sg_dma_address(sg); | |
249 | cur_len = sg_dma_len(sg); | |
250 | ||
251 | /* | |
252 | * Fill in the DMA table, without crossing any 64kB boundaries. | |
253 | */ | |
254 | ||
255 | while (cur_len) { | |
256 | if (count++ >= PRD_ENTRIES) | |
257 | goto use_pio_instead; | |
258 | ||
259 | bcount = 0x10000 - (cur_addr & 0xffff); | |
260 | if (bcount > cur_len) | |
261 | bcount = cur_len; | |
a0fce792 AN |
262 | /* |
263 | * This workaround for zero count seems required. | |
9711a537 | 264 | * (standard ide_build_dmatable does it too) |
a0fce792 | 265 | */ |
9711a537 | 266 | if (bcount == 0x10000) |
a0fce792 | 267 | bcount = 0x8000; |
37897989 AN |
268 | *table++ = bcount & 0xffff; |
269 | *table++ = cur_addr; | |
270 | cur_addr += bcount; | |
271 | cur_len -= bcount; | |
272 | } | |
273 | } | |
274 | ||
275 | if (count) { | |
276 | *(table - 2) |= 0x80000000; | |
277 | return count; | |
278 | } | |
279 | ||
280 | use_pio_instead: | |
281 | printk(KERN_ERR "%s: %s\n", drive->name, | |
282 | count ? "DMA table too small" : "empty DMA table?"); | |
283 | ||
284 | ide_destroy_dmatable(drive); | |
285 | ||
286 | return 0; /* revert to PIO for this request */ | |
287 | } | |
288 | #else | |
289 | #define tx4939ide_build_dmatable ide_build_dmatable | |
290 | #endif | |
291 | ||
292 | static int tx4939ide_dma_setup(ide_drive_t *drive) | |
293 | { | |
294 | ide_hwif_t *hwif = drive->hwif; | |
295 | void __iomem *base = TX4939IDE_BASE(hwif); | |
b65fac32 | 296 | struct request *rq = hwif->rq; |
37897989 AN |
297 | u8 reading; |
298 | int nent; | |
299 | ||
300 | if (rq_data_dir(rq)) | |
301 | reading = 0; | |
302 | else | |
303 | reading = ATA_DMA_WR; | |
304 | ||
305 | /* fall back to PIO! */ | |
306 | nent = tx4939ide_build_dmatable(drive, rq); | |
307 | if (!nent) { | |
308 | ide_map_sg(drive, rq); | |
309 | return 1; | |
310 | } | |
311 | ||
312 | /* PRD table */ | |
313 | tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr); | |
314 | ||
315 | /* specify r/w */ | |
316 | tx4939ide_writeb(reading, base, TX4939IDE_DMA_Cmd); | |
317 | ||
318 | /* clear INTR & ERROR flags */ | |
319 | tx4939ide_clear_dma_status(base); | |
320 | ||
321 | drive->waiting_for_dma = 1; | |
322 | ||
323 | tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ? | |
324 | TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1); | |
325 | tx4939ide_writew(rq->nr_sectors, base, TX4939IDE_Sec_Cnt); | |
326 | return 0; | |
327 | } | |
328 | ||
329 | static int tx4939ide_dma_end(ide_drive_t *drive) | |
330 | { | |
331 | ide_hwif_t *hwif = drive->hwif; | |
332 | u8 dma_stat, dma_cmd; | |
333 | void __iomem *base = TX4939IDE_BASE(hwif); | |
334 | u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); | |
335 | ||
336 | drive->waiting_for_dma = 0; | |
337 | ||
338 | /* get DMA command mode */ | |
339 | dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd); | |
340 | /* stop DMA */ | |
341 | tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd); | |
342 | ||
343 | /* read and clear the INTR & ERROR bits */ | |
344 | dma_stat = tx4939ide_clear_dma_status(base); | |
345 | ||
346 | /* purge DMA mappings */ | |
347 | ide_destroy_dmatable(drive); | |
348 | /* verify good DMA status */ | |
349 | wmb(); | |
350 | ||
351 | if ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) == 0 && | |
352 | (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) == | |
353 | (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) | |
354 | /* INT_IDE lost... bug? */ | |
355 | return 0; | |
356 | return ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) != | |
357 | ATA_DMA_INTR) ? 0x10 | dma_stat : 0; | |
358 | } | |
359 | ||
360 | /* returns 1 if DMA IRQ issued, 0 otherwise */ | |
361 | static int tx4939ide_dma_test_irq(ide_drive_t *drive) | |
362 | { | |
363 | ide_hwif_t *hwif = drive->hwif; | |
364 | void __iomem *base = TX4939IDE_BASE(hwif); | |
365 | u16 ctl, ide_int; | |
366 | u8 dma_stat, stat; | |
367 | int found = 0; | |
368 | ||
369 | ctl = tx4939ide_check_error_ints(hwif); | |
370 | ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST); | |
371 | switch (ide_int) { | |
372 | case TX4939IDE_INT_HOST: | |
373 | /* On error, XFEREND might not be asserted. */ | |
374 | stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl); | |
375 | if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR) | |
376 | found = 1; | |
377 | else | |
378 | /* Wait for XFEREND (Mask HOST and unmask XFEREND) */ | |
379 | ctl &= ~TX4939IDE_INT_XFEREND << 8; | |
380 | ctl |= ide_int << 8; | |
381 | break; | |
382 | case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND: | |
383 | dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); | |
384 | if (!(dma_stat & ATA_DMA_INTR)) | |
385 | pr_warning("%s: weird interrupt status. " | |
386 | "DMA_Stat %#02x int_ctl %#04x\n", | |
387 | hwif->name, dma_stat, ctl); | |
388 | found = 1; | |
389 | break; | |
390 | } | |
391 | /* | |
392 | * Do not clear XFEREND, HOST now. They will be cleared by | |
393 | * clearing bit2 of DMA_Stat. | |
394 | */ | |
395 | ctl &= ~ide_int; | |
396 | tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); | |
397 | return found; | |
398 | } | |
399 | ||
592b5315 SS |
400 | #ifdef __BIG_ENDIAN |
401 | static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif) | |
402 | { | |
403 | void __iomem *base = TX4939IDE_BASE(hwif); | |
404 | ||
405 | return tx4939ide_readb(base, TX4939IDE_DMA_Stat); | |
406 | } | |
407 | #else | |
408 | #define tx4939ide_dma_sff_read_status ide_dma_sff_read_status | |
409 | #endif | |
410 | ||
37897989 AN |
411 | static void tx4939ide_init_hwif(ide_hwif_t *hwif) |
412 | { | |
413 | void __iomem *base = TX4939IDE_BASE(hwif); | |
414 | ||
415 | /* Soft Reset */ | |
416 | tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl); | |
417 | mmiowb(); | |
418 | /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */ | |
419 | ndelay(450); | |
420 | tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl); | |
421 | /* mask some interrupts and clear all interrupts */ | |
422 | tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, | |
423 | TX4939IDE_Int_Ctl); | |
424 | ||
425 | tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt); | |
426 | tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt); | |
427 | } | |
428 | ||
429 | static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d) | |
430 | { | |
431 | hwif->dma_base = | |
432 | hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd); | |
433 | /* | |
434 | * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS | |
435 | * for big endian. | |
436 | */ | |
437 | return ide_allocate_dma_engine(hwif); | |
438 | } | |
439 | ||
440 | static void tx4939ide_tf_load_fixup(ide_drive_t *drive, ide_task_t *task) | |
441 | { | |
442 | ide_hwif_t *hwif = drive->hwif; | |
443 | void __iomem *base = TX4939IDE_BASE(hwif); | |
444 | u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0); | |
445 | ||
446 | /* | |
447 | * Fix ATA100 CORE System Control Register. (The write to the | |
448 | * Device/Head register may write wrong data to the System | |
449 | * Control Register) | |
450 | * While Sys_Ctl is written here, selectproc is not needed. | |
451 | */ | |
452 | tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); | |
453 | } | |
454 | ||
455 | #ifdef __BIG_ENDIAN | |
456 | ||
37897989 AN |
457 | /* custom iops (independent from SWAP_IO_SPACE) */ |
458 | static u8 tx4939ide_inb(unsigned long port) | |
459 | { | |
460 | return __raw_readb((void __iomem *)port); | |
461 | } | |
462 | ||
463 | static void tx4939ide_outb(u8 value, unsigned long port) | |
464 | { | |
465 | __raw_writeb(value, (void __iomem *)port); | |
466 | } | |
467 | ||
468 | static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task) | |
469 | { | |
470 | ide_hwif_t *hwif = drive->hwif; | |
471 | struct ide_io_ports *io_ports = &hwif->io_ports; | |
472 | struct ide_taskfile *tf = &task->tf; | |
473 | u8 HIHI = task->tf_flags & IDE_TFLAG_LBA48 ? 0xE0 : 0xEF; | |
474 | ||
475 | if (task->tf_flags & IDE_TFLAG_FLAGGED) | |
476 | HIHI = 0xFF; | |
477 | ||
478 | if (task->tf_flags & IDE_TFLAG_OUT_DATA) { | |
479 | u16 data = (tf->hob_data << 8) | tf->data; | |
480 | ||
481 | /* no endian swap */ | |
482 | __raw_writew(data, (void __iomem *)io_ports->data_addr); | |
483 | } | |
484 | ||
485 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) | |
486 | tx4939ide_outb(tf->hob_feature, io_ports->feature_addr); | |
487 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) | |
488 | tx4939ide_outb(tf->hob_nsect, io_ports->nsect_addr); | |
489 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) | |
490 | tx4939ide_outb(tf->hob_lbal, io_ports->lbal_addr); | |
491 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) | |
492 | tx4939ide_outb(tf->hob_lbam, io_ports->lbam_addr); | |
493 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) | |
494 | tx4939ide_outb(tf->hob_lbah, io_ports->lbah_addr); | |
495 | ||
496 | if (task->tf_flags & IDE_TFLAG_OUT_FEATURE) | |
497 | tx4939ide_outb(tf->feature, io_ports->feature_addr); | |
498 | if (task->tf_flags & IDE_TFLAG_OUT_NSECT) | |
499 | tx4939ide_outb(tf->nsect, io_ports->nsect_addr); | |
500 | if (task->tf_flags & IDE_TFLAG_OUT_LBAL) | |
501 | tx4939ide_outb(tf->lbal, io_ports->lbal_addr); | |
502 | if (task->tf_flags & IDE_TFLAG_OUT_LBAM) | |
503 | tx4939ide_outb(tf->lbam, io_ports->lbam_addr); | |
504 | if (task->tf_flags & IDE_TFLAG_OUT_LBAH) | |
505 | tx4939ide_outb(tf->lbah, io_ports->lbah_addr); | |
506 | ||
507 | if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) { | |
508 | tx4939ide_outb((tf->device & HIHI) | drive->select, | |
509 | io_ports->device_addr); | |
510 | tx4939ide_tf_load_fixup(drive, task); | |
511 | } | |
512 | } | |
513 | ||
514 | static void tx4939ide_tf_read(ide_drive_t *drive, ide_task_t *task) | |
515 | { | |
516 | ide_hwif_t *hwif = drive->hwif; | |
517 | struct ide_io_ports *io_ports = &hwif->io_ports; | |
518 | struct ide_taskfile *tf = &task->tf; | |
519 | ||
520 | if (task->tf_flags & IDE_TFLAG_IN_DATA) { | |
521 | u16 data; | |
522 | ||
523 | /* no endian swap */ | |
524 | data = __raw_readw((void __iomem *)io_ports->data_addr); | |
525 | tf->data = data & 0xff; | |
526 | tf->hob_data = (data >> 8) & 0xff; | |
527 | } | |
528 | ||
529 | /* be sure we're looking at the low order bits */ | |
530 | tx4939ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); | |
531 | ||
532 | if (task->tf_flags & IDE_TFLAG_IN_FEATURE) | |
533 | tf->feature = tx4939ide_inb(io_ports->feature_addr); | |
534 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) | |
535 | tf->nsect = tx4939ide_inb(io_ports->nsect_addr); | |
536 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | |
537 | tf->lbal = tx4939ide_inb(io_ports->lbal_addr); | |
538 | if (task->tf_flags & IDE_TFLAG_IN_LBAM) | |
539 | tf->lbam = tx4939ide_inb(io_ports->lbam_addr); | |
540 | if (task->tf_flags & IDE_TFLAG_IN_LBAH) | |
541 | tf->lbah = tx4939ide_inb(io_ports->lbah_addr); | |
542 | if (task->tf_flags & IDE_TFLAG_IN_DEVICE) | |
543 | tf->device = tx4939ide_inb(io_ports->device_addr); | |
544 | ||
545 | if (task->tf_flags & IDE_TFLAG_LBA48) { | |
546 | tx4939ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); | |
547 | ||
548 | if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) | |
549 | tf->hob_feature = | |
550 | tx4939ide_inb(io_ports->feature_addr); | |
551 | if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) | |
552 | tf->hob_nsect = tx4939ide_inb(io_ports->nsect_addr); | |
553 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) | |
554 | tf->hob_lbal = tx4939ide_inb(io_ports->lbal_addr); | |
555 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) | |
556 | tf->hob_lbam = tx4939ide_inb(io_ports->lbam_addr); | |
557 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) | |
558 | tf->hob_lbah = tx4939ide_inb(io_ports->lbah_addr); | |
559 | } | |
560 | } | |
561 | ||
562 | static void tx4939ide_input_data_swap(ide_drive_t *drive, struct request *rq, | |
563 | void *buf, unsigned int len) | |
564 | { | |
565 | unsigned long port = drive->hwif->io_ports.data_addr; | |
566 | unsigned short *ptr = buf; | |
567 | unsigned int count = (len + 1) / 2; | |
568 | ||
569 | while (count--) | |
570 | *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port)); | |
f26f6cea | 571 | __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); |
37897989 AN |
572 | } |
573 | ||
574 | static void tx4939ide_output_data_swap(ide_drive_t *drive, struct request *rq, | |
575 | void *buf, unsigned int len) | |
576 | { | |
577 | unsigned long port = drive->hwif->io_ports.data_addr; | |
578 | unsigned short *ptr = buf; | |
579 | unsigned int count = (len + 1) / 2; | |
580 | ||
581 | while (count--) { | |
582 | __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port); | |
583 | ptr++; | |
584 | } | |
f26f6cea | 585 | __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); |
37897989 AN |
586 | } |
587 | ||
588 | static const struct ide_tp_ops tx4939ide_tp_ops = { | |
589 | .exec_command = ide_exec_command, | |
590 | .read_status = ide_read_status, | |
591 | .read_altstatus = ide_read_altstatus, | |
37897989 AN |
592 | |
593 | .set_irq = ide_set_irq, | |
594 | ||
595 | .tf_load = tx4939ide_tf_load, | |
596 | .tf_read = tx4939ide_tf_read, | |
597 | ||
598 | .input_data = tx4939ide_input_data_swap, | |
599 | .output_data = tx4939ide_output_data_swap, | |
600 | }; | |
601 | ||
602 | #else /* __LITTLE_ENDIAN */ | |
603 | ||
604 | static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task) | |
605 | { | |
606 | ide_tf_load(drive, task); | |
607 | if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) | |
608 | tx4939ide_tf_load_fixup(drive, task); | |
609 | } | |
610 | ||
611 | static const struct ide_tp_ops tx4939ide_tp_ops = { | |
612 | .exec_command = ide_exec_command, | |
613 | .read_status = ide_read_status, | |
614 | .read_altstatus = ide_read_altstatus, | |
37897989 AN |
615 | |
616 | .set_irq = ide_set_irq, | |
617 | ||
618 | .tf_load = tx4939ide_tf_load, | |
619 | .tf_read = ide_tf_read, | |
620 | ||
621 | .input_data = ide_input_data, | |
622 | .output_data = ide_output_data, | |
623 | }; | |
624 | ||
625 | #endif /* __LITTLE_ENDIAN */ | |
626 | ||
627 | static const struct ide_port_ops tx4939ide_port_ops = { | |
3ee86dcd BZ |
628 | .set_pio_mode = tx4939ide_set_pio_mode, |
629 | .set_dma_mode = tx4939ide_set_dma_mode, | |
630 | .clear_irq = tx4939ide_clear_irq, | |
631 | .cable_detect = tx4939ide_cable_detect, | |
37897989 AN |
632 | }; |
633 | ||
634 | static const struct ide_dma_ops tx4939ide_dma_ops = { | |
3ee86dcd BZ |
635 | .dma_host_set = tx4939ide_dma_host_set, |
636 | .dma_setup = tx4939ide_dma_setup, | |
637 | .dma_exec_cmd = ide_dma_exec_cmd, | |
638 | .dma_start = ide_dma_start, | |
639 | .dma_end = tx4939ide_dma_end, | |
640 | .dma_test_irq = tx4939ide_dma_test_irq, | |
641 | .dma_lost_irq = ide_dma_lost_irq, | |
642 | .dma_timeout = ide_dma_timeout, | |
592b5315 | 643 | .dma_sff_read_status = tx4939ide_dma_sff_read_status, |
37897989 AN |
644 | }; |
645 | ||
646 | static const struct ide_port_info tx4939ide_port_info __initdata = { | |
3ee86dcd BZ |
647 | .init_hwif = tx4939ide_init_hwif, |
648 | .init_dma = tx4939ide_init_dma, | |
649 | .port_ops = &tx4939ide_port_ops, | |
650 | .dma_ops = &tx4939ide_dma_ops, | |
651 | .tp_ops = &tx4939ide_tp_ops, | |
652 | .host_flags = IDE_HFLAG_MMIO, | |
653 | .pio_mask = ATA_PIO4, | |
654 | .mwdma_mask = ATA_MWDMA2, | |
655 | .udma_mask = ATA_UDMA5, | |
b1d249e8 | 656 | .chipset = ide_generic, |
37897989 AN |
657 | }; |
658 | ||
659 | static int __init tx4939ide_probe(struct platform_device *pdev) | |
660 | { | |
661 | hw_regs_t hw; | |
662 | hw_regs_t *hws[] = { &hw, NULL, NULL, NULL }; | |
663 | struct ide_host *host; | |
664 | struct resource *res; | |
665 | int irq, ret; | |
666 | unsigned long mapbase; | |
667 | ||
668 | irq = platform_get_irq(pdev, 0); | |
669 | if (irq < 0) | |
670 | return -ENODEV; | |
671 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
672 | if (!res) | |
673 | return -ENODEV; | |
674 | ||
675 | if (!devm_request_mem_region(&pdev->dev, res->start, | |
676 | res->end - res->start + 1, "tx4938ide")) | |
677 | return -EBUSY; | |
678 | mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start, | |
679 | res->end - res->start + 1); | |
680 | if (!mapbase) | |
681 | return -EBUSY; | |
682 | memset(&hw, 0, sizeof(hw)); | |
683 | hw.io_ports.data_addr = | |
684 | mapbase + tx4939ide_swizzlew(TX4939IDE_Data); | |
685 | hw.io_ports.error_addr = | |
686 | mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature); | |
687 | hw.io_ports.nsect_addr = | |
688 | mapbase + tx4939ide_swizzleb(TX4939IDE_Sec); | |
689 | hw.io_ports.lbal_addr = | |
690 | mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0); | |
691 | hw.io_ports.lbam_addr = | |
692 | mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1); | |
693 | hw.io_ports.lbah_addr = | |
694 | mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2); | |
695 | hw.io_ports.device_addr = | |
696 | mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead); | |
697 | hw.io_ports.command_addr = | |
698 | mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd); | |
699 | hw.io_ports.ctl_addr = | |
700 | mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl); | |
701 | hw.irq = irq; | |
702 | hw.dev = &pdev->dev; | |
703 | ||
704 | pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq); | |
705 | host = ide_host_alloc(&tx4939ide_port_info, hws); | |
706 | if (!host) | |
707 | return -ENOMEM; | |
708 | /* use extra_base for base address of the all registers */ | |
709 | host->ports[0]->extra_base = mapbase; | |
710 | ret = ide_host_register(host, &tx4939ide_port_info, hws); | |
711 | if (ret) { | |
712 | ide_host_free(host); | |
713 | return ret; | |
714 | } | |
715 | platform_set_drvdata(pdev, host); | |
716 | return 0; | |
717 | } | |
718 | ||
719 | static int __exit tx4939ide_remove(struct platform_device *pdev) | |
720 | { | |
721 | struct ide_host *host = platform_get_drvdata(pdev); | |
722 | ||
723 | ide_host_remove(host); | |
724 | return 0; | |
725 | } | |
726 | ||
727 | #ifdef CONFIG_PM | |
728 | static int tx4939ide_resume(struct platform_device *dev) | |
729 | { | |
730 | struct ide_host *host = platform_get_drvdata(dev); | |
731 | ide_hwif_t *hwif = host->ports[0]; | |
732 | ||
733 | tx4939ide_init_hwif(hwif); | |
734 | return 0; | |
735 | } | |
736 | #else | |
737 | #define tx4939ide_resume NULL | |
738 | #endif | |
739 | ||
740 | static struct platform_driver tx4939ide_driver = { | |
741 | .driver = { | |
742 | .name = MODNAME, | |
743 | .owner = THIS_MODULE, | |
744 | }, | |
745 | .remove = __exit_p(tx4939ide_remove), | |
746 | .resume = tx4939ide_resume, | |
747 | }; | |
748 | ||
749 | static int __init tx4939ide_init(void) | |
750 | { | |
751 | return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe); | |
752 | } | |
753 | ||
754 | static void __exit tx4939ide_exit(void) | |
755 | { | |
756 | platform_driver_unregister(&tx4939ide_driver); | |
757 | } | |
758 | ||
759 | module_init(tx4939ide_init); | |
760 | module_exit(tx4939ide_exit); | |
761 | ||
762 | MODULE_DESCRIPTION("TX4939 internal IDE driver"); | |
763 | MODULE_LICENSE("GPL"); | |
764 | MODULE_ALIAS("platform:tx4939ide"); |